1 /* $NetBSD: be.c,v 1.29 2001/11/13 06:58:16 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.29 2001/11/13 06:58:16 lukem Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_inet.h" 71 #include "opt_ccitt.h" 72 #include "opt_llc.h" 73 #include "opt_ns.h" 74 #include "bpfilter.h" 75 #include "rnd.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/callout.h> 80 #include <sys/kernel.h> 81 #include <sys/errno.h> 82 #include <sys/ioctl.h> 83 #include <sys/mbuf.h> 84 #include <sys/socket.h> 85 #include <sys/syslog.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #if NRND > 0 89 #include <sys/rnd.h> 90 #endif 91 92 #include <net/if.h> 93 #include <net/if_dl.h> 94 #include <net/if_types.h> 95 #include <net/netisr.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_inarp.h> 102 #include <netinet/in_systm.h> 103 #include <netinet/in_var.h> 104 #include <netinet/ip.h> 105 #endif 106 107 #ifdef NS 108 #include <netns/ns.h> 109 #include <netns/ns_if.h> 110 #endif 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #include <net/bpfdesc.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 #include <machine/autoconf.h> 120 121 #include <dev/sbus/sbusvar.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/sbus/qecreg.h> 127 #include <dev/sbus/qecvar.h> 128 #include <dev/sbus/bereg.h> 129 130 struct be_softc { 131 struct device sc_dev; 132 struct sbusdev sc_sd; /* sbus device */ 133 bus_space_tag_t sc_bustag; /* bus & dma tags */ 134 bus_dma_tag_t sc_dmatag; 135 bus_dmamap_t sc_dmamap; 136 struct ethercom sc_ethercom; 137 /*struct ifmedia sc_ifmedia; -* interface media */ 138 struct mii_data sc_mii; /* MII media control */ 139 #define sc_media sc_mii.mii_media/* shorthand */ 140 int sc_phys[2]; /* MII instance -> phy */ 141 142 struct callout sc_tick_ch; 143 144 /* 145 * Some `mii_softc' items we need to emulate MII operation 146 * for our internal transceiver. 147 */ 148 int sc_mii_inst; /* instance of internal phy */ 149 int sc_mii_active; /* currently active medium */ 150 int sc_mii_ticks; /* tick counter */ 151 int sc_mii_flags; /* phy status flags */ 152 #define MIIF_HAVELINK 0x04000000 153 int sc_intphy_curspeed; /* Established link speed */ 154 155 struct qec_softc *sc_qec; /* QEC parent */ 156 157 bus_space_handle_t sc_qr; /* QEC registers */ 158 bus_space_handle_t sc_br; /* BE registers */ 159 bus_space_handle_t sc_cr; /* channel registers */ 160 bus_space_handle_t sc_tr; /* transceiver registers */ 161 162 u_int sc_rev; 163 164 int sc_channel; /* channel number */ 165 int sc_burst; 166 167 struct qec_ring sc_rb; /* Packet Ring Buffer */ 168 169 /* MAC address */ 170 u_int8_t sc_enaddr[6]; 171 }; 172 173 int bematch __P((struct device *, struct cfdata *, void *)); 174 void beattach __P((struct device *, struct device *, void *)); 175 176 void beinit __P((struct be_softc *)); 177 void bestart __P((struct ifnet *)); 178 void bestop __P((struct be_softc *)); 179 void bewatchdog __P((struct ifnet *)); 180 int beioctl __P((struct ifnet *, u_long, caddr_t)); 181 void bereset __P((struct be_softc *)); 182 183 int beintr __P((void *)); 184 int berint __P((struct be_softc *)); 185 int betint __P((struct be_softc *)); 186 int beqint __P((struct be_softc *, u_int32_t)); 187 int beeint __P((struct be_softc *, u_int32_t)); 188 189 static void be_read __P((struct be_softc *, int, int)); 190 static int be_put __P((struct be_softc *, int, struct mbuf *)); 191 static struct mbuf *be_get __P((struct be_softc *, int, int)); 192 193 void be_pal_gate __P((struct be_softc *, int)); 194 195 /* ifmedia callbacks */ 196 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 197 int be_ifmedia_upd __P((struct ifnet *)); 198 199 void be_mcreset __P((struct be_softc *)); 200 201 /* MII methods & callbacks */ 202 static int be_mii_readreg __P((struct device *, int, int)); 203 static void be_mii_writereg __P((struct device *, int, int, int)); 204 static void be_mii_statchg __P((struct device *)); 205 206 /* MII helpers */ 207 static void be_mii_sync __P((struct be_softc *)); 208 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 209 static int be_mii_reset __P((struct be_softc *, int)); 210 static int be_tcvr_read_bit __P((struct be_softc *, int)); 211 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 212 213 void be_tick __P((void *)); 214 void be_intphy_auto __P((struct be_softc *)); 215 void be_intphy_status __P((struct be_softc *)); 216 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 217 218 219 struct cfattach be_ca = { 220 sizeof(struct be_softc), bematch, beattach 221 }; 222 223 int 224 bematch(parent, cf, aux) 225 struct device *parent; 226 struct cfdata *cf; 227 void *aux; 228 { 229 struct sbus_attach_args *sa = aux; 230 231 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 232 } 233 234 void 235 beattach(parent, self, aux) 236 struct device *parent, *self; 237 void *aux; 238 { 239 struct sbus_attach_args *sa = aux; 240 struct qec_softc *qec = (struct qec_softc *)parent; 241 struct be_softc *sc = (struct be_softc *)self; 242 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 243 struct mii_data *mii = &sc->sc_mii; 244 struct mii_softc *child; 245 int node = sa->sa_node; 246 bus_dma_tag_t dmatag = sa->sa_dmatag; 247 bus_dma_segment_t seg; 248 bus_size_t size; 249 int instance; 250 int rseg, error; 251 u_int32_t v; 252 extern void myetheraddr __P((u_char *)); 253 254 if (sa->sa_nreg < 3) { 255 printf("%s: only %d register sets\n", 256 self->dv_xname, sa->sa_nreg); 257 return; 258 } 259 260 if (bus_space_map2(sa->sa_bustag, 261 (bus_type_t)sa->sa_reg[0].sbr_slot, 262 (bus_addr_t)sa->sa_reg[0].sbr_offset, 263 (bus_size_t)sa->sa_reg[0].sbr_size, 264 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 265 printf("beattach: cannot map registers\n"); 266 return; 267 } 268 269 if (bus_space_map2(sa->sa_bustag, 270 (bus_type_t)sa->sa_reg[1].sbr_slot, 271 (bus_addr_t)sa->sa_reg[1].sbr_offset, 272 (bus_size_t)sa->sa_reg[1].sbr_size, 273 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 274 printf("beattach: cannot map registers\n"); 275 return; 276 } 277 278 if (bus_space_map2(sa->sa_bustag, 279 (bus_type_t)sa->sa_reg[2].sbr_slot, 280 (bus_addr_t)sa->sa_reg[2].sbr_offset, 281 (bus_size_t)sa->sa_reg[2].sbr_size, 282 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 283 printf("beattach: cannot map registers\n"); 284 return; 285 } 286 287 sc->sc_bustag = sa->sa_bustag; 288 sc->sc_qec = qec; 289 sc->sc_qr = qec->sc_regs; 290 291 sc->sc_rev = PROM_getpropint(node, "board-version", -1); 292 printf(" rev %x", sc->sc_rev); 293 294 bestop(sc); 295 296 sc->sc_channel = PROM_getpropint(node, "channel#", -1); 297 if (sc->sc_channel == -1) 298 sc->sc_channel = 0; 299 300 sc->sc_burst = PROM_getpropint(node, "burst-sizes", -1); 301 if (sc->sc_burst == -1) 302 sc->sc_burst = qec->sc_burst; 303 304 /* Clamp at parent's burst sizes */ 305 sc->sc_burst &= qec->sc_burst; 306 307 /* Establish interrupt handler */ 308 if (sa->sa_nintr) 309 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 310 0, beintr, sc); 311 312 myetheraddr(sc->sc_enaddr); 313 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 314 315 /* 316 * Allocate descriptor ring and buffers. 317 */ 318 319 /* for now, allocate as many bufs as there are ring descriptors */ 320 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 321 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 322 323 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 324 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 325 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 326 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 327 328 /* Get a DMA handle */ 329 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 330 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 331 printf("%s: DMA map create error %d\n", self->dv_xname, error); 332 return; 333 } 334 335 /* Allocate DMA buffer */ 336 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 337 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 338 printf("%s: DMA buffer alloc error %d\n", 339 self->dv_xname, error); 340 return; 341 } 342 343 /* Map DMA memory in CPU addressable space */ 344 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 345 &sc->sc_rb.rb_membase, 346 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 347 printf("%s: DMA buffer map error %d\n", 348 self->dv_xname, error); 349 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 350 return; 351 } 352 353 /* Load the buffer */ 354 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 355 sc->sc_rb.rb_membase, size, NULL, 356 BUS_DMA_NOWAIT)) != 0) { 357 printf("%s: DMA buffer map load error %d\n", 358 self->dv_xname, error); 359 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 360 bus_dmamem_free(dmatag, &seg, rseg); 361 return; 362 } 363 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 364 365 /* 366 * Initialize our media structures and MII info. 367 */ 368 mii->mii_ifp = ifp; 369 mii->mii_readreg = be_mii_readreg; 370 mii->mii_writereg = be_mii_writereg; 371 mii->mii_statchg = be_mii_statchg; 372 373 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 374 375 callout_init(&sc->sc_tick_ch); 376 377 /* 378 * Initialize transceiver and determine which PHY connection to use. 379 */ 380 be_mii_sync(sc); 381 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 382 383 instance = 0; 384 385 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 386 387 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 388 MII_OFFSET_ANY, 0); 389 390 child = LIST_FIRST(&mii->mii_phys); 391 if (child == NULL) { 392 /* No PHY attached */ 393 ifmedia_add(&sc->sc_media, 394 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 395 0, NULL); 396 ifmedia_set(&sc->sc_media, 397 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 398 } else { 399 /* 400 * Note: we support just one PHY on the external 401 * MII connector. 402 */ 403 #ifdef DIAGNOSTIC 404 if (LIST_NEXT(child, mii_list) != NULL) { 405 printf("%s: spurious MII device %s attached\n", 406 sc->sc_dev.dv_xname, 407 child->mii_dev.dv_xname); 408 } 409 #endif 410 if (child->mii_phy != BE_PHY_EXTERNAL || 411 child->mii_inst > 0) { 412 printf("%s: cannot accomodate MII device %s" 413 " at phy %d, instance %d\n", 414 sc->sc_dev.dv_xname, 415 child->mii_dev.dv_xname, 416 child->mii_phy, child->mii_inst); 417 } else { 418 sc->sc_phys[instance] = child->mii_phy; 419 } 420 421 /* 422 * XXX - we can really do the following ONLY if the 423 * phy indeed has the auto negotiation capability!! 424 */ 425 ifmedia_set(&sc->sc_media, 426 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 427 428 /* Mark our current media setting */ 429 be_pal_gate(sc, BE_PHY_EXTERNAL); 430 instance++; 431 } 432 433 } 434 435 if ((v & MGMT_PAL_INT_MDIO) != 0) { 436 /* 437 * The be internal phy looks vaguely like MII hardware, 438 * but not enough to be able to use the MII device 439 * layer. Hence, we have to take care of media selection 440 * ourselves. 441 */ 442 443 sc->sc_mii_inst = instance; 444 sc->sc_phys[instance] = BE_PHY_INTERNAL; 445 446 /* Use `ifm_data' to store BMCR bits */ 447 ifmedia_add(&sc->sc_media, 448 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 449 0, NULL); 450 ifmedia_add(&sc->sc_media, 451 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 452 BMCR_S100, NULL); 453 ifmedia_add(&sc->sc_media, 454 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 455 0, NULL); 456 457 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 458 self->dv_xname); 459 460 be_mii_reset(sc, BE_PHY_INTERNAL); 461 /* Only set default medium here if there's no external PHY */ 462 if (instance == 0) { 463 be_pal_gate(sc, BE_PHY_INTERNAL); 464 ifmedia_set(&sc->sc_media, 465 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 466 } else 467 be_mii_writereg((void *)sc, 468 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 469 } 470 471 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 472 ifp->if_softc = sc; 473 ifp->if_start = bestart; 474 ifp->if_ioctl = beioctl; 475 ifp->if_watchdog = bewatchdog; 476 ifp->if_flags = 477 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 478 IFQ_SET_READY(&ifp->if_snd); 479 480 /* Attach the interface. */ 481 if_attach(ifp); 482 ether_ifattach(ifp, sc->sc_enaddr); 483 } 484 485 486 /* 487 * Routine to copy from mbuf chain to transmit buffer in 488 * network buffer memory. 489 */ 490 static __inline__ int 491 be_put(sc, idx, m) 492 struct be_softc *sc; 493 int idx; 494 struct mbuf *m; 495 { 496 struct mbuf *n; 497 int len, tlen = 0, boff = 0; 498 caddr_t bp; 499 500 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 501 502 for (; m; m = n) { 503 len = m->m_len; 504 if (len == 0) { 505 MFREE(m, n); 506 continue; 507 } 508 bcopy(mtod(m, caddr_t), bp+boff, len); 509 boff += len; 510 tlen += len; 511 MFREE(m, n); 512 } 513 return (tlen); 514 } 515 516 /* 517 * Pull data off an interface. 518 * Len is the length of data, with local net header stripped. 519 * We copy the data into mbufs. When full cluster sized units are present, 520 * we copy into clusters. 521 */ 522 static __inline__ struct mbuf * 523 be_get(sc, idx, totlen) 524 struct be_softc *sc; 525 int idx, totlen; 526 { 527 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 528 struct mbuf *m; 529 struct mbuf *top, **mp; 530 int len, pad, boff = 0; 531 caddr_t bp; 532 533 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 534 535 MGETHDR(m, M_DONTWAIT, MT_DATA); 536 if (m == NULL) 537 return (NULL); 538 m->m_pkthdr.rcvif = ifp; 539 m->m_pkthdr.len = totlen; 540 541 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 542 m->m_data += pad; 543 len = MHLEN - pad; 544 top = NULL; 545 mp = ⊤ 546 547 while (totlen > 0) { 548 if (top) { 549 MGET(m, M_DONTWAIT, MT_DATA); 550 if (m == NULL) { 551 m_freem(top); 552 return (NULL); 553 } 554 len = MLEN; 555 } 556 if (top && totlen >= MINCLSIZE) { 557 MCLGET(m, M_DONTWAIT); 558 if (m->m_flags & M_EXT) 559 len = MCLBYTES; 560 } 561 m->m_len = len = min(totlen, len); 562 bcopy(bp + boff, mtod(m, caddr_t), len); 563 boff += len; 564 totlen -= len; 565 *mp = m; 566 mp = &m->m_next; 567 } 568 569 return (top); 570 } 571 572 /* 573 * Pass a packet to the higher levels. 574 */ 575 static __inline__ void 576 be_read(sc, idx, len) 577 struct be_softc *sc; 578 int idx, len; 579 { 580 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 581 struct mbuf *m; 582 583 if (len <= sizeof(struct ether_header) || 584 len > ETHERMTU + sizeof(struct ether_header)) { 585 586 printf("%s: invalid packet size %d; dropping\n", 587 ifp->if_xname, len); 588 589 ifp->if_ierrors++; 590 return; 591 } 592 593 /* 594 * Pull packet off interface. 595 */ 596 m = be_get(sc, idx, len); 597 if (m == NULL) { 598 ifp->if_ierrors++; 599 return; 600 } 601 ifp->if_ipackets++; 602 603 #if NBPFILTER > 0 604 /* 605 * Check if there's a BPF listener on this interface. 606 * If so, hand off the raw packet to BPF. 607 */ 608 if (ifp->if_bpf) 609 bpf_mtap(ifp->if_bpf, m); 610 #endif 611 /* Pass the packet up. */ 612 (*ifp->if_input)(ifp, m); 613 } 614 615 /* 616 * Start output on interface. 617 * We make two assumptions here: 618 * 1) that the current priority is set to splnet _before_ this code 619 * is called *and* is returned to the appropriate priority after 620 * return 621 * 2) that the IFF_OACTIVE flag is checked before this code is called 622 * (i.e. that the output part of the interface is idle) 623 */ 624 void 625 bestart(ifp) 626 struct ifnet *ifp; 627 { 628 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 629 struct qec_xd *txd = sc->sc_rb.rb_txd; 630 struct mbuf *m; 631 unsigned int bix, len; 632 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 633 634 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 635 return; 636 637 bix = sc->sc_rb.rb_tdhead; 638 639 for (;;) { 640 IFQ_DEQUEUE(&ifp->if_snd, m); 641 if (m == 0) 642 break; 643 644 #if NBPFILTER > 0 645 /* 646 * If BPF is listening on this interface, let it see the 647 * packet before we commit it to the wire. 648 */ 649 if (ifp->if_bpf) 650 bpf_mtap(ifp->if_bpf, m); 651 #endif 652 653 /* 654 * Copy the mbuf chain into the transmit buffer. 655 */ 656 len = be_put(sc, bix, m); 657 658 /* 659 * Initialize transmit registers and start transmission 660 */ 661 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 662 (len & QEC_XD_LENGTH); 663 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 664 BE_CR_CTRL_TWAKEUP); 665 666 if (++bix == QEC_XD_RING_MAXSIZE) 667 bix = 0; 668 669 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 670 ifp->if_flags |= IFF_OACTIVE; 671 break; 672 } 673 } 674 675 sc->sc_rb.rb_tdhead = bix; 676 } 677 678 void 679 bestop(sc) 680 struct be_softc *sc; 681 { 682 int n; 683 bus_space_tag_t t = sc->sc_bustag; 684 bus_space_handle_t br = sc->sc_br; 685 686 callout_stop(&sc->sc_tick_ch); 687 688 /* Down the MII. */ 689 mii_down(&sc->sc_mii); 690 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 691 692 /* Stop the transmitter */ 693 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 694 for (n = 32; n > 0; n--) { 695 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 696 break; 697 DELAY(20); 698 } 699 700 /* Stop the receiver */ 701 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 702 for (n = 32; n > 0; n--) { 703 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 704 break; 705 DELAY(20); 706 } 707 } 708 709 /* 710 * Reset interface. 711 */ 712 void 713 bereset(sc) 714 struct be_softc *sc; 715 { 716 int s; 717 718 s = splnet(); 719 bestop(sc); 720 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 721 beinit(sc); 722 splx(s); 723 } 724 725 void 726 bewatchdog(ifp) 727 struct ifnet *ifp; 728 { 729 struct be_softc *sc = ifp->if_softc; 730 731 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 732 ++sc->sc_ethercom.ec_if.if_oerrors; 733 734 bereset(sc); 735 } 736 737 int 738 beintr(v) 739 void *v; 740 { 741 struct be_softc *sc = (struct be_softc *)v; 742 bus_space_tag_t t = sc->sc_bustag; 743 u_int32_t whyq, whyb, whyc; 744 int r = 0; 745 746 /* Read QEC status, channel status and BE status */ 747 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 748 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 749 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 750 751 if (whyq & QEC_STAT_BM) 752 r |= beeint(sc, whyb); 753 754 if (whyq & QEC_STAT_ER) 755 r |= beqint(sc, whyc); 756 757 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 758 r |= betint(sc); 759 760 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 761 r |= berint(sc); 762 763 return (r); 764 } 765 766 /* 767 * QEC Interrupt. 768 */ 769 int 770 beqint(sc, why) 771 struct be_softc *sc; 772 u_int32_t why; 773 { 774 int r = 0, rst = 0; 775 776 if (why & BE_CR_STAT_TXIRQ) 777 r |= 1; 778 if (why & BE_CR_STAT_RXIRQ) 779 r |= 1; 780 781 if (why & BE_CR_STAT_BERROR) { 782 r |= 1; 783 rst = 1; 784 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 785 } 786 787 if (why & BE_CR_STAT_TXDERR) { 788 r |= 1; 789 rst = 1; 790 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 791 } 792 793 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 794 r |= 1; 795 rst = 1; 796 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 797 if (why & BE_CR_STAT_TXLERR) 798 printf("Late "); 799 if (why & BE_CR_STAT_TXPERR) 800 printf("Parity "); 801 if (why & BE_CR_STAT_TXSERR) 802 printf("Generic "); 803 printf(")\n"); 804 } 805 806 if (why & BE_CR_STAT_RXDROP) { 807 r |= 1; 808 rst = 1; 809 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 810 } 811 812 if (why & BE_CR_STAT_RXSMALL) { 813 r |= 1; 814 rst = 1; 815 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 816 } 817 818 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 819 r |= 1; 820 rst = 1; 821 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 822 if (why & BE_CR_STAT_RXLERR) 823 printf("Late "); 824 if (why & BE_CR_STAT_RXPERR) 825 printf("Parity "); 826 if (why & BE_CR_STAT_RXSERR) 827 printf("Generic "); 828 printf(")\n"); 829 } 830 831 if (!r) { 832 rst = 1; 833 printf("%s: unexpected error interrupt %08x\n", 834 sc->sc_dev.dv_xname, why); 835 } 836 837 if (rst) { 838 printf("%s: resetting\n", sc->sc_dev.dv_xname); 839 bereset(sc); 840 } 841 842 return (r); 843 } 844 845 /* 846 * Error interrupt. 847 */ 848 int 849 beeint(sc, why) 850 struct be_softc *sc; 851 u_int32_t why; 852 { 853 int r = 0, rst = 0; 854 855 if (why & BE_BR_STAT_RFIFOVF) { 856 r |= 1; 857 rst = 1; 858 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 859 } 860 if (why & BE_BR_STAT_TFIFO_UND) { 861 r |= 1; 862 rst = 1; 863 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 864 } 865 if (why & BE_BR_STAT_MAXPKTERR) { 866 r |= 1; 867 rst = 1; 868 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 869 } 870 871 if (!r) { 872 rst = 1; 873 printf("%s: unexpected error interrupt %08x\n", 874 sc->sc_dev.dv_xname, why); 875 } 876 877 if (rst) { 878 printf("%s: resetting\n", sc->sc_dev.dv_xname); 879 bereset(sc); 880 } 881 882 return (r); 883 } 884 885 /* 886 * Transmit interrupt. 887 */ 888 int 889 betint(sc) 890 struct be_softc *sc; 891 { 892 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 893 bus_space_tag_t t = sc->sc_bustag; 894 bus_space_handle_t br = sc->sc_br; 895 unsigned int bix, txflags; 896 897 /* 898 * Unload collision counters 899 */ 900 ifp->if_collisions += 901 bus_space_read_4(t, br, BE_BRI_NCCNT) + 902 bus_space_read_4(t, br, BE_BRI_FCCNT) + 903 bus_space_read_4(t, br, BE_BRI_EXCNT) + 904 bus_space_read_4(t, br, BE_BRI_LTCNT); 905 906 /* 907 * the clear the hardware counters 908 */ 909 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 910 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 911 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 912 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 913 914 bix = sc->sc_rb.rb_tdtail; 915 916 for (;;) { 917 if (sc->sc_rb.rb_td_nbusy <= 0) 918 break; 919 920 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 921 922 if (txflags & QEC_XD_OWN) 923 break; 924 925 ifp->if_flags &= ~IFF_OACTIVE; 926 ifp->if_opackets++; 927 928 if (++bix == QEC_XD_RING_MAXSIZE) 929 bix = 0; 930 931 --sc->sc_rb.rb_td_nbusy; 932 } 933 934 sc->sc_rb.rb_tdtail = bix; 935 936 bestart(ifp); 937 938 if (sc->sc_rb.rb_td_nbusy == 0) 939 ifp->if_timer = 0; 940 941 return (1); 942 } 943 944 /* 945 * Receive interrupt. 946 */ 947 int 948 berint(sc) 949 struct be_softc *sc; 950 { 951 struct qec_xd *xd = sc->sc_rb.rb_rxd; 952 unsigned int bix, len; 953 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 954 955 bix = sc->sc_rb.rb_rdtail; 956 957 /* 958 * Process all buffers with valid data. 959 */ 960 for (;;) { 961 len = xd[bix].xd_flags; 962 if (len & QEC_XD_OWN) 963 break; 964 965 len &= QEC_XD_LENGTH; 966 be_read(sc, bix, len); 967 968 /* ... */ 969 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 970 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 971 972 if (++bix == QEC_XD_RING_MAXSIZE) 973 bix = 0; 974 } 975 976 sc->sc_rb.rb_rdtail = bix; 977 978 return (1); 979 } 980 981 int 982 beioctl(ifp, cmd, data) 983 struct ifnet *ifp; 984 u_long cmd; 985 caddr_t data; 986 { 987 struct be_softc *sc = ifp->if_softc; 988 struct ifaddr *ifa = (struct ifaddr *)data; 989 struct ifreq *ifr = (struct ifreq *)data; 990 int s, error = 0; 991 992 s = splnet(); 993 994 switch (cmd) { 995 case SIOCSIFADDR: 996 ifp->if_flags |= IFF_UP; 997 switch (ifa->ifa_addr->sa_family) { 998 #ifdef INET 999 case AF_INET: 1000 beinit(sc); 1001 arp_ifinit(ifp, ifa); 1002 break; 1003 #endif /* INET */ 1004 #ifdef NS 1005 case AF_NS: 1006 { 1007 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1008 1009 if (ns_nullhost(*ina)) 1010 ina->x_host = 1011 *(union ns_host *)LLADDR(ifp->if_sadl); 1012 else 1013 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1014 sizeof(sc->sc_enaddr)); 1015 /* Set new address. */ 1016 beinit(sc); 1017 break; 1018 } 1019 #endif /* NS */ 1020 default: 1021 beinit(sc); 1022 break; 1023 } 1024 break; 1025 1026 case SIOCSIFFLAGS: 1027 if ((ifp->if_flags & IFF_UP) == 0 && 1028 (ifp->if_flags & IFF_RUNNING) != 0) { 1029 /* 1030 * If interface is marked down and it is running, then 1031 * stop it. 1032 */ 1033 bestop(sc); 1034 ifp->if_flags &= ~IFF_RUNNING; 1035 } else if ((ifp->if_flags & IFF_UP) != 0 && 1036 (ifp->if_flags & IFF_RUNNING) == 0) { 1037 /* 1038 * If interface is marked up and it is stopped, then 1039 * start it. 1040 */ 1041 beinit(sc); 1042 } else { 1043 /* 1044 * Reset the interface to pick up changes in any other 1045 * flags that affect hardware registers. 1046 */ 1047 bestop(sc); 1048 beinit(sc); 1049 } 1050 #ifdef BEDEBUG 1051 if (ifp->if_flags & IFF_DEBUG) 1052 sc->sc_debug = 1; 1053 else 1054 sc->sc_debug = 0; 1055 #endif 1056 break; 1057 1058 case SIOCADDMULTI: 1059 case SIOCDELMULTI: 1060 error = (cmd == SIOCADDMULTI) ? 1061 ether_addmulti(ifr, &sc->sc_ethercom): 1062 ether_delmulti(ifr, &sc->sc_ethercom); 1063 1064 if (error == ENETRESET) { 1065 /* 1066 * Multicast list has changed; set the hardware filter 1067 * accordingly. 1068 */ 1069 be_mcreset(sc); 1070 error = 0; 1071 } 1072 break; 1073 case SIOCGIFMEDIA: 1074 case SIOCSIFMEDIA: 1075 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1076 break; 1077 default: 1078 error = EINVAL; 1079 break; 1080 } 1081 splx(s); 1082 return (error); 1083 } 1084 1085 1086 void 1087 beinit(sc) 1088 struct be_softc *sc; 1089 { 1090 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1091 bus_space_tag_t t = sc->sc_bustag; 1092 bus_space_handle_t br = sc->sc_br; 1093 bus_space_handle_t cr = sc->sc_cr; 1094 struct qec_softc *qec = sc->sc_qec; 1095 u_int32_t v; 1096 u_int32_t qecaddr; 1097 u_int8_t *ea; 1098 int s; 1099 1100 s = splnet(); 1101 1102 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1103 1104 bestop(sc); 1105 1106 ea = sc->sc_enaddr; 1107 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1108 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1109 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1110 1111 /* Clear hash table */ 1112 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1113 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1114 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1115 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1116 1117 /* Re-initialize RX configuration */ 1118 v = BE_BR_RXCFG_FIFO; 1119 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1120 1121 be_mcreset(sc); 1122 1123 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1124 1125 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1126 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1127 1128 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1129 1130 /* 1131 * Turn off counter expiration interrupts as well as 1132 * 'gotframe' and 'sentframe' 1133 */ 1134 bus_space_write_4(t, br, BE_BRI_IMASK, 1135 BE_BR_IMASK_GOTFRAME | 1136 BE_BR_IMASK_RCNTEXP | 1137 BE_BR_IMASK_ACNTEXP | 1138 BE_BR_IMASK_CCNTEXP | 1139 BE_BR_IMASK_LCNTEXP | 1140 BE_BR_IMASK_CVCNTEXP | 1141 BE_BR_IMASK_SENTFRAME | 1142 BE_BR_IMASK_NCNTEXP | 1143 BE_BR_IMASK_ECNTEXP | 1144 BE_BR_IMASK_LCCNTEXP | 1145 BE_BR_IMASK_FCNTEXP | 1146 BE_BR_IMASK_DTIMEXP); 1147 1148 /* Channel registers: */ 1149 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1150 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1151 1152 qecaddr = sc->sc_channel * qec->sc_msize; 1153 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1154 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1155 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1156 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1157 1158 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1159 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1160 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1161 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1162 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1163 1164 /* Enable transmitter */ 1165 bus_space_write_4(t, br, BE_BRI_TXCFG, 1166 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1167 1168 /* Enable receiver */ 1169 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1170 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1171 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1172 1173 ifp->if_flags |= IFF_RUNNING; 1174 ifp->if_flags &= ~IFF_OACTIVE; 1175 1176 be_ifmedia_upd(ifp); 1177 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1178 splx(s); 1179 } 1180 1181 void 1182 be_mcreset(sc) 1183 struct be_softc *sc; 1184 { 1185 struct ethercom *ec = &sc->sc_ethercom; 1186 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1187 bus_space_tag_t t = sc->sc_bustag; 1188 bus_space_handle_t br = sc->sc_br; 1189 u_int32_t crc; 1190 u_int16_t hash[4]; 1191 u_int8_t octet; 1192 u_int32_t v; 1193 int i, j; 1194 struct ether_multi *enm; 1195 struct ether_multistep step; 1196 1197 if (ifp->if_flags & IFF_PROMISC) { 1198 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1199 v |= BE_BR_RXCFG_PMISC; 1200 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1201 return; 1202 } 1203 1204 if (ifp->if_flags & IFF_ALLMULTI) { 1205 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1206 goto chipit; 1207 } 1208 1209 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1210 1211 ETHER_FIRST_MULTI(step, ec, enm); 1212 while (enm != NULL) { 1213 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1214 /* 1215 * We must listen to a range of multicast 1216 * addresses. For now, just accept all 1217 * multicasts, rather than trying to set only 1218 * those filter bits needed to match the range. 1219 * (At this time, the only use of address 1220 * ranges is for IP multicast routing, for 1221 * which the range is big enough to require 1222 * all bits set.) 1223 */ 1224 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1225 ifp->if_flags |= IFF_ALLMULTI; 1226 goto chipit; 1227 } 1228 1229 crc = 0xffffffff; 1230 1231 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1232 octet = enm->enm_addrlo[i]; 1233 1234 for (j = 0; j < 8; j++) { 1235 if ((crc & 1) ^ (octet & 1)) { 1236 crc >>= 1; 1237 crc ^= MC_POLY_LE; 1238 } 1239 else 1240 crc >>= 1; 1241 octet >>= 1; 1242 } 1243 } 1244 1245 crc >>= 26; 1246 hash[crc >> 4] |= 1 << (crc & 0xf); 1247 ETHER_NEXT_MULTI(step, enm); 1248 } 1249 1250 ifp->if_flags &= ~IFF_ALLMULTI; 1251 1252 chipit: 1253 /* Enable the hash filter */ 1254 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1255 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1256 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1257 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1258 1259 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1260 v &= ~BE_BR_RXCFG_PMISC; 1261 v |= BE_BR_RXCFG_HENABLE; 1262 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1263 } 1264 1265 /* 1266 * Set the tcvr to an idle state 1267 */ 1268 void 1269 be_mii_sync(sc) 1270 struct be_softc *sc; 1271 { 1272 bus_space_tag_t t = sc->sc_bustag; 1273 bus_space_handle_t tr = sc->sc_tr; 1274 int n = 32; 1275 1276 while (n--) { 1277 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1278 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1279 MGMT_PAL_OENAB); 1280 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1281 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1282 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1283 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1284 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1285 } 1286 } 1287 1288 void 1289 be_pal_gate(sc, phy) 1290 struct be_softc *sc; 1291 int phy; 1292 { 1293 bus_space_tag_t t = sc->sc_bustag; 1294 bus_space_handle_t tr = sc->sc_tr; 1295 u_int32_t v; 1296 1297 be_mii_sync(sc); 1298 1299 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1300 if (phy == BE_PHY_INTERNAL) 1301 v &= ~TCVR_PAL_SERIAL; 1302 1303 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1304 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1305 } 1306 1307 static int 1308 be_tcvr_read_bit(sc, phy) 1309 struct be_softc *sc; 1310 int phy; 1311 { 1312 bus_space_tag_t t = sc->sc_bustag; 1313 bus_space_handle_t tr = sc->sc_tr; 1314 int ret; 1315 1316 if (phy == BE_PHY_INTERNAL) { 1317 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1318 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1319 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1320 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1321 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1322 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1323 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1324 } else { 1325 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1326 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1327 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1328 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1329 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1330 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1331 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1332 } 1333 1334 return (ret); 1335 } 1336 1337 static void 1338 be_tcvr_write_bit(sc, phy, bit) 1339 struct be_softc *sc; 1340 int phy; 1341 int bit; 1342 { 1343 bus_space_tag_t t = sc->sc_bustag; 1344 bus_space_handle_t tr = sc->sc_tr; 1345 u_int32_t v; 1346 1347 if (phy == BE_PHY_INTERNAL) { 1348 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1349 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1350 } else { 1351 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1352 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1353 } 1354 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1355 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1356 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1357 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1358 } 1359 1360 static void 1361 be_mii_sendbits(sc, phy, data, nbits) 1362 struct be_softc *sc; 1363 int phy; 1364 u_int32_t data; 1365 int nbits; 1366 { 1367 int i; 1368 1369 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1370 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1371 } 1372 } 1373 1374 static int 1375 be_mii_readreg(self, phy, reg) 1376 struct device *self; 1377 int phy, reg; 1378 { 1379 struct be_softc *sc = (struct be_softc *)self; 1380 int val = 0, i; 1381 1382 /* 1383 * Read the PHY register by manually driving the MII control lines. 1384 */ 1385 be_mii_sync(sc); 1386 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1387 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1388 be_mii_sendbits(sc, phy, phy, 5); 1389 be_mii_sendbits(sc, phy, reg, 5); 1390 1391 (void) be_tcvr_read_bit(sc, phy); 1392 (void) be_tcvr_read_bit(sc, phy); 1393 1394 for (i = 15; i >= 0; i--) 1395 val |= (be_tcvr_read_bit(sc, phy) << i); 1396 1397 (void) be_tcvr_read_bit(sc, phy); 1398 (void) be_tcvr_read_bit(sc, phy); 1399 (void) be_tcvr_read_bit(sc, phy); 1400 1401 return (val); 1402 } 1403 1404 void 1405 be_mii_writereg(self, phy, reg, val) 1406 struct device *self; 1407 int phy, reg, val; 1408 { 1409 struct be_softc *sc = (struct be_softc *)self; 1410 int i; 1411 1412 /* 1413 * Write the PHY register by manually driving the MII control lines. 1414 */ 1415 be_mii_sync(sc); 1416 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1417 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1418 be_mii_sendbits(sc, phy, phy, 5); 1419 be_mii_sendbits(sc, phy, reg, 5); 1420 1421 be_tcvr_write_bit(sc, phy, 1); 1422 be_tcvr_write_bit(sc, phy, 0); 1423 1424 for (i = 15; i >= 0; i--) 1425 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1426 } 1427 1428 int 1429 be_mii_reset(sc, phy) 1430 struct be_softc *sc; 1431 int phy; 1432 { 1433 int n; 1434 1435 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1436 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1437 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1438 1439 for (n = 16; n >= 0; n--) { 1440 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1441 if ((bmcr & BMCR_RESET) == 0) 1442 break; 1443 DELAY(20); 1444 } 1445 if (n == 0) { 1446 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1447 return (EIO); 1448 } 1449 1450 return (0); 1451 } 1452 1453 void 1454 be_tick(arg) 1455 void *arg; 1456 { 1457 struct be_softc *sc = arg; 1458 int s = splnet(); 1459 1460 mii_tick(&sc->sc_mii); 1461 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1462 1463 splx(s); 1464 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1465 } 1466 1467 void 1468 be_mii_statchg(self) 1469 struct device *self; 1470 { 1471 struct be_softc *sc = (struct be_softc *)self; 1472 bus_space_tag_t t = sc->sc_bustag; 1473 bus_space_handle_t br = sc->sc_br; 1474 u_int instance; 1475 u_int32_t v; 1476 1477 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1478 #ifdef DIAGNOSTIC 1479 if (instance > 1) 1480 panic("be_mii_statchg: instance %d out of range", instance); 1481 #endif 1482 1483 /* Update duplex mode in TX configuration */ 1484 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1485 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1486 v |= BE_BR_TXCFG_FULLDPLX; 1487 else 1488 v &= ~BE_BR_TXCFG_FULLDPLX; 1489 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1490 1491 /* Change to appropriate gate in transceiver PAL */ 1492 be_pal_gate(sc, sc->sc_phys[instance]); 1493 } 1494 1495 /* 1496 * Get current media settings. 1497 */ 1498 void 1499 be_ifmedia_sts(ifp, ifmr) 1500 struct ifnet *ifp; 1501 struct ifmediareq *ifmr; 1502 { 1503 struct be_softc *sc = ifp->if_softc; 1504 1505 mii_pollstat(&sc->sc_mii); 1506 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1507 1508 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1509 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1510 return; 1511 } 1512 1513 /* 1514 * Set media options. 1515 */ 1516 int 1517 be_ifmedia_upd(ifp) 1518 struct ifnet *ifp; 1519 { 1520 struct be_softc *sc = ifp->if_softc; 1521 int error; 1522 1523 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1524 return (error); 1525 1526 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1527 } 1528 1529 /* 1530 * Service routine for our pseudo-MII internal transceiver. 1531 */ 1532 int 1533 be_intphy_service(sc, mii, cmd) 1534 struct be_softc *sc; 1535 struct mii_data *mii; 1536 int cmd; 1537 { 1538 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1539 int bmcr, bmsr; 1540 int error; 1541 1542 switch (cmd) { 1543 case MII_POLLSTAT: 1544 /* 1545 * If we're not polling our PHY instance, just return. 1546 */ 1547 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1548 return (0); 1549 1550 break; 1551 1552 case MII_MEDIACHG: 1553 1554 /* 1555 * If the media indicates a different PHY instance, 1556 * isolate ourselves. 1557 */ 1558 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1559 bmcr = be_mii_readreg((void *)sc, 1560 BE_PHY_INTERNAL, MII_BMCR); 1561 be_mii_writereg((void *)sc, 1562 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1563 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1564 sc->sc_intphy_curspeed = 0; 1565 return (0); 1566 } 1567 1568 1569 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1570 return (error); 1571 1572 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1573 1574 /* 1575 * Select the new mode and take out of isolation 1576 */ 1577 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1578 bmcr |= BMCR_S100; 1579 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1580 bmcr &= ~BMCR_S100; 1581 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1582 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1583 bmcr &= ~BMCR_S100; 1584 bmcr |= sc->sc_intphy_curspeed; 1585 } else { 1586 /* Keep isolated until link is up */ 1587 bmcr |= BMCR_ISO; 1588 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1589 } 1590 } 1591 1592 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1593 bmcr |= BMCR_FDX; 1594 else 1595 bmcr &= ~BMCR_FDX; 1596 1597 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1598 break; 1599 1600 case MII_TICK: 1601 /* 1602 * If we're not currently selected, just return. 1603 */ 1604 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1605 return (0); 1606 1607 /* Only used for automatic media selection */ 1608 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1609 return (0); 1610 1611 /* Is the interface even up? */ 1612 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1613 return (0); 1614 1615 /* 1616 * Check link status; if we don't have a link, try another 1617 * speed. We can't detect duplex mode, so half-duplex is 1618 * what we have to settle for. 1619 */ 1620 1621 /* Read twice in case the register is latched */ 1622 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1623 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1624 1625 if ((bmsr & BMSR_LINK) != 0) { 1626 /* We have a carrier */ 1627 bmcr = be_mii_readreg((void *)sc, 1628 BE_PHY_INTERNAL, MII_BMCR); 1629 1630 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1631 bmcr = be_mii_readreg((void *)sc, 1632 BE_PHY_INTERNAL, MII_BMCR); 1633 1634 sc->sc_mii_flags |= MIIF_HAVELINK; 1635 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1636 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1637 1638 bmcr &= ~BMCR_ISO; 1639 be_mii_writereg((void *)sc, 1640 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1641 1642 printf("%s: link up at %s Mbps\n", 1643 sc->sc_dev.dv_xname, 1644 (bmcr & BMCR_S100) ? "100" : "10"); 1645 } 1646 return (0); 1647 } 1648 1649 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1650 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1651 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1652 sc->sc_intphy_curspeed = 0; 1653 printf("%s: link down\n", sc->sc_dev.dv_xname); 1654 } 1655 1656 /* Only retry autonegotiation every 5 seconds. */ 1657 if (++sc->sc_mii_ticks < 5) 1658 return(0); 1659 1660 sc->sc_mii_ticks = 0; 1661 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1662 /* Just flip the fast speed bit */ 1663 bmcr ^= BMCR_S100; 1664 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1665 1666 break; 1667 1668 case MII_DOWN: 1669 /* Isolate this phy */ 1670 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1671 be_mii_writereg((void *)sc, 1672 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1673 return (0); 1674 } 1675 1676 /* Update the media status. */ 1677 be_intphy_status(sc); 1678 1679 /* Callback if something changed. */ 1680 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1681 (*mii->mii_statchg)((struct device *)sc); 1682 sc->sc_mii_active = mii->mii_media_active; 1683 } 1684 return (0); 1685 } 1686 1687 /* 1688 * Determine status of internal transceiver 1689 */ 1690 void 1691 be_intphy_status(sc) 1692 struct be_softc *sc; 1693 { 1694 struct mii_data *mii = &sc->sc_mii; 1695 int media_active, media_status; 1696 int bmcr, bmsr; 1697 1698 media_status = IFM_AVALID; 1699 media_active = 0; 1700 1701 /* 1702 * Internal transceiver; do the work here. 1703 */ 1704 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1705 1706 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1707 case (BMCR_S100 | BMCR_FDX): 1708 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1709 break; 1710 case BMCR_S100: 1711 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1712 break; 1713 case BMCR_FDX: 1714 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1715 break; 1716 case 0: 1717 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1718 break; 1719 } 1720 1721 /* Read twice in case the register is latched */ 1722 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1723 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1724 if (bmsr & BMSR_LINK) 1725 media_status |= IFM_ACTIVE; 1726 1727 mii->mii_media_status = media_status; 1728 mii->mii_media_active = media_active; 1729 } 1730