xref: /netbsd-src/sys/dev/qbus/uda.c (revision b1c86f5f087524e68db12794ee9c3e3da1ab17a0)
1 /*	$NetBSD: uda.c,v 1.60 2009/05/12 14:08:35 cegger Exp $	*/
2 /*
3  * Copyright (c) 1988 Regents of the University of California.
4  * All rights reserved.
5  *
6  * This code is derived from software contributed to Berkeley by
7  * Chris Torek.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. Neither the name of the University nor the names of its contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  *
33  *	@(#)uda.c	7.32 (Berkeley) 2/13/91
34  */
35 
36 /*
37  * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
38  * All rights reserved.
39  *
40  * This code is derived from software contributed to Berkeley by
41  * Chris Torek.
42  *
43  * Redistribution and use in source and binary forms, with or without
44  * modification, are permitted provided that the following conditions
45  * are met:
46  * 1. Redistributions of source code must retain the above copyright
47  *    notice, this list of conditions and the following disclaimer.
48  * 2. Redistributions in binary form must reproduce the above copyright
49  *    notice, this list of conditions and the following disclaimer in the
50  *    documentation and/or other materials provided with the distribution.
51  * 3. All advertising materials mentioning features or use of this software
52  *    must display the following acknowledgement:
53  *	This product includes software developed by the University of
54  *	California, Berkeley and its contributors.
55  * 4. Neither the name of the University nor the names of its contributors
56  *    may be used to endorse or promote products derived from this software
57  *    without specific prior written permission.
58  *
59  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
60  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
63  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69  * SUCH DAMAGE.
70  *
71  *	@(#)uda.c	7.32 (Berkeley) 2/13/91
72  */
73 
74 /*
75  * UDA50 disk device driver
76  */
77 
78 #include <sys/cdefs.h>
79 __KERNEL_RCSID(0, "$NetBSD: uda.c,v 1.60 2009/05/12 14:08:35 cegger Exp $");
80 
81 #include <sys/param.h>
82 #include <sys/kernel.h>
83 #include <sys/systm.h>
84 #include <sys/device.h>
85 #include <sys/buf.h>
86 #include <sys/bufq.h>
87 #include <sys/malloc.h>
88 
89 #include <sys/bus.h>
90 #include <machine/sid.h>
91 
92 #include <dev/qbus/ubavar.h>
93 
94 #include <dev/mscp/mscp.h>
95 #include <dev/mscp/mscpreg.h>
96 #include <dev/mscp/mscpvar.h>
97 
98 #include "ioconf.h"
99 
100 /*
101  * Software status, per controller.
102  */
103 struct	uda_softc {
104 	device_t sc_dev;	/* Autoconfig info */
105 	struct uba_softc *sc_uh;
106 	struct	evcnt sc_intrcnt; /* Interrupt counting */
107 	struct	uba_unit sc_unit; /* Struct common for UBA to communicate */
108 	struct	ubinfo sc_ui;
109 	bus_dma_tag_t		sc_dmat;
110 	bus_space_tag_t		sc_iot;
111 	bus_space_handle_t	sc_iph;
112 	bus_space_handle_t	sc_sah;
113 	struct	mscp_softc *sc_softc;	/* MSCP info (per mscpvar.h) */
114 	int	sc_inq;
115 };
116 
117 static	int udamatch(device_t, cfdata_t, void *);
118 static	void udaattach(device_t, device_t, void *);
119 static	void udareset(device_t);
120 static	void udaintr(void *);
121 static	int udaready(struct uba_unit *);
122 static	void udactlrdone(device_t);
123 static	int udaprint(void *, const char *);
124 static	void udasaerror(device_t, int);
125 static	void udago(device_t, struct mscp_xi *);
126 
127 CFATTACH_DECL_NEW(mtc, sizeof(struct uda_softc),
128     udamatch, udaattach, NULL, NULL);
129 
130 CFATTACH_DECL_NEW(uda, sizeof(struct uda_softc),
131     udamatch, udaattach, NULL, NULL);
132 
133 /*
134  * More driver definitions, for generic MSCP code.
135  */
136 struct	mscp_ctlr uda_mscp_ctlr = {
137 	udactlrdone,
138 	udago,
139 	udasaerror,
140 };
141 
142 int
143 udaprint(void *aux, const char *name)
144 {
145 	if (name)
146 		aprint_normal("%s: mscpbus", name);
147 	return UNCONF;
148 }
149 
150 /*
151  * Poke at a supposed UDA50 to see if it is there.
152  */
153 int
154 udamatch(device_t parent, cfdata_t cf, void *aux)
155 {
156 	struct	uba_attach_args *ua = aux;
157 	struct	uba_softc *uh = device_private(parent);
158 	struct	mscp_softc mi;	/* Nice hack */
159 	int	tries;
160 
161 	/* Get an interrupt vector. */
162 
163 	mi.mi_iot = ua->ua_iot;
164 	mi.mi_iph = ua->ua_ioh;
165 	mi.mi_sah = ua->ua_ioh + 2;
166 	mi.mi_swh = ua->ua_ioh + 2;
167 
168 	/*
169 	 * Initialise the controller (partially).  The UDA50 programmer's
170 	 * manual states that if initialisation fails, it should be retried
171 	 * at least once, but after a second failure the port should be
172 	 * considered `down'; it also mentions that the controller should
173 	 * initialise within ten seconds.  Or so I hear; I have not seen
174 	 * this manual myself.
175 	 */
176 	tries = 0;
177 again:
178 
179 	bus_space_write_2(mi.mi_iot, mi.mi_iph, 0, 0); /* Start init */
180 	if (mscp_waitstep(&mi, MP_STEP1, MP_STEP1) == 0)
181 		return 0; /* Nothing here... */
182 
183 	bus_space_write_2(mi.mi_iot, mi.mi_sah, 0,
184 	    MP_ERR | (NCMDL2 << 11) | (NRSPL2 << 8) | MP_IE |
185 	    ((uh->uh_lastiv - 4) >> 2));
186 
187 	if (mscp_waitstep(&mi, MP_STEP2, MP_STEP2) == 0) {
188 		printf("udaprobe: init step2 no change. sa=%x\n",
189 		    bus_space_read_2(mi.mi_iot, mi.mi_sah, 0));
190 		goto bad;
191 	}
192 
193 	/* should have interrupted by now */
194 	return 1;
195 bad:
196 	if (++tries < 2)
197 		goto again;
198 	return 0;
199 }
200 
201 void
202 udaattach(device_t parent, device_t self, void *aux)
203 {
204 	struct	uda_softc *sc = device_private(self);
205 	struct	uba_attach_args *ua = aux;
206 	struct	mscp_attach_args ma;
207 	int	error;
208 
209 	printf("\n");
210 
211 	sc->sc_dev = self;
212 	sc->sc_uh = device_private(parent);
213 
214 	sc->sc_uh->uh_lastiv -= 4;	/* remove dynamic interrupt vector */
215 
216 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
217 		udaintr, sc, &sc->sc_intrcnt);
218 	uba_reset_establish(udareset, sc->sc_dev);
219 	evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
220 		device_xname(sc->sc_dev), "intr");
221 
222 	sc->sc_iot = ua->ua_iot;
223 	sc->sc_iph = ua->ua_ioh;
224 	sc->sc_sah = ua->ua_ioh + 2;
225 	sc->sc_dmat = ua->ua_dmat;
226 
227 	/*
228 	 * Fill in the uba_unit struct, so we can communicate with the uba.
229 	 */
230 	sc->sc_unit.uu_dev = self;	/* Backpointer to softc */
231 	sc->sc_unit.uu_ready = udaready;/* go routine called from adapter */
232 	sc->sc_unit.uu_keepbdp = vax_cputype == VAX_750 ? 1 : 0;
233 
234 	/*
235 	 * Map the communication area and command and
236 	 * response packets into Unibus space.
237 	 */
238 	sc->sc_ui.ui_size = sizeof(struct mscp_pack);
239 	if ((error = ubmemalloc(sc->sc_uh, &sc->sc_ui, UBA_CANTWAIT)))
240 		return printf("ubmemalloc failed: %d\n", error);
241 
242 	memset(sc->sc_ui.ui_vaddr, 0, sizeof (struct mscp_pack));
243 
244 	/*
245 	 * The only thing that differ UDA's and Tape ctlr's is
246 	 * their vcid. Beacuse there are no way to determine which
247 	 * ctlr type it is, we check what is generated and later
248 	 * set the correct vcid.
249 	 */
250 	ma.ma_type = (device_is_a(self, "mtc") ? MSCPBUS_TAPE : MSCPBUS_DISK);
251 
252 	ma.ma_mc = &uda_mscp_ctlr;
253 	ma.ma_type |= MSCPBUS_UDA;
254 	ma.ma_uda = (struct mscp_pack *)sc->sc_ui.ui_vaddr;
255 	ma.ma_softc = &sc->sc_softc;
256 	ma.ma_iot = sc->sc_iot;
257 	ma.ma_iph = sc->sc_iph;
258 	ma.ma_sah = sc->sc_sah;
259 	ma.ma_swh = sc->sc_sah;
260 	ma.ma_dmat = sc->sc_dmat;
261 	ma.ma_dmam = sc->sc_ui.ui_dmam;
262 	ma.ma_ivec = sc->sc_uh->uh_lastiv;
263 	ma.ma_ctlrnr = (ua->ua_iaddr == 0172150 ? 0 : 1);	/* XXX */
264 	ma.ma_adapnr = sc->sc_uh->uh_nr;
265 	config_found(sc->sc_dev, &ma, udaprint);
266 }
267 
268 /*
269  * Start a transfer if there are free resources available, otherwise
270  * let it go in udaready, forget it for now.
271  * Called from mscp routines.
272  */
273 void
274 udago(device_t dv, struct mscp_xi *mxi)
275 {
276 	struct uda_softc *sc = device_private(dv);
277 	struct uba_unit *uu;
278 	struct buf *bp = mxi->mxi_bp;
279 	int err;
280 
281 	/*
282 	 * If we already have transfers queued, don't try to load
283 	 * the map again.
284 	 */
285 	if (sc->sc_inq == 0) {
286 		err = bus_dmamap_load(sc->sc_dmat, mxi->mxi_dmam,
287 		    bp->b_data, bp->b_bcount,
288 		    (bp->b_flags & B_PHYS ? bp->b_proc : 0), BUS_DMA_NOWAIT);
289 		if (err == 0) {
290 			mscp_dgo(sc->sc_softc, mxi);
291 			return;
292 		}
293 	}
294 	uu = malloc(sizeof(struct uba_unit), M_DEVBUF, M_NOWAIT|M_ZERO);
295 	if (uu == NULL)
296 		panic("udago: no mem");
297 	uu->uu_ready = udaready;
298 	uu->uu_dev = dv;
299 	uu->uu_ref = mxi;
300 	uba_enqueue(uu);
301 	sc->sc_inq++;
302 }
303 
304 /*
305  * Called if we have been blocked for resources, and resources
306  * have been freed again. Return 1 if we could start all
307  * transfers again, 0 if we still are waiting.
308  * Called from uba resource free routines.
309  */
310 int
311 udaready(struct uba_unit *uu)
312 {
313 	struct uda_softc *sc = device_private(uu->uu_dev);
314 	struct mscp_xi *mxi = uu->uu_ref;
315 	struct buf *bp = mxi->mxi_bp;
316 	int err;
317 
318 	err = bus_dmamap_load(sc->sc_dmat, mxi->mxi_dmam, bp->b_data,
319 	    bp->b_bcount, (bp->b_flags & B_PHYS ? bp->b_proc : 0),
320 	    BUS_DMA_NOWAIT);
321 
322 	if (err)
323 		return 0;
324 	mscp_dgo(sc->sc_softc, mxi);
325 	sc->sc_inq--;
326 	free(uu, M_DEVBUF);
327 	return 1;
328 }
329 
330 static const struct saerr {
331 	int	code;		/* error code (including UDA_ERR) */
332 	const char	*desc;		/* what it means: Efoo => foo error */
333 } saerr[] = {
334 	{ 0100001, "Eunibus packet read" },
335 	{ 0100002, "Eunibus packet write" },
336 	{ 0100003, "EUDA ROM and RAM parity" },
337 	{ 0100004, "EUDA RAM parity" },
338 	{ 0100005, "EUDA ROM parity" },
339 	{ 0100006, "Eunibus ring read" },
340 	{ 0100007, "Eunibus ring write" },
341 	{ 0100010, " unibus interrupt master failure" },
342 	{ 0100011, "Ehost access timeout" },
343 	{ 0100012, " host exceeded command limit" },
344 	{ 0100013, " unibus bus master failure" },
345 	{ 0100014, " DM XFC fatal error" },
346 	{ 0100015, " hardware timeout of instruction loop" },
347 	{ 0100016, " invalid virtual circuit id" },
348 	{ 0100017, "Eunibus interrupt write" },
349 	{ 0104000, "Efatal sequence" },
350 	{ 0104040, " D proc ALU" },
351 	{ 0104041, "ED proc control ROM parity" },
352 	{ 0105102, "ED proc w/no BD#2 or RAM parity" },
353 	{ 0105105, "ED proc RAM buffer" },
354 	{ 0105152, "ED proc SDI" },
355 	{ 0105153, "ED proc write mode wrap serdes" },
356 	{ 0105154, "ED proc read mode serdes, RSGEN & ECC" },
357 	{ 0106040, "EU proc ALU" },
358 	{ 0106041, "EU proc control reg" },
359 	{ 0106042, " U proc DFAIL/cntl ROM parity/BD #1 test CNT" },
360 	{ 0106047, " U proc const PROM err w/D proc running SDI test" },
361 	{ 0106055, " unexpected trap" },
362 	{ 0106071, "EU proc const PROM" },
363 	{ 0106072, "EU proc control ROM parity" },
364 	{ 0106200, "Estep 1 data" },
365 	{ 0107103, "EU proc RAM parity" },
366 	{ 0107107, "EU proc RAM buffer" },
367 	{ 0107115, " test count wrong (BD 12)" },
368 	{ 0112300, "Estep 2" },
369 	{ 0122240, "ENPR" },
370 	{ 0122300, "Estep 3" },
371 	{ 0142300, "Estep 4" },
372 	{ 0, " unknown error code" }
373 };
374 
375 /*
376  * If the error bit was set in the controller status register, gripe,
377  * then (optionally) reset the controller and requeue pending transfers.
378  */
379 void
380 udasaerror(device_t dev, int doreset)
381 {
382 	struct	uda_softc *sc = device_private(dev);
383 	int code = bus_space_read_2(sc->sc_iot, sc->sc_sah, 0);
384 	const struct saerr *e;
385 
386 	if ((code & MP_ERR) == 0)
387 		return;
388 	for (e = saerr; e->code; e++)
389 		if (e->code == code)
390 			break;
391 	aprint_error_dev(sc->sc_dev, "controller error, sa=0%o (%s%s)\n",
392 		code, e->desc + 1, *e->desc == 'E' ? " error" : "");
393 #if 0 /* XXX we just avoid panic when autoconfig non-existent KFQSA devices */
394 	if (doreset) {
395 		mscp_requeue(sc->sc_softc);
396 /*		(void) udainit(sc);	XXX */
397 	}
398 #endif
399 }
400 
401 /*
402  * Interrupt routine.  Depending on the state of the controller,
403  * continue initialisation, or acknowledge command and response
404  * interrupts, and process responses.
405  */
406 static void
407 udaintr(void *arg)
408 {
409 	struct uda_softc *sc = arg;
410 
411 	/* ctlr fatal error */
412 	if (bus_space_read_2(sc->sc_iot, sc->sc_sah, 0) & MP_ERR) {
413 		udasaerror(sc->sc_dev, 1);
414 		return;
415 	}
416 	/*
417 	 * Handle buffer purge requests.
418 	 * XXX - should be done in bus_dma_sync().
419 	 */
420 #ifdef notyet
421 	if (ud->mp_ca.ca_bdp) {
422 		if (sc->sc_uh->uh_ubapurge)
423 			(*sc->sc_uh->uh_ubapurge)(sc->sc_uh,
424 			    ud->mp_ca.ca_bdp);
425 		/* signal purge complete */
426 		bus_space_write_2(sc->sc_iot, sc->sc_sah, 0, 0);
427 	}
428 #endif
429 
430 	mscp_intr(sc->sc_softc);
431 }
432 
433 /*
434  * A Unibus reset has occurred on UBA uban.  Reinitialise the controller(s)
435  * on that Unibus, and requeue outstanding I/O.
436  */
437 static void
438 udareset(device_t dev)
439 {
440 	struct uda_softc *sc = device_private(dev);
441 	/*
442 	 * Our BDP (if any) is gone; our command (if any) is
443 	 * flushed; the device is no longer mapped; and the
444 	 * UDA50 is not yet initialised.
445 	 */
446 	if (sc->sc_unit.uu_bdp) {
447 		/* printf("<%d>", UBAI_BDP(sc->sc_unit.uu_bdp)); */
448 		sc->sc_unit.uu_bdp = 0;
449 	}
450 
451 	/* reset queues and requeue pending transfers */
452 	mscp_requeue(sc->sc_softc);
453 
454 	/*
455 	 * If it fails to initialise we will notice later and
456 	 * try again (and again...).  Do not call udastart()
457 	 * here; it will be done after the controller finishes
458 	 * initialisation.
459 	 */
460 /* XXX	if (udainit(sc)) */
461 		printf(" (hung)");
462 }
463 
464 void
465 udactlrdone(device_t dev)
466 {
467 	struct uda_softc *sc = device_private(dev);
468 	int s;
469 
470 	s = spluba();
471 	uba_done(sc->sc_uh);
472 	splx(s);
473 }
474