xref: /netbsd-src/sys/dev/qbus/uda.c (revision 481fca6e59249d8ffcf24fef7cfbe7b131bfb080)
1 /*	$NetBSD: uda.c,v 1.38 2000/06/10 19:44:55 ragge Exp $	*/
2 /*
3  * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
4  * Copyright (c) 1988 Regents of the University of California.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * Chris Torek.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed by the University of
21  *	California, Berkeley and its contributors.
22  * 4. Neither the name of the University nor the names of its contributors
23  *    may be used to endorse or promote products derived from this software
24  *    without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  *	@(#)uda.c	7.32 (Berkeley) 2/13/91
39  */
40 
41 /*
42  * UDA50 disk device driver
43  */
44 
45 #include <sys/param.h>
46 #include <sys/kernel.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/buf.h>
50 #include <sys/malloc.h>
51 
52 #include <machine/bus.h>
53 #include <machine/sid.h>
54 
55 #include <dev/qbus/ubavar.h>
56 
57 #include <dev/mscp/mscp.h>
58 #include <dev/mscp/mscpreg.h>
59 #include <dev/mscp/mscpvar.h>
60 
61 #include "ioconf.h"
62 
63 /*
64  * Software status, per controller.
65  */
66 struct	uda_softc {
67 	struct	device sc_dev;	/* Autoconfig info */
68 	struct	evcnt sc_intrcnt; /* Interrupt counting */
69 	struct	uba_unit sc_unit; /* Struct common for UBA to communicate */
70 	struct	buf_queue sc_bufq;	/* bufs awaiting for resources */
71 	struct	mscp_pack *sc_uuda;	/* Unibus address of uda struct */
72 	struct	mscp_pack sc_uda;	/* Struct for uda communication */
73 	bus_dma_tag_t		sc_dmat;
74 	bus_space_tag_t		sc_iot;
75 	bus_space_handle_t	sc_iph;
76 	bus_space_handle_t	sc_sah;
77 	bus_dmamap_t		sc_cmap;/* Control structures */
78 	struct	mscp *sc_mscp;		/* Keep pointer to active mscp */
79 	struct	mscp_softc *sc_softc;	/* MSCP info (per mscpvar.h) */
80 	int	sc_wticks;	/* watchdog timer ticks */
81 	int	sc_inq;
82 };
83 
84 static	int	udamatch __P((struct device *, struct cfdata *, void *));
85 static	void	udaattach __P((struct device *, struct device *, void *));
86 static	void	udareset(struct device *);
87 static	void	udaintr __P((void *));
88 int	udaready __P((struct uba_unit *));
89 void	udactlrdone __P((struct device *));
90 int	udaprint __P((void *, const char *));
91 void	udasaerror __P((struct device *, int));
92 void	udago __P((struct device *, struct mscp_xi *));
93 
94 struct	cfattach mtc_ca = {
95 	sizeof(struct uda_softc), udamatch, udaattach
96 };
97 
98 struct	cfattach uda_ca = {
99 	sizeof(struct uda_softc), udamatch, udaattach
100 };
101 
102 /*
103  * More driver definitions, for generic MSCP code.
104  */
105 struct	mscp_ctlr uda_mscp_ctlr = {
106 	udactlrdone,
107 	udago,
108 	udasaerror,
109 };
110 
111 /*
112  * Miscellaneous private variables.
113  */
114 static	int	ivec_no;
115 
116 int
117 udaprint(aux, name)
118 	void	*aux;
119 	const char	*name;
120 {
121 	if (name)
122 		printf("%s: mscpbus", name);
123 	return UNCONF;
124 }
125 
126 /*
127  * Poke at a supposed UDA50 to see if it is there.
128  */
129 int
130 udamatch(parent, cf, aux)
131 	struct device *parent;
132 	struct cfdata *cf;
133 	void *aux;
134 {
135 	struct	uba_attach_args *ua = aux;
136 	struct	mscp_softc mi;	/* Nice hack */
137 	struct	uba_softc *ubasc;
138 	int	tries;
139 
140 	/* Get an interrupt vector. */
141 	ubasc = (void *)parent;
142 	ivec_no = ubasc->uh_lastiv - 4;
143 
144 	mi.mi_iot = ua->ua_iot;
145 	mi.mi_iph = ua->ua_ioh;
146 	mi.mi_sah = ua->ua_ioh + 2;
147 	mi.mi_swh = ua->ua_ioh + 2;
148 
149 	/*
150 	 * Initialise the controller (partially).  The UDA50 programmer's
151 	 * manual states that if initialisation fails, it should be retried
152 	 * at least once, but after a second failure the port should be
153 	 * considered `down'; it also mentions that the controller should
154 	 * initialise within ten seconds.  Or so I hear; I have not seen
155 	 * this manual myself.
156 	 */
157 	tries = 0;
158 again:
159 
160 	bus_space_write_2(mi.mi_iot, mi.mi_iph, 0, 0); /* Start init */
161 	if (mscp_waitstep(&mi, MP_STEP1, MP_STEP1) == 0)
162 		return 0; /* Nothing here... */
163 
164 	bus_space_write_2(mi.mi_iot, mi.mi_sah, 0,
165 	    MP_ERR | (NCMDL2 << 11) | (NRSPL2 << 8) | MP_IE | (ivec_no >> 2));
166 
167 	if (mscp_waitstep(&mi, MP_STEP2, MP_STEP2) == 0) {
168 		printf("udaprobe: init step2 no change. sa=%x\n",
169 		    bus_space_read_2(mi.mi_iot, mi.mi_sah, 0));
170 		goto bad;
171 	}
172 
173 	/* should have interrupted by now */
174 	return 1;
175 bad:
176 	if (++tries < 2)
177 		goto again;
178 	return 0;
179 }
180 
181 void
182 udaattach(parent, self, aux)
183 	struct device *parent, *self;
184 	void *aux;
185 {
186 	struct	uda_softc *sc = (void *)self;
187 	struct	uba_attach_args *ua = aux;
188 	struct	uba_softc *uh = (void *)parent;
189 	struct	mscp_attach_args ma;
190 	int	ctlr, error, rseg;
191 	bus_dma_segment_t seg;
192 
193 	printf("\n");
194 
195 	uh->uh_lastiv -= 4;	/* remove dynamic interrupt vector */
196 
197 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
198 		udaintr, sc, &sc->sc_intrcnt);
199 	uba_reset_establish(udareset, &sc->sc_dev);
200 	evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
201 		sc->sc_dev.dv_xname, "intr");
202 
203 	sc->sc_iot = ua->ua_iot;
204 	sc->sc_iph = ua->ua_ioh;
205 	sc->sc_sah = ua->ua_ioh + 2;
206 	sc->sc_dmat = ua->ua_dmat;
207 	ctlr = sc->sc_dev.dv_unit;
208 	BUFQ_INIT(&sc->sc_bufq);
209 
210 	/*
211 	 * Fill in the uba_unit struct, so we can communicate with the uba.
212 	 */
213 	sc->sc_unit.uu_softc = sc;	/* Backpointer to softc */
214 	sc->sc_unit.uu_ready = udaready;/* go routine called from adapter */
215 	sc->sc_unit.uu_keepbdp = vax_cputype == VAX_750 ? 1 : 0;
216 
217 	/*
218 	 * Map the communication area and command and
219 	 * response packets into Unibus space.
220 	 */
221 	if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mscp_pack),
222 	    NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
223 		printf("Alloc ctrl area %d\n", error);
224 		return;
225 	}
226 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
227 	    sizeof(struct mscp_pack), (caddr_t *) &sc->sc_uda,
228 	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
229 		printf("Map ctrl area %d\n", error);
230 err:		bus_dmamem_free(sc->sc_dmat, &seg, rseg);
231 		return;
232 	}
233 	if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct mscp_pack),
234 	    1, sizeof(struct mscp_pack), 0, BUS_DMA_NOWAIT, &sc->sc_cmap))) {
235 		printf("Create DMA map %d\n", error);
236 err2:		bus_dmamem_unmap(sc->sc_dmat, (caddr_t)&sc->sc_uda,
237 		    sizeof(struct mscp_pack));
238 		goto err;
239 	}
240 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap,
241 	    &sc->sc_uda, sizeof(struct mscp_pack), 0, BUS_DMA_NOWAIT))) {
242 		printf("Load ctrl map %d\n", error);
243 		bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap);
244 		goto err2;
245 	}
246 
247 	bzero(&sc->sc_uda, sizeof (struct mscp_pack));
248 
249 	/*
250 	 * The only thing that differ UDA's and Tape ctlr's is
251 	 * their vcid. Beacuse there are no way to determine which
252 	 * ctlr type it is, we check what is generated and later
253 	 * set the correct vcid.
254 	 */
255 	ma.ma_type = (strcmp(self->dv_cfdata->cf_driver->cd_name, "mtc") ?
256 	    MSCPBUS_DISK : MSCPBUS_TAPE);
257 
258 	ma.ma_mc = &uda_mscp_ctlr;
259 	ma.ma_type |= MSCPBUS_UDA;
260 	ma.ma_uda = &sc->sc_uda;
261 	ma.ma_softc = &sc->sc_softc;
262 	ma.ma_iot = sc->sc_iot;
263 	ma.ma_iph = sc->sc_iph;
264 	ma.ma_sah = sc->sc_sah;
265 	ma.ma_swh = sc->sc_sah;
266 	ma.ma_dmat = sc->sc_dmat;
267 	ma.ma_dmam = sc->sc_cmap;
268 	ma.ma_ivec = ivec_no;
269 	ma.ma_ctlrnr = (ua->ua_iaddr == 0172150 ? 0 : 1);	/* XXX */
270 	ma.ma_adapnr = uh->uh_nr;
271 	config_found(&sc->sc_dev, &ma, udaprint);
272 }
273 
274 /*
275  * Start a transfer if there are free resources available, otherwise
276  * let it go in udaready, forget it for now.
277  * Called from mscp routines.
278  */
279 void
280 udago(usc, mxi)
281 	struct device *usc;
282 	struct mscp_xi *mxi;
283 {
284 	struct uda_softc *sc = (void *)usc;
285 	struct uba_unit *uu;
286 	struct buf *bp = mxi->mxi_bp;
287 	int err;
288 
289 	/*
290 	 * If we already have transfers queued, don't try to load
291 	 * the map again.
292 	 */
293 	if (sc->sc_inq == 0) {
294 		err = bus_dmamap_load(sc->sc_dmat, mxi->mxi_dmam,
295 		    bp->b_data,
296 		    bp->b_bcount, bp->b_proc, BUS_DMA_NOWAIT);
297 		if (err == 0) {
298 			mscp_dgo(sc->sc_softc, mxi);
299 			return;
300 		}
301 	}
302 	uu = malloc(sizeof(struct uba_unit), M_DEVBUF, M_NOWAIT);
303 	if (uu == 0)
304 		panic("udago: no mem");
305 	uu->uu_ready = udaready;
306 	uu->uu_softc = sc;
307 	uu->uu_ref = mxi;
308 	uba_enqueue(uu);
309 	sc->sc_inq++;
310 }
311 
312 /*
313  * Called if we have been blocked for resources, and resources
314  * have been freed again. Return 1 if we could start all
315  * transfers again, 0 if we still are waiting.
316  * Called from uba resource free routines.
317  */
318 int
319 udaready(uu)
320 	struct uba_unit *uu;
321 {
322 	struct uda_softc *sc = uu->uu_softc;
323 	struct mscp_xi *mxi = uu->uu_ref;
324 	struct buf *bp = mxi->mxi_bp;
325 	int err;
326 
327 	err = bus_dmamap_load(sc->sc_dmat, mxi->mxi_dmam, bp->b_data,
328 	    bp->b_bcount, bp->b_proc, BUS_DMA_NOWAIT);
329 	if (err)
330 		return 0;
331 	mscp_dgo(sc->sc_softc, mxi);
332 	sc->sc_inq--;
333 	free(uu, M_DEVBUF);
334 	return 1;
335 }
336 
337 static struct saerr {
338 	int	code;		/* error code (including UDA_ERR) */
339 	char	*desc;		/* what it means: Efoo => foo error */
340 } saerr[] = {
341 	{ 0100001, "Eunibus packet read" },
342 	{ 0100002, "Eunibus packet write" },
343 	{ 0100003, "EUDA ROM and RAM parity" },
344 	{ 0100004, "EUDA RAM parity" },
345 	{ 0100005, "EUDA ROM parity" },
346 	{ 0100006, "Eunibus ring read" },
347 	{ 0100007, "Eunibus ring write" },
348 	{ 0100010, " unibus interrupt master failure" },
349 	{ 0100011, "Ehost access timeout" },
350 	{ 0100012, " host exceeded command limit" },
351 	{ 0100013, " unibus bus master failure" },
352 	{ 0100014, " DM XFC fatal error" },
353 	{ 0100015, " hardware timeout of instruction loop" },
354 	{ 0100016, " invalid virtual circuit id" },
355 	{ 0100017, "Eunibus interrupt write" },
356 	{ 0104000, "Efatal sequence" },
357 	{ 0104040, " D proc ALU" },
358 	{ 0104041, "ED proc control ROM parity" },
359 	{ 0105102, "ED proc w/no BD#2 or RAM parity" },
360 	{ 0105105, "ED proc RAM buffer" },
361 	{ 0105152, "ED proc SDI" },
362 	{ 0105153, "ED proc write mode wrap serdes" },
363 	{ 0105154, "ED proc read mode serdes, RSGEN & ECC" },
364 	{ 0106040, "EU proc ALU" },
365 	{ 0106041, "EU proc control reg" },
366 	{ 0106042, " U proc DFAIL/cntl ROM parity/BD #1 test CNT" },
367 	{ 0106047, " U proc const PROM err w/D proc running SDI test" },
368 	{ 0106055, " unexpected trap" },
369 	{ 0106071, "EU proc const PROM" },
370 	{ 0106072, "EU proc control ROM parity" },
371 	{ 0106200, "Estep 1 data" },
372 	{ 0107103, "EU proc RAM parity" },
373 	{ 0107107, "EU proc RAM buffer" },
374 	{ 0107115, " test count wrong (BD 12)" },
375 	{ 0112300, "Estep 2" },
376 	{ 0122240, "ENPR" },
377 	{ 0122300, "Estep 3" },
378 	{ 0142300, "Estep 4" },
379 	{ 0, " unknown error code" }
380 };
381 
382 /*
383  * If the error bit was set in the controller status register, gripe,
384  * then (optionally) reset the controller and requeue pending transfers.
385  */
386 void
387 udasaerror(usc, doreset)
388 	struct device *usc;
389 	int doreset;
390 {
391 	struct	uda_softc *sc = (void *)usc;
392 	int code = bus_space_read_2(sc->sc_iot, sc->sc_sah, 0);
393 	struct saerr *e;
394 
395 	if ((code & MP_ERR) == 0)
396 		return;
397 	for (e = saerr; e->code; e++)
398 		if (e->code == code)
399 			break;
400 	printf("%s: controller error, sa=0%o (%s%s)\n",
401 		sc->sc_dev.dv_xname, code, e->desc + 1,
402 		*e->desc == 'E' ? " error" : "");
403 #if 0 /* XXX we just avoid panic when autoconfig non-existent KFQSA devices */
404 	if (doreset) {
405 		mscp_requeue(sc->sc_softc);
406 /*		(void) udainit(sc);	XXX */
407 	}
408 #endif
409 }
410 
411 /*
412  * Interrupt routine.  Depending on the state of the controller,
413  * continue initialisation, or acknowledge command and response
414  * interrupts, and process responses.
415  */
416 static void
417 udaintr(arg)
418 	void *arg;
419 {
420 	struct uda_softc *sc = arg;
421 	struct uba_softc *uh;
422 	struct mscp_pack *ud;
423 
424 	sc->sc_wticks = 0;	/* reset interrupt watchdog */
425 
426 	/* ctlr fatal error */
427 	if (bus_space_read_2(sc->sc_iot, sc->sc_sah, 0) & MP_ERR) {
428 		udasaerror(&sc->sc_dev, 1);
429 		return;
430 	}
431 	ud = &sc->sc_uda;
432 	/*
433 	 * Handle buffer purge requests.
434 	 * XXX - should be done in bus_dma_sync().
435 	 */
436 	uh = (void *)sc->sc_dev.dv_parent;
437 	if (ud->mp_ca.ca_bdp) {
438 		if (uh->uh_ubapurge)
439 			(*uh->uh_ubapurge)(uh, ud->mp_ca.ca_bdp);
440 		ud->mp_ca.ca_bdp = 0;
441 		/* signal purge complete */
442 		bus_space_write_2(sc->sc_iot, sc->sc_sah, 0, 0);
443 	}
444 
445 	mscp_intr(sc->sc_softc);
446 }
447 
448 /*
449  * A Unibus reset has occurred on UBA uban.  Reinitialise the controller(s)
450  * on that Unibus, and requeue outstanding I/O.
451  */
452 static void
453 udareset(struct device *dev)
454 {
455 	struct uda_softc *sc = (void *)dev;
456 	/*
457 	 * Our BDP (if any) is gone; our command (if any) is
458 	 * flushed; the device is no longer mapped; and the
459 	 * UDA50 is not yet initialised.
460 	 */
461 	if (sc->sc_unit.uu_bdp) {
462 		/* printf("<%d>", UBAI_BDP(sc->sc_unit.uu_bdp)); */
463 		sc->sc_unit.uu_bdp = 0;
464 	}
465 
466 	/* reset queues and requeue pending transfers */
467 	mscp_requeue(sc->sc_softc);
468 
469 	/*
470 	 * If it fails to initialise we will notice later and
471 	 * try again (and again...).  Do not call udastart()
472 	 * here; it will be done after the controller finishes
473 	 * initialisation.
474 	 */
475 /* XXX	if (udainit(sc)) */
476 		printf(" (hung)");
477 }
478 
479 void
480 udactlrdone(usc)
481 	struct device *usc;
482 {
483 	struct uda_softc *sc = (void *)usc;
484 
485 	uba_done((struct uba_softc *)sc->sc_dev.dv_parent);
486 }
487