1 /* $NetBSD: dhu.c,v 1.20 2000/06/05 00:09:18 matt Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 #include <machine/scb.h> 55 56 #include <dev/qbus/ubavar.h> 57 58 #include <dev/qbus/dhureg.h> 59 60 #include "ioconf.h" 61 62 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 63 64 #define NDHULINE 16 65 66 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 67 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 68 69 struct dhu_softc { 70 struct device sc_dev; /* Device struct used by config */ 71 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 72 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 73 int sc_type; /* controller type, DHU or DHV */ 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 bus_dma_tag_t sc_dmat; 77 struct { 78 struct tty *dhu_tty; /* what we work on */ 79 bus_dmamap_t dhu_dmah; 80 int dhu_state; /* to manage TX output status */ 81 short dhu_cc; /* character count on TX */ 82 short dhu_modem; /* modem bits state */ 83 } sc_dhu[NDHULINE]; 84 }; 85 86 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 87 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 88 89 #define STATE_IDLE 000 /* no current output in progress */ 90 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 91 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 92 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 93 94 /* Flags used to monitor modem bits, make them understood outside driver */ 95 96 #define DML_DTR TIOCM_DTR 97 #define DML_RTS TIOCM_RTS 98 #define DML_CTS TIOCM_CTS 99 #define DML_DCD TIOCM_CD 100 #define DML_RI TIOCM_RI 101 #define DML_DSR TIOCM_DSR 102 #define DML_BRK 0100000 /* no equivalent, we will mask */ 103 104 #define DHU_READ_WORD(reg) \ 105 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 106 #define DHU_WRITE_WORD(reg, val) \ 107 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 108 #define DHU_READ_BYTE(reg) \ 109 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 110 #define DHU_WRITE_BYTE(reg, val) \ 111 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 112 113 114 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 115 /* a baud rate from the same group. So limiting to B is likely */ 116 /* best, although clone boards like the ABLE QHV allow all settings. */ 117 118 static struct speedtab dhuspeedtab[] = { 119 { 0, 0 }, /* Groups */ 120 { 50, DHU_LPR_B50 }, /* A */ 121 { 75, DHU_LPR_B75 }, /* B */ 122 { 110, DHU_LPR_B110 }, /* A and B */ 123 { 134, DHU_LPR_B134 }, /* A and B */ 124 { 150, DHU_LPR_B150 }, /* B */ 125 { 300, DHU_LPR_B300 }, /* A and B */ 126 { 600, DHU_LPR_B600 }, /* A and B */ 127 { 1200, DHU_LPR_B1200 }, /* A and B */ 128 { 1800, DHU_LPR_B1800 }, /* B */ 129 { 2000, DHU_LPR_B2000 }, /* B */ 130 { 2400, DHU_LPR_B2400 }, /* A and B */ 131 { 4800, DHU_LPR_B4800 }, /* A and B */ 132 { 7200, DHU_LPR_B7200 }, /* A */ 133 { 9600, DHU_LPR_B9600 }, /* A and B */ 134 { 19200, DHU_LPR_B19200 }, /* B */ 135 { 38400, DHU_LPR_B38400 }, /* A */ 136 { -1, -1 } 137 }; 138 139 static int dhu_match __P((struct device *, struct cfdata *, void *)); 140 static void dhu_attach __P((struct device *, struct device *, void *)); 141 static void dhurint __P((void *)); 142 static void dhuxint __P((void *)); 143 static void dhustart __P((struct tty *)); 144 static int dhuparam __P((struct tty *, struct termios *)); 145 static int dhuiflow __P((struct tty *, int)); 146 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 147 int dhuopen __P((dev_t, int, int, struct proc *)); 148 int dhuclose __P((dev_t, int, int, struct proc *)); 149 int dhuread __P((dev_t, struct uio *, int)); 150 int dhuwrite __P((dev_t, struct uio *, int)); 151 int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); 152 void dhustop __P((struct tty *, int)); 153 struct tty * dhutty __P((dev_t)); 154 155 struct cfattach dhu_ca = { 156 sizeof(struct dhu_softc), dhu_match, dhu_attach 157 }; 158 159 /* Autoconfig handles: setup the controller to interrupt, */ 160 /* then complete the housecleaning for full operation */ 161 162 static int 163 dhu_match(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 struct uba_attach_args *ua = aux; 169 int n; 170 171 /* Reset controller to initialize, enable TX/RX interrupts */ 172 /* to catch floating vector info elsewhere when completed */ 173 174 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 175 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 176 177 /* Now wait up to 3 seconds for self-test to complete. */ 178 179 for (n = 0; n < 300; n++) { 180 DELAY(10000); 181 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 182 DHU_CSR_MASTER_RESET) == 0) 183 break; 184 } 185 186 /* If the RESET did not clear after 3 seconds, */ 187 /* the controller must be broken. */ 188 189 if (n >= 300) 190 return 0; 191 192 /* Check whether diagnostic run has signalled a failure. */ 193 194 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 195 DHU_CSR_DIAG_FAIL) != 0) 196 return 0; 197 198 return 1; 199 } 200 201 static void 202 dhu_attach(parent, self, aux) 203 struct device *parent, *self; 204 void *aux; 205 { 206 struct dhu_softc *sc = (void *)self; 207 struct uba_attach_args *ua = aux; 208 unsigned c; 209 int n, i; 210 211 sc->sc_iot = ua->ua_iot; 212 sc->sc_ioh = ua->ua_ioh; 213 sc->sc_dmat = ua->ua_dmat; 214 /* Process the 8 bytes of diagnostic info put into */ 215 /* the FIFO following the master reset operation. */ 216 217 printf("\n%s:", self->dv_xname); 218 for (n = 0; n < 8; n++) { 219 c = DHU_READ_WORD(DHU_UBA_RBUF); 220 221 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 222 if ((c&0200) == 0000) 223 printf(" rom(%d) version %d", 224 ((c>>1)&01), ((c>>2)&037)); 225 else if (((c>>2)&07) != 0) 226 printf(" diag-error(proc%d)=%x", 227 ((c>>1)&01), ((c>>2)&07)); 228 } 229 } 230 231 c = DHU_READ_WORD(DHU_UBA_STAT); 232 233 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 234 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 235 236 for (i = 0; i < sc->sc_type; i++) { 237 struct tty *tp; 238 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 239 sc->sc_dhu[i].dhu_state = STATE_IDLE; 240 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 241 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 242 &sc->sc_dhu[i].dhu_dmah); 243 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 244 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 245 246 } 247 248 /* Now establish RX & TX interrupt handlers */ 249 250 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 251 dhurint, sc, &sc->sc_rintrcnt); 252 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 253 dhuxint, sc, &sc->sc_tintrcnt); 254 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 255 sc->sc_dev.dv_xname, "rintr"); 256 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 257 sc->sc_dev.dv_xname, "tintr"); 258 } 259 260 /* Receiver Interrupt */ 261 262 static void 263 dhurint(arg) 264 void *arg; 265 { 266 struct dhu_softc *sc = arg; 267 struct tty *tp; 268 int cc, line; 269 unsigned c, delta; 270 int overrun = 0; 271 272 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 273 274 /* Ignore diagnostic FIFO entries. */ 275 276 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 277 continue; 278 279 cc = c & 0xFF; 280 line = DHU_LINE(c>>8); 281 tp = sc->sc_dhu[line].dhu_tty; 282 283 /* LINK.TYPE is set so we get modem control FIFO entries */ 284 285 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 286 c = (c << 8); 287 /* Do MDMBUF flow control, wakeup sleeping opens */ 288 if (c & DHU_STAT_DCD) { 289 if (!(tp->t_state & TS_CARR_ON)) 290 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 291 } 292 else if ((tp->t_state & TS_CARR_ON) && 293 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) 294 (void) dhumctl(sc, line, 0, DMSET); 295 296 /* Do CRTSCTS flow control */ 297 delta = c ^ sc->sc_dhu[line].dhu_modem; 298 sc->sc_dhu[line].dhu_modem = c; 299 if ((delta & DHU_STAT_CTS) && 300 (tp->t_state & TS_ISOPEN) && 301 (tp->t_cflag & CRTSCTS)) { 302 if (c & DHU_STAT_CTS) { 303 tp->t_state &= ~TS_TTSTOP; 304 ttstart(tp); 305 } else { 306 tp->t_state |= TS_TTSTOP; 307 dhustop(tp, 0); 308 } 309 } 310 continue; 311 } 312 313 if (!(tp->t_state & TS_ISOPEN)) { 314 wakeup((caddr_t)&tp->t_rawq); 315 continue; 316 } 317 318 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 319 log(LOG_WARNING, "%s: silo overflow, line %d\n", 320 sc->sc_dev.dv_xname, line); 321 overrun = 1; 322 } 323 /* A BREAK key will appear as a NULL with a framing error */ 324 if (c & DHU_RBUF_FRAMING_ERR) 325 cc |= TTY_FE; 326 if (c & DHU_RBUF_PARITY_ERR) 327 cc |= TTY_PE; 328 329 (*linesw[tp->t_line].l_rint)(cc, tp); 330 } 331 } 332 333 /* Transmitter Interrupt */ 334 335 static void 336 dhuxint(arg) 337 void *arg; 338 { 339 struct dhu_softc *sc = arg; 340 struct tty *tp; 341 int line; 342 343 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 344 345 tp = sc->sc_dhu[line].dhu_tty; 346 347 tp->t_state &= ~TS_BUSY; 348 if (tp->t_state & TS_FLUSH) 349 tp->t_state &= ~TS_FLUSH; 350 else { 351 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 352 sc->sc_dhu[line].dhu_cc -= 353 DHU_READ_WORD(DHU_UBA_TBUFCNT); 354 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 355 sc->sc_dhu[line].dhu_cc = 0; 356 } 357 358 sc->sc_dhu[line].dhu_state = STATE_IDLE; 359 360 if (tp->t_line) 361 (*linesw[tp->t_line].l_start)(tp); 362 else 363 dhustart(tp); 364 } 365 366 int 367 dhuopen(dev, flag, mode, p) 368 dev_t dev; 369 int flag, mode; 370 struct proc *p; 371 { 372 struct tty *tp; 373 int unit, line; 374 struct dhu_softc *sc; 375 int s, error = 0; 376 377 unit = DHU_M2U(minor(dev)); 378 line = DHU_LINE(minor(dev)); 379 380 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 381 return (ENXIO); 382 383 sc = dhu_cd.cd_devs[unit]; 384 385 if (line >= sc->sc_type) 386 return ENXIO; 387 388 s = spltty(); 389 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 390 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 391 (void) splx(s); 392 393 tp = sc->sc_dhu[line].dhu_tty; 394 395 tp->t_oproc = dhustart; 396 tp->t_param = dhuparam; 397 tp->t_hwiflow = dhuiflow; 398 tp->t_dev = dev; 399 if ((tp->t_state & TS_ISOPEN) == 0) { 400 ttychars(tp); 401 if (tp->t_ispeed == 0) { 402 tp->t_iflag = TTYDEF_IFLAG; 403 tp->t_oflag = TTYDEF_OFLAG; 404 tp->t_cflag = TTYDEF_CFLAG; 405 tp->t_lflag = TTYDEF_LFLAG; 406 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 407 } 408 (void) dhuparam(tp, &tp->t_termios); 409 ttsetwater(tp); 410 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 411 return (EBUSY); 412 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 413 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 414 tp->t_state |= TS_CARR_ON; 415 s = spltty(); 416 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 417 !(tp->t_state & TS_CARR_ON)) { 418 tp->t_wopen++; 419 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 420 TTIPRI | PCATCH, ttopen, 0); 421 tp->t_wopen--; 422 if (error) 423 break; 424 } 425 (void) splx(s); 426 if (error) 427 return (error); 428 return ((*linesw[tp->t_line].l_open)(dev, tp)); 429 } 430 431 /*ARGSUSED*/ 432 int 433 dhuclose(dev, flag, mode, p) 434 dev_t dev; 435 int flag, mode; 436 struct proc *p; 437 { 438 struct tty *tp; 439 int unit, line; 440 struct dhu_softc *sc; 441 442 unit = DHU_M2U(minor(dev)); 443 line = DHU_LINE(minor(dev)); 444 445 sc = dhu_cd.cd_devs[unit]; 446 447 tp = sc->sc_dhu[line].dhu_tty; 448 449 (*linesw[tp->t_line].l_close)(tp, flag); 450 451 /* Make sure a BREAK state is not left enabled. */ 452 453 (void) dhumctl(sc, line, DML_BRK, DMBIC); 454 455 /* Do a hangup if so required. */ 456 457 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 458 !(tp->t_state & TS_ISOPEN)) 459 (void) dhumctl(sc, line, 0, DMSET); 460 461 return (ttyclose(tp)); 462 } 463 464 int 465 dhuread(dev, uio, flag) 466 dev_t dev; 467 struct uio *uio; 468 { 469 struct dhu_softc *sc; 470 struct tty *tp; 471 472 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 473 474 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 475 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 476 } 477 478 int 479 dhuwrite(dev, uio, flag) 480 dev_t dev; 481 struct uio *uio; 482 { 483 struct dhu_softc *sc; 484 struct tty *tp; 485 486 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 487 488 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 489 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 490 } 491 492 /*ARGSUSED*/ 493 int 494 dhuioctl(dev, cmd, data, flag, p) 495 dev_t dev; 496 u_long cmd; 497 caddr_t data; 498 int flag; 499 struct proc *p; 500 { 501 struct dhu_softc *sc; 502 struct tty *tp; 503 int unit, line; 504 int error; 505 506 unit = DHU_M2U(minor(dev)); 507 line = DHU_LINE(minor(dev)); 508 sc = dhu_cd.cd_devs[unit]; 509 tp = sc->sc_dhu[line].dhu_tty; 510 511 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 512 if (error >= 0) 513 return (error); 514 error = ttioctl(tp, cmd, data, flag, p); 515 if (error >= 0) 516 return (error); 517 518 switch (cmd) { 519 520 case TIOCSBRK: 521 (void) dhumctl(sc, line, DML_BRK, DMBIS); 522 break; 523 524 case TIOCCBRK: 525 (void) dhumctl(sc, line, DML_BRK, DMBIC); 526 break; 527 528 case TIOCSDTR: 529 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 530 break; 531 532 case TIOCCDTR: 533 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 534 break; 535 536 case TIOCMSET: 537 (void) dhumctl(sc, line, *(int *)data, DMSET); 538 break; 539 540 case TIOCMBIS: 541 (void) dhumctl(sc, line, *(int *)data, DMBIS); 542 break; 543 544 case TIOCMBIC: 545 (void) dhumctl(sc, line, *(int *)data, DMBIC); 546 break; 547 548 case TIOCMGET: 549 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 550 break; 551 552 default: 553 return (ENOTTY); 554 } 555 return (0); 556 } 557 558 struct tty * 559 dhutty(dev) 560 dev_t dev; 561 { 562 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 563 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 564 return (tp); 565 } 566 567 /*ARGSUSED*/ 568 void 569 dhustop(tp, flag) 570 struct tty *tp; 571 { 572 struct dhu_softc *sc; 573 int line; 574 int s; 575 576 s = spltty(); 577 578 if (tp->t_state & TS_BUSY) { 579 580 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 581 line = DHU_LINE(minor(tp->t_dev)); 582 583 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 584 585 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 586 587 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 588 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 589 DHU_READ_WORD(DHU_UBA_LNCTRL) | 590 DHU_LNCTRL_DMA_ABORT); 591 } 592 593 if (!(tp->t_state & TS_TTSTOP)) 594 tp->t_state |= TS_FLUSH; 595 } 596 (void) splx(s); 597 } 598 599 static void 600 dhustart(tp) 601 struct tty *tp; 602 { 603 struct dhu_softc *sc; 604 int line, cc; 605 int addr; 606 int s; 607 608 s = spltty(); 609 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 610 goto out; 611 if (tp->t_outq.c_cc <= tp->t_lowat) { 612 if (tp->t_state & TS_ASLEEP) { 613 tp->t_state &= ~TS_ASLEEP; 614 wakeup((caddr_t)&tp->t_outq); 615 } 616 selwakeup(&tp->t_wsel); 617 } 618 if (tp->t_outq.c_cc == 0) 619 goto out; 620 cc = ndqb(&tp->t_outq, 0); 621 if (cc == 0) 622 goto out; 623 624 tp->t_state |= TS_BUSY; 625 626 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 627 628 line = DHU_LINE(minor(tp->t_dev)); 629 630 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 631 632 sc->sc_dhu[line].dhu_cc = cc; 633 634 if (cc == 1) { 635 636 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 637 638 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 639 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 640 641 } else { 642 643 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 644 645 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 646 (tp->t_outq.c_cf - tp->t_outq.c_cs); 647 648 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 649 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 650 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 651 DHU_TBUFAD2_TX_ENABLE); 652 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 653 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 654 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 655 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 656 } 657 out: 658 (void) splx(s); 659 return; 660 } 661 662 static int 663 dhuparam(tp, t) 664 struct tty *tp; 665 struct termios *t; 666 { 667 struct dhu_softc *sc; 668 int cflag = t->c_cflag; 669 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 670 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 671 unsigned lpr, lnctrl; 672 int unit, line; 673 int s; 674 675 unit = DHU_M2U(minor(tp->t_dev)); 676 line = DHU_LINE(minor(tp->t_dev)); 677 678 sc = dhu_cd.cd_devs[unit]; 679 680 /* check requested parameters */ 681 if (ospeed < 0 || ispeed < 0) 682 return (EINVAL); 683 684 tp->t_ispeed = t->c_ispeed; 685 tp->t_ospeed = t->c_ospeed; 686 tp->t_cflag = cflag; 687 688 if (ospeed == 0) { 689 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 690 return (0); 691 } 692 693 s = spltty(); 694 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 695 696 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 697 698 switch (cflag & CSIZE) { 699 700 case CS5: 701 lpr |= DHU_LPR_5_BIT_CHAR; 702 break; 703 704 case CS6: 705 lpr |= DHU_LPR_6_BIT_CHAR; 706 break; 707 708 case CS7: 709 lpr |= DHU_LPR_7_BIT_CHAR; 710 break; 711 712 default: 713 lpr |= DHU_LPR_8_BIT_CHAR; 714 break; 715 } 716 717 if (cflag & PARENB) 718 lpr |= DHU_LPR_PARENB; 719 if (!(cflag & PARODD)) 720 lpr |= DHU_LPR_EPAR; 721 if (cflag & CSTOPB) 722 lpr |= DHU_LPR_2_STOP; 723 724 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 725 726 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 727 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 728 729 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 730 731 /* Setting LINK.TYPE enables modem signal change interrupts. */ 732 733 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 734 735 /* Enable the auto XON/XOFF feature on the controller */ 736 737 if (t->c_iflag & IXON) 738 lnctrl |= DHU_LNCTRL_OAUTO; 739 else 740 lnctrl &= ~DHU_LNCTRL_OAUTO; 741 742 if (t->c_iflag & IXOFF) 743 lnctrl |= DHU_LNCTRL_IAUTO; 744 else 745 lnctrl &= ~DHU_LNCTRL_IAUTO; 746 747 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 748 749 (void) splx(s); 750 return (0); 751 } 752 753 static int 754 dhuiflow(tp, flag) 755 struct tty *tp; 756 int flag; 757 { 758 struct dhu_softc *sc; 759 int line = DHU_LINE(minor(tp->t_dev)); 760 761 if (tp->t_cflag & CRTSCTS) { 762 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 763 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 764 return (1); 765 } 766 return (0); 767 } 768 769 static unsigned 770 dhumctl(sc, line, bits, how) 771 struct dhu_softc *sc; 772 int line, bits, how; 773 { 774 unsigned status; 775 unsigned lnctrl; 776 unsigned mbits; 777 int s; 778 779 s = spltty(); 780 781 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 782 783 mbits = 0; 784 785 /* external signals as seen from the port */ 786 787 status = DHU_READ_WORD(DHU_UBA_STAT); 788 789 if (status & DHU_STAT_CTS) 790 mbits |= DML_CTS; 791 792 if (status & DHU_STAT_DCD) 793 mbits |= DML_DCD; 794 795 if (status & DHU_STAT_DSR) 796 mbits |= DML_DSR; 797 798 if (status & DHU_STAT_RI) 799 mbits |= DML_RI; 800 801 /* internal signals/state delivered to port */ 802 803 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 804 805 if (lnctrl & DHU_LNCTRL_RTS) 806 mbits |= DML_RTS; 807 808 if (lnctrl & DHU_LNCTRL_DTR) 809 mbits |= DML_DTR; 810 811 if (lnctrl & DHU_LNCTRL_BREAK) 812 mbits |= DML_BRK; 813 814 switch (how) { 815 816 case DMSET: 817 mbits = bits; 818 break; 819 820 case DMBIS: 821 mbits |= bits; 822 break; 823 824 case DMBIC: 825 mbits &= ~bits; 826 break; 827 828 case DMGET: 829 (void) splx(s); 830 return (mbits); 831 } 832 833 if (mbits & DML_RTS) 834 lnctrl |= DHU_LNCTRL_RTS; 835 else 836 lnctrl &= ~DHU_LNCTRL_RTS; 837 838 if (mbits & DML_DTR) 839 lnctrl |= DHU_LNCTRL_DTR; 840 else 841 lnctrl &= ~DHU_LNCTRL_DTR; 842 843 if (mbits & DML_BRK) 844 lnctrl |= DHU_LNCTRL_BREAK; 845 else 846 lnctrl &= ~DHU_LNCTRL_BREAK; 847 848 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 849 850 (void) splx(s); 851 return (mbits); 852 } 853