1*5375dc7fSbjh21 /* $NetBSD: secreg.h,v 1.1 2006/10/01 12:39:35 bjh21 Exp $ */ 2*5375dc7fSbjh21 3*5375dc7fSbjh21 /* 4*5375dc7fSbjh21 * Ben Harris 2006 5*5375dc7fSbjh21 * 6*5375dc7fSbjh21 * This file is in the public domain. 7*5375dc7fSbjh21 */ 8*5375dc7fSbjh21 9*5375dc7fSbjh21 /* 10*5375dc7fSbjh21 * Register definitions for Acorn SCSI expansion cards (AKA30, AKA31, AKA32) 11*5375dc7fSbjh21 */ 12*5375dc7fSbjh21 13*5375dc7fSbjh21 /* 14*5375dc7fSbjh21 * Offsets are in bus_space units (words) 15*5375dc7fSbjh21 */ 16*5375dc7fSbjh21 17*5375dc7fSbjh21 /* Podule "fast" space */ 18*5375dc7fSbjh21 #define SEC_ROM 0x000 19*5375dc7fSbjh21 #define SEC_ISR 0x800 /* Interrupt status (read-only) */ 20*5375dc7fSbjh21 #define SEC_ISR_SBIC 0x08 /* Interrupt from WD33C93A SBIC */ 21*5375dc7fSbjh21 #define SEC_ISR_DMAC 0x02 /* TC uPD71071 DMAC */ 22*5375dc7fSbjh21 #define SEC_ISR_IRQ 0x01 /* OR of the above */ 23*5375dc7fSbjh21 #define SEC_CLRINT 0x800 /* Clear TC interrupt (write-only) */ 24*5375dc7fSbjh21 #define SEC_MPR 0xc00 /* Memory page register */ 25*5375dc7fSbjh21 #define SEC_MPR_UR 0x80 /* User reset */ 26*5375dc7fSbjh21 #define SEC_MPR_IE 0x40 /* Interrupts enabled */ 27*5375dc7fSbjh21 #define SEC_MPR_PAGE 0x3f /* EPROM/SRAM page address */ 28*5375dc7fSbjh21 29*5375dc7fSbjh21 /* Module space */ 30*5375dc7fSbjh21 #define SEC_SRAM 0x000 31*5375dc7fSbjh21 #define SEC_SBIC 0x800 32*5375dc7fSbjh21 #define SEC_DMAC 0xc00 33*5375dc7fSbjh21 34*5375dc7fSbjh21 /* The address lines of the DMAC are permuted. */ 35*5375dc7fSbjh21 #define DMAC(addr) ((addr) >> 1 | ((addr) & 1) << 7) 36*5375dc7fSbjh21 37*5375dc7fSbjh21 #define SEC_CLKFREQ 80 /* Clock speed in 100 kHz */ 38*5375dc7fSbjh21 #define SEC_NPAGES 16 39*5375dc7fSbjh21 #define SEC_PAGESIZE 4096 40*5375dc7fSbjh21 #define SEC_MEMSIZE (SEC_PAGESIZE * SEC_NPAGES) 41