1 /* $NetBSD: hcsc.c,v 1.7 2001/07/04 15:01:08 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 * 72 * Andy Armstrong gives some details of the HCCS SCSI cards at 73 * <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>. 74 */ 75 76 #include <sys/param.h> 77 78 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.7 2001/07/04 15:01:08 bjh21 Exp $"); 79 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/device.h> 83 #include <sys/buf.h> 84 #include <dev/scsipi/scsi_all.h> 85 #include <dev/scsipi/scsipi_all.h> 86 #include <dev/scsipi/scsiconf.h> 87 88 #include <dev/ic/ncr5380reg.h> 89 #include <dev/ic/ncr5380var.h> 90 91 #include <machine/bootconfig.h> 92 93 #include <dev/podulebus/podulebus.h> 94 #include <dev/podulebus/podules.h> 95 #include <dev/podulebus/powerromreg.h> 96 97 #include <dev/podulebus/hcscreg.h> 98 99 void hcsc_attach (struct device *, struct device *, void *); 100 int hcsc_match (struct device *, struct cfdata *, void *); 101 102 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *); 103 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *); 104 105 106 /* 107 * HCCS 8-bit SCSI softc structure. 108 * 109 * Contains the generic ncr5380 device node, podule information and 110 * global information required by the driver. 111 */ 112 113 struct hcsc_softc { 114 struct ncr5380_softc sc_ncr5380; 115 bus_space_tag_t sc_pdmat; 116 bus_space_handle_t sc_pdmah; 117 void *sc_ih; 118 struct evcnt sc_intrcnt; 119 }; 120 121 struct cfattach hcsc_ca = { 122 sizeof(struct hcsc_softc), hcsc_match, hcsc_attach 123 }; 124 125 /* 126 * Card probe function 127 * 128 * Just match the manufacturer and podule ID's 129 */ 130 131 int 132 hcsc_match(struct device *parent, struct cfdata *cf, void *aux) 133 { 134 struct podulebus_attach_args *pa = aux; 135 136 /* Normal ROM */ 137 if (pa->pa_product == PODULE_HCCS_IDESCSI && 138 strncmp(pa->pa_descr, "SCSI", 4) == 0) 139 return 1; 140 /* PowerROM */ 141 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 142 podulebus_initloader(pa) == 0 && 143 podloader_callloader(pa, 0, 0) == PRID_HCCS_SCSI1) 144 return 1; 145 return 0; 146 } 147 148 /* 149 * Card attach function 150 * 151 */ 152 153 void 154 hcsc_attach(struct device *parent, struct device *self, void *aux) 155 { 156 struct hcsc_softc *sc = (struct hcsc_softc *)self; 157 struct podulebus_attach_args *pa = aux; 158 u_char *iobase; 159 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8]; 160 161 sc->sc_ncr5380.sc_min_dma_len = 0; 162 sc->sc_ncr5380.sc_no_disconnect = 0; 163 sc->sc_ncr5380.sc_parity_disable = 0; 164 165 sc->sc_ncr5380.sc_dma_alloc = NULL; 166 sc->sc_ncr5380.sc_dma_free = NULL; 167 sc->sc_ncr5380.sc_dma_poll = NULL; 168 sc->sc_ncr5380.sc_dma_setup = NULL; 169 sc->sc_ncr5380.sc_dma_start = NULL; 170 sc->sc_ncr5380.sc_dma_eop = NULL; 171 sc->sc_ncr5380.sc_dma_stop = NULL; 172 sc->sc_ncr5380.sc_intr_on = NULL; 173 sc->sc_ncr5380.sc_intr_off = NULL; 174 175 #ifdef NCR5380_USE_BUS_SPACE 176 sc->sc_ncr5380.sc_regt = pa->pa_fast_t; 177 bus_space_map(sc->sc_ncr5380.sc_regt, 178 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 179 &sc->sc_ncr5380.sc_regh); 180 sc->sc_ncr5380.sci_r0 = 0; 181 sc->sc_ncr5380.sci_r1 = 1; 182 sc->sc_ncr5380.sci_r2 = 2; 183 sc->sc_ncr5380.sci_r3 = 3; 184 sc->sc_ncr5380.sci_r4 = 4; 185 sc->sc_ncr5380.sci_r5 = 5; 186 sc->sc_ncr5380.sci_r6 = 6; 187 sc->sc_ncr5380.sci_r7 = 7; 188 #else 189 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 190 sc->sc_ncr5380.sci_r0 = iobase + 0; 191 sc->sc_ncr5380.sci_r1 = iobase + 4; 192 sc->sc_ncr5380.sci_r2 = iobase + 8; 193 sc->sc_ncr5380.sci_r3 = iobase + 12; 194 sc->sc_ncr5380.sci_r4 = iobase + 16; 195 sc->sc_ncr5380.sci_r5 = iobase + 20; 196 sc->sc_ncr5380.sci_r6 = iobase + 24; 197 sc->sc_ncr5380.sci_r7 = iobase + 28; 198 #endif 199 sc->sc_pdmat = pa->pa_mod_t; 200 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 201 &sc->sc_pdmah); 202 203 sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490; 204 205 sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in; 206 sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out; 207 208 /* Provide an override for the host id */ 209 sc->sc_ncr5380.sc_channel.chan_id = 7; 210 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname); 211 (void)get_bootconf_option(boot_args, hi_option, 212 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id); 213 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys; 214 215 printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id); 216 217 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 218 self->dv_xname, "intr"); 219 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 220 sc, &sc->sc_intrcnt); 221 222 ncr5380_attach(&sc->sc_ncr5380); 223 } 224 225 #ifndef HCSC_TSIZE_OUT 226 #define HCSC_TSIZE_OUT 512 227 #endif 228 229 #ifndef HCSC_TSIZE_IN 230 #define HCSC_TSIZE_IN 512 231 #endif 232 233 #define TIMEOUT 1000000 234 235 static __inline int 236 hcsc_ready(struct ncr5380_softc *sc) 237 { 238 int i; 239 240 for (i = TIMEOUT; i > 0; i--) { 241 if ((NCR5380_READ(sc,sci_csr) & 242 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 243 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 244 return(1); 245 246 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 247 SCI_BUSY(sc) == 0) 248 return(0); 249 } 250 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 251 return(0); 252 } 253 254 255 256 /* Return zero on success. */ 257 static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 258 { 259 int timo; 260 for (timo = TIMEOUT; timo; timo--) { 261 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 262 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 263 SCI_BUSY(sc) == 0) { 264 return; 265 } 266 } 267 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 268 } 269 270 static int 271 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 272 u_char *data) 273 { 274 struct hcsc_softc *sc = (void *)ncr_sc; 275 bus_space_tag_t pdmat = sc->sc_pdmat; 276 bus_space_handle_t pdmah = sc->sc_pdmah; 277 int s, resid, len; 278 279 s = splbio(); 280 281 NCR5380_WRITE(ncr_sc, sci_mode, 282 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 283 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 284 285 resid = datalen; 286 while (resid > 0) { 287 len = min(resid, HCSC_TSIZE_IN); 288 if (hcsc_ready(ncr_sc) == 0) 289 goto interrupt; 290 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 291 data += len; 292 resid -= len; 293 } 294 295 hcsc_wait_not_req(ncr_sc); 296 297 interrupt: 298 SCI_CLR_INTR(ncr_sc); 299 NCR5380_WRITE(ncr_sc, sci_mode, 300 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 301 splx(s); 302 return datalen - resid; 303 } 304 305 static int 306 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 307 u_char *data) 308 { 309 struct hcsc_softc *sc = (void *)ncr_sc; 310 bus_space_tag_t pdmat = sc->sc_pdmat; 311 bus_space_handle_t pdmah = sc->sc_pdmah; 312 int i, s, icmd, resid; 313 314 s = splbio(); 315 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 316 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 317 NCR5380_WRITE(ncr_sc, sci_mode, 318 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 319 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 320 321 resid = datalen; 322 if (hcsc_ready(ncr_sc) == 0) 323 goto interrupt; 324 325 if (resid > HCSC_TSIZE_OUT) { 326 /* 327 * Because of the chips DMA prefetch, phase changes 328 * etc, won't be detected until we have written at 329 * least one byte more. We pre-write 4 bytes so 330 * subsequent transfers will be aligned to a 4 byte 331 * boundary. Assuming disconects will only occur on 332 * block boundaries, we then correct for the pre-write 333 * when and if we get a phase change. If the chip had 334 * DMA byte counting hardware, the assumption would not 335 * be necessary. 336 */ 337 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 338 data += 4; 339 resid -= 4; 340 341 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 342 if (hcsc_ready(ncr_sc) == 0) { 343 resid += 4; /* Overshot */ 344 goto interrupt; 345 } 346 bus_space_write_multi_1(pdmat, pdmah, 0, data, 347 HCSC_TSIZE_OUT); 348 data += HCSC_TSIZE_OUT; 349 } 350 if (hcsc_ready(ncr_sc) == 0) { 351 resid += 4; /* Overshot */ 352 goto interrupt; 353 } 354 } 355 356 if (resid) { 357 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 358 resid = 0; 359 } 360 for (i = TIMEOUT; i > 0; i--) { 361 if ((NCR5380_READ(ncr_sc, sci_csr) 362 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 363 != SCI_CSR_DREQ) 364 break; 365 } 366 if (i != 0) 367 bus_space_write_1(pdmat, pdmah, 0, 0); 368 else 369 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 370 ncr_sc->sc_dev.dv_xname); 371 372 hcsc_wait_not_req(ncr_sc); 373 interrupt: 374 SCI_CLR_INTR(ncr_sc); 375 NCR5380_WRITE(ncr_sc, sci_mode, 376 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 377 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 378 splx(s); 379 return(datalen - resid); 380 } 381