1 /* $NetBSD: ydsvar.h,v 1.10 2008/07/09 15:42:37 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Kazuki Sakamoto and Minoura Makoto. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _DEV_PCI_YDSVAR_H_ 29 #define _DEV_PCI_YDSVAR_H_ 30 31 #define N_PLAY_SLOTS 2 /* We use only 2 (R and L) */ 32 #define N_PLAY_SLOT_CTRL 2 33 #define WORK_SIZE 0x0400 34 35 /* 36 * softc 37 */ 38 struct yds_dma { 39 bus_dmamap_t map; 40 void *addr; /* VA */ 41 bus_dma_segment_t segs[1]; 42 int nsegs; 43 size_t size; 44 struct yds_dma *next; 45 }; 46 47 struct yds_codec_softc { 48 struct yds_softc *sc; 49 int id; 50 int status_data; 51 int status_addr; 52 struct ac97_host_if host_if; 53 struct ac97_codec_if *codec_if; 54 }; 55 56 struct yds_softc { 57 device_t sc_dev; 58 pci_chipset_tag_t sc_pc; 59 pcitag_t sc_pcitag; 60 pcireg_t sc_id; 61 int sc_revision; 62 void *sc_ih; /* interrupt vectoring */ 63 bus_space_tag_t memt; 64 bus_space_handle_t memh; 65 bus_dma_tag_t sc_dmatag; /* DMA tag */ 66 u_int sc_flags; 67 68 struct yds_codec_softc sc_codec[2]; /* Primary/Secondary AC97 */ 69 70 struct yds_dma *sc_dmas; /* List of DMA handles */ 71 72 /* 73 * Play/record status 74 */ 75 struct { 76 void (*intr)(void *); /* rint/pint */ 77 void *intr_arg; /* arg for intr */ 78 u_int offset; /* filled up to here */ 79 u_int blksize; 80 u_int factor; /* byte per sample */ 81 u_int length; /* ring buffer length */ 82 struct yds_dma *dma; /* DMA handle for ring buf */ 83 } sc_play, sc_rec; 84 85 /* 86 * DSP control data 87 * 88 * Work space, play control data table, play slot control data, 89 * rec slot control data and effect slot control data are 90 * stored in a single memory segment in this order. 91 */ 92 struct yds_dma sc_ctrldata; 93 /* KVA and offset in buffer of play ctrl data tbl */ 94 uint32_t *ptbl; 95 off_t ptbloff; 96 /* KVA and offset in buffer of rec slot ctrl data */ 97 struct rec_slot_ctrl_bank *rbank; 98 off_t rbankoff; 99 /* Array of KVA pointers and offset of play slot control data */ 100 struct play_slot_ctrl_bank *pbankp[N_PLAY_SLOT_CTRL_BANK 101 *N_PLAY_SLOTS]; 102 off_t pbankoff; 103 104 /* 105 * Legacy support 106 */ 107 bus_space_tag_t sc_legacy_iot; 108 bus_space_handle_t sc_opl_ioh; 109 device_t sc_mpu; 110 bus_space_handle_t sc_mpu_ioh; 111 112 struct audio_encoding_set *sc_encodings; 113 114 /* 115 * Power management 116 */ 117 struct pci_conf_state sc_pciconf; 118 pcireg_t sc_dsctrl; 119 pcireg_t sc_legacy; 120 pcireg_t sc_ba[2]; 121 }; 122 #define sc_opl_iot sc_legacy_iot 123 #define sc_mpu_iot sc_legacy_iot 124 125 #endif /* _DEV_PCI_YDSVAR_H_ */ 126