1 /* $NetBSD: viaide.c,v 1.77 2011/12/28 20:28:04 phx Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.77 2011/12/28 20:28:04 phx Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_apollo_reg.h> 40 41 static int via_pcib_match(const struct pci_attach_args *); 42 static void via_chip_map(struct pciide_softc *, 43 const struct pci_attach_args *); 44 static void via_mapchan(const struct pci_attach_args *, 45 struct pciide_channel *, 46 pcireg_t, int (*)(void *)); 47 static void via_mapregs_compat_native(const struct pci_attach_args *, 48 struct pciide_channel *); 49 static int via_sata_chip_map_common(struct pciide_softc *, 50 const struct pci_attach_args *); 51 static void via_sata_chip_map(struct pciide_softc *, 52 const struct pci_attach_args *, int); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 const struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 const struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 const struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(device_t, cfdata_t, void *); 62 static void viaide_attach(device_t, device_t, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 static bool viaide_suspend(device_t, const pmf_qual_t *); 66 static bool viaide_resume(device_t, const pmf_qual_t *); 67 68 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 69 viaide_match, viaide_attach, pciide_detach, NULL); 70 71 static const struct pciide_product_desc pciide_amd_products[] = { 72 { PCI_PRODUCT_AMD_PBC756_IDE, 73 0, 74 "AMD AMD756 IDE Controller", 75 via_chip_map 76 }, 77 { PCI_PRODUCT_AMD_PBC766_IDE, 78 0, 79 "AMD AMD766 IDE Controller", 80 via_chip_map 81 }, 82 { PCI_PRODUCT_AMD_PBC768_IDE, 83 0, 84 "AMD AMD768 IDE Controller", 85 via_chip_map 86 }, 87 { PCI_PRODUCT_AMD_PBC8111_IDE, 88 0, 89 "AMD AMD8111 IDE Controller", 90 via_chip_map 91 }, 92 { PCI_PRODUCT_AMD_CS5536_IDE, 93 0, 94 "AMD CS5536 IDE Controller", 95 via_chip_map 96 }, 97 { 0, 98 0, 99 NULL, 100 NULL 101 } 102 }; 103 104 static const struct pciide_product_desc pciide_nvidia_products[] = { 105 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 106 0, 107 "NVIDIA nForce IDE Controller", 108 via_chip_map 109 }, 110 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 111 0, 112 "NVIDIA nForce2 IDE Controller", 113 via_chip_map 114 }, 115 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 116 0, 117 "NVIDIA nForce2 Ultra 400 IDE Controller", 118 via_chip_map 119 }, 120 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 121 0, 122 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 123 via_sata_chip_map_6 124 }, 125 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 126 0, 127 "NVIDIA nForce3 IDE Controller", 128 via_chip_map 129 }, 130 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 131 0, 132 "NVIDIA nForce3 250 IDE Controller", 133 via_chip_map 134 }, 135 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 136 0, 137 "NVIDIA nForce3 250 Serial ATA Controller", 138 via_sata_chip_map_6 139 }, 140 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 141 0, 142 "NVIDIA nForce3 250 Serial ATA Controller", 143 via_sata_chip_map_6 144 }, 145 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 146 0, 147 "NVIDIA nForce4 IDE Controller", 148 via_chip_map 149 }, 150 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 151 0, 152 "NVIDIA nForce4 Serial ATA Controller", 153 via_sata_chip_map_6 154 }, 155 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 156 0, 157 "NVIDIA nForce4 Serial ATA Controller", 158 via_sata_chip_map_6 159 }, 160 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 161 0, 162 "NVIDIA nForce430 IDE Controller", 163 via_chip_map 164 }, 165 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 166 0, 167 "NVIDIA nForce430 Serial ATA Controller", 168 via_sata_chip_map_6 169 }, 170 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 171 0, 172 "NVIDIA nForce430 Serial ATA Controller", 173 via_sata_chip_map_6 174 }, 175 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 176 0, 177 "NVIDIA MCP04 IDE Controller", 178 via_chip_map 179 }, 180 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 181 0, 182 "NVIDIA MCP04 Serial ATA Controller", 183 via_sata_chip_map_6 184 }, 185 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 186 0, 187 "NVIDIA MCP04 Serial ATA Controller", 188 via_sata_chip_map_6 189 }, 190 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 191 0, 192 "NVIDIA MCP55 IDE Controller", 193 via_chip_map 194 }, 195 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 196 0, 197 "NVIDIA MCP55 Serial ATA Controller", 198 via_sata_chip_map_6 199 }, 200 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 201 0, 202 "NVIDIA MCP55 Serial ATA Controller", 203 via_sata_chip_map_6 204 }, 205 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 206 0, 207 "NVIDIA MCP61 IDE Controller", 208 via_chip_map 209 }, 210 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 211 0, 212 "NVIDIA MCP65 IDE Controller", 213 via_chip_map 214 }, 215 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 216 0, 217 "NVIDIA MCP73 IDE Controller", 218 via_chip_map 219 }, 220 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 221 0, 222 "NVIDIA MCP77 IDE Controller", 223 via_chip_map 224 }, 225 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 226 0, 227 "NVIDIA MCP61 Serial ATA Controller", 228 via_sata_chip_map_6 229 }, 230 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 231 0, 232 "NVIDIA MCP61 Serial ATA Controller", 233 via_sata_chip_map_6 234 }, 235 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 236 0, 237 "NVIDIA MCP61 Serial ATA Controller", 238 via_sata_chip_map_6 239 }, 240 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 241 0, 242 "NVIDIA MCP65 Serial ATA Controller", 243 via_sata_chip_map_6 244 }, 245 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 246 0, 247 "NVIDIA MCP65 Serial ATA Controller", 248 via_sata_chip_map_6 249 }, 250 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 251 0, 252 "NVIDIA MCP65 Serial ATA Controller", 253 via_sata_chip_map_6 254 }, 255 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 256 0, 257 "NVIDIA MCP65 Serial ATA Controller", 258 via_sata_chip_map_6 259 }, 260 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 261 0, 262 "NVIDIA MCP67 IDE Controller", 263 via_chip_map, 264 }, 265 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 266 0, 267 "NVIDIA MCP67 Serial ATA Controller", 268 via_sata_chip_map_6, 269 }, 270 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 271 0, 272 "NVIDIA MCP67 Serial ATA Controller", 273 via_sata_chip_map_6, 274 }, 275 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 276 0, 277 "NVIDIA MCP67 Serial ATA Controller", 278 via_sata_chip_map_6, 279 }, 280 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 281 0, 282 "NVIDIA MCP67 Serial ATA Controller", 283 via_sata_chip_map_6, 284 }, 285 { 0, 286 0, 287 NULL, 288 NULL 289 } 290 }; 291 292 static const struct pciide_product_desc pciide_via_products[] = { 293 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 294 0, 295 NULL, 296 via_chip_map, 297 }, 298 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 299 0, 300 NULL, 301 via_chip_map, 302 }, 303 { PCI_PRODUCT_VIATECH_CX700_IDE, 304 0, 305 NULL, 306 via_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 309 0, 310 NULL, 311 via_chip_map, 312 }, 313 { PCI_PRODUCT_VIATECH_VT6410_RAID, 314 0, 315 NULL, 316 via_chip_map, 317 }, 318 { PCI_PRODUCT_VIATECH_VT6421_RAID, 319 0, 320 "VIA Technologies VT6421 Serial ATA RAID Controller", 321 via_sata_chip_map_new, 322 }, 323 { PCI_PRODUCT_VIATECH_VT8237_SATA, 324 0, 325 "VIA Technologies VT8237 SATA Controller", 326 via_sata_chip_map_7, 327 }, 328 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 329 0, 330 "VIA Technologies VT8237A SATA Controller", 331 via_sata_chip_map_7, 332 }, 333 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 334 0, 335 "VIA Technologies VT8237A (5337) SATA Controller", 336 via_sata_chip_map_7, 337 }, 338 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 339 0, 340 "VIA Technologies VT8237R SATA Controller", 341 via_sata_chip_map_7, 342 }, 343 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 344 0, 345 "VIA Technologies VT8237S SATA Controller", 346 via_sata_chip_map_7, 347 }, 348 { 0, 349 0, 350 NULL, 351 NULL 352 } 353 }; 354 355 static const struct pciide_product_desc * 356 viaide_lookup(pcireg_t id) 357 { 358 359 switch (PCI_VENDOR(id)) { 360 case PCI_VENDOR_VIATECH: 361 return (pciide_lookup_product(id, pciide_via_products)); 362 363 case PCI_VENDOR_AMD: 364 return (pciide_lookup_product(id, pciide_amd_products)); 365 366 case PCI_VENDOR_NVIDIA: 367 return (pciide_lookup_product(id, pciide_nvidia_products)); 368 } 369 return (NULL); 370 } 371 372 static int 373 viaide_match(device_t parent, cfdata_t match, void *aux) 374 { 375 const struct pci_attach_args *pa = aux; 376 377 if (viaide_lookup(pa->pa_id) != NULL) 378 return (2); 379 return (0); 380 } 381 382 static void 383 viaide_attach(device_t parent, device_t self, void *aux) 384 { 385 const struct pci_attach_args *pa = aux; 386 struct pciide_softc *sc = device_private(self); 387 const struct pciide_product_desc *pp; 388 389 sc->sc_wdcdev.sc_atac.atac_dev = self; 390 391 pp = viaide_lookup(pa->pa_id); 392 if (pp == NULL) 393 panic("viaide_attach"); 394 pciide_common_attach(sc, pa, pp); 395 396 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 397 aprint_error_dev(self, "couldn't establish power handler\n"); 398 } 399 400 static int 401 via_pcib_match(const struct pci_attach_args *pa) 402 { 403 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 404 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 405 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 406 return (1); 407 return 0; 408 } 409 410 static bool 411 viaide_suspend(device_t dv, const pmf_qual_t *qual) 412 { 413 struct pciide_softc *sc = device_private(dv); 414 415 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 416 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 417 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 418 /* This two are VIA-only, but should be ignored by other devices. */ 419 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 420 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 421 422 return true; 423 } 424 425 static bool 426 viaide_resume(device_t dv, const pmf_qual_t *qual) 427 { 428 struct pciide_softc *sc = device_private(dv); 429 430 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 431 sc->sc_pm_reg[0]); 432 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 433 sc->sc_pm_reg[1]); 434 /* This two are VIA-only, but should be ignored by other devices. */ 435 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 436 sc->sc_pm_reg[2]); 437 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 438 sc->sc_pm_reg[3]); 439 440 return true; 441 } 442 443 static void 444 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 445 { 446 struct pciide_channel *cp; 447 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 448 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 449 int channel; 450 u_int32_t ideconf; 451 pcireg_t pcib_id, pcib_class; 452 struct pci_attach_args pcib_pa; 453 454 if (pciide_chipen(sc, pa) == 0) 455 return; 456 457 switch (vendor) { 458 case PCI_VENDOR_VIATECH: 459 switch (PCI_PRODUCT(pa->pa_id)) { 460 case PCI_PRODUCT_VIATECH_VT6410_RAID: 461 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 462 "VIA Technologies VT6410 IDE controller\n"); 463 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 464 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 465 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 466 break; 467 default: 468 /* 469 * get a PCI tag for the ISA bridge. 470 */ 471 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 472 goto unknown; 473 pcib_id = pcib_pa.pa_id; 474 pcib_class = pcib_pa.pa_class; 475 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 476 "VIA Technologies "); 477 switch (PCI_PRODUCT(pcib_id)) { 478 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 479 aprint_normal("VT82C586 (Apollo VP) "); 480 if(PCI_REVISION(pcib_class) >= 0x02) { 481 aprint_normal("ATA33 controller\n"); 482 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 483 } else { 484 aprint_normal("controller\n"); 485 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 486 } 487 break; 488 case PCI_PRODUCT_VIATECH_VT82C596A: 489 aprint_normal("VT82C596A (Apollo Pro) "); 490 if (PCI_REVISION(pcib_class) >= 0x12) { 491 aprint_normal("ATA66 controller\n"); 492 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 493 } else { 494 aprint_normal("ATA33 controller\n"); 495 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 496 } 497 break; 498 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 499 aprint_normal("VT82C686A (Apollo KX133) "); 500 if (PCI_REVISION(pcib_class) >= 0x40) { 501 aprint_normal("ATA100 controller\n"); 502 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 503 } else { 504 aprint_normal("ATA66 controller\n"); 505 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 506 } 507 break; 508 case PCI_PRODUCT_VIATECH_VT8231: 509 aprint_normal("VT8231 ATA100 controller\n"); 510 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 511 break; 512 case PCI_PRODUCT_VIATECH_VT8233: 513 aprint_normal("VT8233 ATA100 controller\n"); 514 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 515 break; 516 case PCI_PRODUCT_VIATECH_VT8233A: 517 aprint_normal("VT8233A ATA133 controller\n"); 518 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 519 break; 520 case PCI_PRODUCT_VIATECH_VT8235: 521 aprint_normal("VT8235 ATA133 controller\n"); 522 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 523 break; 524 case PCI_PRODUCT_VIATECH_VT8237: 525 aprint_normal("VT8237 ATA133 controller\n"); 526 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 527 break; 528 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 529 aprint_normal("VT8237A ATA133 controller\n"); 530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 531 break; 532 case PCI_PRODUCT_VIATECH_CX700: 533 aprint_normal("CX700 ATA133 controller\n"); 534 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 535 break; 536 case PCI_PRODUCT_VIATECH_VT8251: 537 aprint_normal("VT8251 ATA133 controller\n"); 538 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 539 break; 540 default: 541 unknown: 542 aprint_normal("unknown VIA ATA controller\n"); 543 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 544 } 545 break; 546 } 547 sc->sc_apo_regbase = APO_VIA_REGBASE; 548 break; 549 case PCI_VENDOR_AMD: 550 switch (sc->sc_pp->ide_product) { 551 case PCI_PRODUCT_AMD_PBC8111_IDE: 552 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 553 break; 554 case PCI_PRODUCT_AMD_CS5536_IDE: 555 case PCI_PRODUCT_AMD_PBC766_IDE: 556 case PCI_PRODUCT_AMD_PBC768_IDE: 557 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 558 break; 559 default: 560 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 561 } 562 sc->sc_apo_regbase = APO_AMD_REGBASE; 563 break; 564 case PCI_VENDOR_NVIDIA: 565 switch (sc->sc_pp->ide_product) { 566 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 567 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 568 break; 569 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 570 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 571 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 572 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 573 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 574 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 575 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 576 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 577 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 578 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 579 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 580 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 581 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 582 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 583 break; 584 } 585 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 586 break; 587 default: 588 panic("via_chip_map: unknown vendor"); 589 } 590 591 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 592 "bus-master DMA support present"); 593 pciide_mapreg_dma(sc, pa); 594 aprint_verbose("\n"); 595 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 596 if (sc->sc_dma_ok) { 597 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 598 sc->sc_wdcdev.irqack = pciide_irqack; 599 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 600 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 601 } 602 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 603 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 604 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 605 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 606 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 607 608 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 609 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 610 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 611 612 wdc_allocate_regs(&sc->sc_wdcdev); 613 614 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 615 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 616 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 617 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 618 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 619 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 620 DEBUG_PROBE); 621 622 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 623 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 624 channel++) { 625 cp = &sc->pciide_channels[channel]; 626 if (pciide_chansetup(sc, channel, interface) == 0) 627 continue; 628 629 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 630 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 631 "%s channel ignored (disabled)\n", cp->name); 632 cp->ata_channel.ch_flags |= ATACH_DISABLED; 633 continue; 634 } 635 via_mapchan(pa, cp, interface, pciide_pci_intr); 636 } 637 } 638 639 static void 640 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 641 pcireg_t interface, int (*pci_intr)(void *)) 642 { 643 struct ata_channel *wdc_cp; 644 struct pciide_softc *sc; 645 prop_bool_t compat_nat_enable; 646 647 wdc_cp = &cp->ata_channel; 648 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 649 compat_nat_enable = prop_dictionary_get( 650 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 651 "use-compat-native-irq"); 652 653 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 654 /* native mode with irq 14/15 requested? */ 655 if (compat_nat_enable != NULL && 656 prop_bool_true(compat_nat_enable)) 657 via_mapregs_compat_native(pa, cp); 658 else 659 pciide_mapregs_native(pa, cp, pci_intr); 660 } else { 661 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 662 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 663 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 664 } 665 wdcattach(wdc_cp); 666 } 667 668 /* 669 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 670 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 671 * programmed to use a single native PCI irq alone. So we install an interrupt 672 * handler for each channel, as in compatibility mode. 673 */ 674 static void 675 via_mapregs_compat_native(const struct pci_attach_args *pa, 676 struct pciide_channel *cp) 677 { 678 struct ata_channel *wdc_cp; 679 struct pciide_softc *sc; 680 681 wdc_cp = &cp->ata_channel; 682 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 683 684 /* XXX prevent pciide_mapregs_native from installing a handler */ 685 if (sc->sc_pci_ih == NULL) 686 sc->sc_pci_ih = (void *)~0; 687 pciide_mapregs_native(pa, cp, NULL); 688 689 /* interrupts are fixed to 14/15, as in compatibility mode */ 690 cp->compat = 1; 691 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 692 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 693 cp->ih = pciide_machdep_compat_intr_establish( 694 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 695 pciide_compat_intr, cp); 696 if (cp->ih == NULL) { 697 #endif 698 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 699 "no compatibility interrupt for " 700 "use by %s channel\n", cp->name); 701 wdc_cp->ch_flags |= ATACH_DISABLED; 702 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 703 } 704 sc->sc_pci_ih = cp->ih; /* XXX */ 705 #endif 706 } 707 } 708 709 static void 710 via_setup_channel(struct ata_channel *chp) 711 { 712 u_int32_t udmatim_reg, datatim_reg; 713 u_int8_t idedma_ctl; 714 int mode, drive, s; 715 struct ata_drive_datas *drvp; 716 struct atac_softc *atac = chp->ch_atac; 717 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 718 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 719 #ifndef PCIIDE_AMD756_ENABLEDMA 720 int rev = PCI_REVISION( 721 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 722 #endif 723 724 idedma_ctl = 0; 725 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 726 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 727 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 728 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 729 730 /* setup DMA if needed */ 731 pciide_channel_dma_setup(cp); 732 733 for (drive = 0; drive < 2; drive++) { 734 drvp = &chp->ch_drive[drive]; 735 /* If no drive, skip */ 736 if ((drvp->drive_flags & DRIVE) == 0) 737 continue; 738 /* add timing values, setup DMA if needed */ 739 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 740 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 741 mode = drvp->PIO_mode; 742 goto pio; 743 } 744 if ((atac->atac_cap & ATAC_CAP_UDMA) && 745 (drvp->drive_flags & DRIVE_UDMA)) { 746 /* use Ultra/DMA */ 747 s = splbio(); 748 drvp->drive_flags &= ~DRIVE_DMA; 749 splx(s); 750 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 751 APO_UDMA_EN_MTH(chp->ch_channel, drive); 752 switch (PCI_VENDOR(sc->sc_pci_id)) { 753 case PCI_VENDOR_VIATECH: 754 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 755 /* 8233a */ 756 udmatim_reg |= APO_UDMA_TIME( 757 chp->ch_channel, 758 drive, 759 via_udma133_tim[drvp->UDMA_mode]); 760 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 761 /* 686b */ 762 udmatim_reg |= APO_UDMA_TIME( 763 chp->ch_channel, 764 drive, 765 via_udma100_tim[drvp->UDMA_mode]); 766 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 767 /* 596b or 686a */ 768 udmatim_reg |= APO_UDMA_CLK66( 769 chp->ch_channel); 770 udmatim_reg |= APO_UDMA_TIME( 771 chp->ch_channel, 772 drive, 773 via_udma66_tim[drvp->UDMA_mode]); 774 } else { 775 /* 596a or 586b */ 776 udmatim_reg |= APO_UDMA_TIME( 777 chp->ch_channel, 778 drive, 779 via_udma33_tim[drvp->UDMA_mode]); 780 } 781 break; 782 case PCI_VENDOR_AMD: 783 case PCI_VENDOR_NVIDIA: 784 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 785 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 786 break; 787 } 788 /* can use PIO timings, MW DMA unused */ 789 mode = drvp->PIO_mode; 790 } else { 791 /* use Multiword DMA, but only if revision is OK */ 792 s = splbio(); 793 drvp->drive_flags &= ~DRIVE_UDMA; 794 splx(s); 795 #ifndef PCIIDE_AMD756_ENABLEDMA 796 /* 797 * The workaround doesn't seem to be necessary 798 * with all drives, so it can be disabled by 799 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 800 * triggered. 801 */ 802 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 803 sc->sc_pp->ide_product == 804 PCI_PRODUCT_AMD_PBC756_IDE && 805 AMD756_CHIPREV_DISABLEDMA(rev)) { 806 aprint_normal( 807 "%s:%d:%d: multi-word DMA disabled due " 808 "to chip revision\n", 809 device_xname( 810 sc->sc_wdcdev.sc_atac.atac_dev), 811 chp->ch_channel, drive); 812 mode = drvp->PIO_mode; 813 s = splbio(); 814 drvp->drive_flags &= ~DRIVE_DMA; 815 splx(s); 816 goto pio; 817 } 818 #endif 819 /* mode = min(pio, dma+2) */ 820 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 821 mode = drvp->PIO_mode; 822 else 823 mode = drvp->DMA_mode + 2; 824 } 825 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 826 827 pio: /* setup PIO mode */ 828 if (mode <= 2) { 829 drvp->DMA_mode = 0; 830 drvp->PIO_mode = 0; 831 mode = 0; 832 } else { 833 drvp->PIO_mode = mode; 834 drvp->DMA_mode = mode - 2; 835 } 836 datatim_reg |= 837 APO_DATATIM_PULSE(chp->ch_channel, drive, 838 apollo_pio_set[mode]) | 839 APO_DATATIM_RECOV(chp->ch_channel, drive, 840 apollo_pio_rec[mode]); 841 } 842 if (idedma_ctl != 0) { 843 /* Add software bits in status register */ 844 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 845 idedma_ctl); 846 } 847 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 848 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 849 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 850 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 851 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 852 } 853 854 static int 855 via_sata_chip_map_common(struct pciide_softc *sc, 856 const struct pci_attach_args *cpa) 857 { 858 pcireg_t csr; 859 int maptype, ret; 860 struct pci_attach_args pac, *pa = &pac; 861 862 pac = *cpa; 863 864 if (pciide_chipen(sc, pa) == 0) 865 return 0; 866 867 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 868 "bus-master DMA support present"); 869 pciide_mapreg_dma(sc, pa); 870 aprint_verbose("\n"); 871 872 if (sc->sc_dma_ok) { 873 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 874 sc->sc_wdcdev.irqack = pciide_irqack; 875 } 876 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 877 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 878 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 879 880 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 881 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 882 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 883 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 884 885 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 886 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 887 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 888 889 wdc_allocate_regs(&sc->sc_wdcdev); 890 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 891 PCI_MAPREG_START + 0x14); 892 switch(maptype) { 893 case PCI_MAPREG_TYPE_IO: 894 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 895 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 896 NULL, &sc->sc_ba5_ss); 897 break; 898 case PCI_MAPREG_MEM_TYPE_32BIT: 899 /* 900 * Enable memory-space access if it isn't already there. 901 */ 902 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 903 PCI_COMMAND_STATUS_REG); 904 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 905 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 906 907 pci_conf_write(pa->pa_pc, pa->pa_tag, 908 PCI_COMMAND_STATUS_REG, 909 csr | PCI_COMMAND_MEM_ENABLE); 910 } 911 912 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 913 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 914 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 915 NULL, &sc->sc_ba5_ss); 916 break; 917 default: 918 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 919 "couldn't map sata regs, unsupported maptype (0x%x)\n", 920 maptype); 921 return 0; 922 } 923 if (ret != 0) { 924 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 925 "couldn't map sata regs\n"); 926 return 0; 927 } 928 return 1; 929 } 930 931 static void 932 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 933 int satareg_shift) 934 { 935 struct pciide_channel *cp; 936 struct ata_channel *wdc_cp; 937 struct wdc_regs *wdr; 938 pcireg_t interface; 939 int channel; 940 941 interface = PCI_INTERFACE(pa->pa_class); 942 943 if (via_sata_chip_map_common(sc, pa) == 0) 944 return; 945 946 if (interface == 0) { 947 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 948 DEBUG_PROBE); 949 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 950 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 951 } 952 953 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 954 channel++) { 955 cp = &sc->pciide_channels[channel]; 956 if (pciide_chansetup(sc, channel, interface) == 0) 957 continue; 958 wdc_cp = &cp->ata_channel; 959 wdr = CHAN_TO_WDC_REGS(wdc_cp); 960 wdr->sata_iot = sc->sc_ba5_st; 961 wdr->sata_baseioh = sc->sc_ba5_sh; 962 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 963 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 964 &wdr->sata_status) != 0) { 965 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 966 "couldn't map channel %d sata_status regs\n", 967 wdc_cp->ch_channel); 968 continue; 969 } 970 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 971 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 972 &wdr->sata_error) != 0) { 973 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 974 "couldn't map channel %d sata_error regs\n", 975 wdc_cp->ch_channel); 976 continue; 977 } 978 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 979 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 980 &wdr->sata_control) != 0) { 981 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 982 "couldn't map channel %d sata_control regs\n", 983 wdc_cp->ch_channel); 984 continue; 985 } 986 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 987 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 988 } 989 } 990 991 static void 992 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 993 { 994 via_sata_chip_map(sc, pa, 6); 995 } 996 997 static void 998 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 999 { 1000 via_sata_chip_map(sc, pa, 7); 1001 } 1002 1003 static void 1004 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1005 { 1006 struct pciide_channel *pc; 1007 int chan, reg; 1008 bus_size_t size; 1009 1010 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1011 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1012 NULL, &sc->sc_dma_ios) == 0); 1013 sc->sc_dmat = pa->pa_dmat; 1014 if (sc->sc_dma_ok == 0) { 1015 aprint_verbose(", but unused (couldn't map registers)"); 1016 } else { 1017 sc->sc_wdcdev.dma_arg = sc; 1018 sc->sc_wdcdev.dma_init = pciide_dma_init; 1019 sc->sc_wdcdev.dma_start = pciide_dma_start; 1020 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1021 } 1022 1023 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1024 PCIIDE_OPTIONS_NODMA) { 1025 aprint_verbose( 1026 ", but unused (forced off by config file)"); 1027 sc->sc_dma_ok = 0; 1028 } 1029 1030 if (sc->sc_dma_ok == 0) 1031 return; 1032 1033 for (chan = 0; chan < 4; chan++) { 1034 pc = &sc->pciide_channels[chan]; 1035 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1036 size = 4; 1037 if (size > (IDEDMA_SCH_OFFSET - reg)) 1038 size = IDEDMA_SCH_OFFSET - reg; 1039 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1040 IDEDMA_SCH_OFFSET * chan + reg, size, 1041 &pc->dma_iohs[reg]) != 0) { 1042 sc->sc_dma_ok = 0; 1043 aprint_verbose(", but can't subregion offset " 1044 "%d size %lu", 1045 reg, (u_long)size); 1046 return; 1047 } 1048 } 1049 } 1050 } 1051 1052 static int 1053 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1054 { 1055 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1056 1057 sc->wdc_chanarray[channel] = &cp->ata_channel; 1058 1059 cp->ata_channel.ch_channel = channel; 1060 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1061 cp->ata_channel.ch_queue = 1062 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 1063 cp->ata_channel.ch_ndrive = 2; 1064 if (cp->ata_channel.ch_queue == NULL) { 1065 aprint_error("%s channel %d: " 1066 "can't allocate memory for command queue", 1067 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel); 1068 return 0; 1069 } 1070 return 1; 1071 } 1072 1073 static void 1074 via_sata_chip_map_new(struct pciide_softc *sc, 1075 const struct pci_attach_args *pa) 1076 { 1077 struct pciide_channel *cp; 1078 struct ata_channel *wdc_cp; 1079 struct wdc_regs *wdr; 1080 int channel; 1081 pci_intr_handle_t intrhandle; 1082 const char *intrstr; 1083 int i; 1084 1085 if (pciide_chipen(sc, pa) == 0) 1086 return; 1087 1088 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1089 1090 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1091 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1092 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1093 "couldn't map SATA regs\n"); 1094 } 1095 1096 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1097 "bus-master DMA support present"); 1098 via_vt6421_mapreg_dma(sc, pa); 1099 aprint_verbose("\n"); 1100 1101 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1102 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1103 if (sc->sc_dma_ok) { 1104 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1105 sc->sc_wdcdev.irqack = pciide_irqack; 1106 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1107 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1108 } 1109 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1110 1111 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1112 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1113 1114 wdc_allocate_regs(&sc->sc_wdcdev); 1115 1116 if (pci_intr_map(pa, &intrhandle) != 0) { 1117 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1118 "couldn't map native-PCI interrupt\n"); 1119 return; 1120 } 1121 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1122 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1123 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1124 if (sc->sc_pci_ih == NULL) { 1125 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1126 "couldn't establish native-PCI interrupt"); 1127 if (intrstr != NULL) 1128 aprint_error(" at %s", intrstr); 1129 aprint_error("\n"); 1130 return; 1131 } 1132 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1133 "using %s for native-PCI interrupt\n", 1134 intrstr ? intrstr : "unknown interrupt"); 1135 1136 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1137 channel++) { 1138 cp = &sc->pciide_channels[channel]; 1139 if (via_vt6421_chansetup(sc, channel) == 0) 1140 continue; 1141 cp->ata_channel.ch_ndrive = 2; 1142 wdc_cp = &cp->ata_channel; 1143 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1144 1145 wdr->sata_iot = sc->sc_ba5_st; 1146 wdr->sata_baseioh = sc->sc_ba5_sh; 1147 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1148 (wdc_cp->ch_channel << 6) + 0x0, 4, 1149 &wdr->sata_status) != 0) { 1150 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1151 "couldn't map channel %d sata_status regs\n", 1152 wdc_cp->ch_channel); 1153 continue; 1154 } 1155 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1156 (wdc_cp->ch_channel << 6) + 0x4, 4, 1157 &wdr->sata_error) != 0) { 1158 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1159 "couldn't map channel %d sata_error regs\n", 1160 wdc_cp->ch_channel); 1161 continue; 1162 } 1163 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1164 (wdc_cp->ch_channel << 6) + 0x8, 4, 1165 &wdr->sata_control) != 0) { 1166 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1167 "couldn't map channel %d sata_control regs\n", 1168 wdc_cp->ch_channel); 1169 continue; 1170 } 1171 1172 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1173 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1174 NULL, &wdr->cmd_ios) != 0) { 1175 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1176 "couldn't map %s channel regs\n", cp->name); 1177 } 1178 wdr->ctl_iot = wdr->cmd_iot; 1179 for (i = 0; i < WDC_NREG; i++) { 1180 if (bus_space_subregion(wdr->cmd_iot, 1181 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1182 &wdr->cmd_iohs[i]) != 0) { 1183 aprint_error_dev( 1184 sc->sc_wdcdev.sc_atac.atac_dev, 1185 "couldn't subregion %s " 1186 "channel cmd regs\n", cp->name); 1187 return; 1188 } 1189 } 1190 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1191 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1192 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1193 "couldn't map channel %d ctl regs\n", channel); 1194 return; 1195 } 1196 wdc_init_shadow_regs(wdc_cp); 1197 wdr->data32iot = wdr->cmd_iot; 1198 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1199 wdcattach(wdc_cp); 1200 } 1201 } 1202