1 /* $NetBSD: viaide.c,v 1.75 2011/05/17 17:34:54 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.75 2011/05/17 17:34:54 dyoung Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 NULL, 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VT6421_RAID, 313 0, 314 "VIA Technologies VT6421 Serial RAID Controller", 315 via_sata_chip_map_new, 316 }, 317 { PCI_PRODUCT_VIATECH_VT8237_SATA, 318 0, 319 "VIA Technologies VT8237 SATA Controller", 320 via_sata_chip_map_7, 321 }, 322 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 323 0, 324 "VIA Technologies VT8237A SATA Controller", 325 via_sata_chip_map_7, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 328 0, 329 "VIA Technologies VT8237A (5337) SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 333 0, 334 "VIA Technologies VT8237R SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 338 0, 339 "VIA Technologies VT8237S SATA Controller", 340 via_sata_chip_map_7, 341 }, 342 { 0, 343 0, 344 NULL, 345 NULL 346 } 347 }; 348 349 static const struct pciide_product_desc * 350 viaide_lookup(pcireg_t id) 351 { 352 353 switch (PCI_VENDOR(id)) { 354 case PCI_VENDOR_VIATECH: 355 return (pciide_lookup_product(id, pciide_via_products)); 356 357 case PCI_VENDOR_AMD: 358 return (pciide_lookup_product(id, pciide_amd_products)); 359 360 case PCI_VENDOR_NVIDIA: 361 return (pciide_lookup_product(id, pciide_nvidia_products)); 362 } 363 return (NULL); 364 } 365 366 static int 367 viaide_match(device_t parent, cfdata_t match, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 371 if (viaide_lookup(pa->pa_id) != NULL) 372 return (2); 373 return (0); 374 } 375 376 static void 377 viaide_attach(device_t parent, device_t self, void *aux) 378 { 379 struct pci_attach_args *pa = aux; 380 struct pciide_softc *sc = device_private(self); 381 const struct pciide_product_desc *pp; 382 383 sc->sc_wdcdev.sc_atac.atac_dev = self; 384 385 pp = viaide_lookup(pa->pa_id); 386 if (pp == NULL) 387 panic("viaide_attach"); 388 pciide_common_attach(sc, pa, pp); 389 390 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 391 aprint_error_dev(self, "couldn't establish power handler\n"); 392 } 393 394 static int 395 via_pcib_match(const struct pci_attach_args *pa) 396 { 397 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 398 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 399 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 400 return (1); 401 return 0; 402 } 403 404 static bool 405 viaide_suspend(device_t dv, const pmf_qual_t *qual) 406 { 407 struct pciide_softc *sc = device_private(dv); 408 409 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 410 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 411 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 412 /* This two are VIA-only, but should be ignored by other devices. */ 413 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 414 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 415 416 return true; 417 } 418 419 static bool 420 viaide_resume(device_t dv, const pmf_qual_t *qual) 421 { 422 struct pciide_softc *sc = device_private(dv); 423 424 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 425 sc->sc_pm_reg[0]); 426 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 427 sc->sc_pm_reg[1]); 428 /* This two are VIA-only, but should be ignored by other devices. */ 429 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 430 sc->sc_pm_reg[2]); 431 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 432 sc->sc_pm_reg[3]); 433 434 return true; 435 } 436 437 static void 438 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 439 { 440 struct pciide_channel *cp; 441 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 442 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 443 int channel; 444 u_int32_t ideconf; 445 pcireg_t pcib_id, pcib_class; 446 struct pci_attach_args pcib_pa; 447 448 if (pciide_chipen(sc, pa) == 0) 449 return; 450 451 switch (vendor) { 452 case PCI_VENDOR_VIATECH: 453 /* 454 * get a PCI tag for the ISA bridge. 455 */ 456 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 457 goto unknown; 458 pcib_id = pcib_pa.pa_id; 459 pcib_class = pcib_pa.pa_class; 460 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 461 "VIA Technologies "); 462 switch (PCI_PRODUCT(pcib_id)) { 463 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 464 aprint_normal("VT82C586 (Apollo VP) "); 465 if(PCI_REVISION(pcib_class) >= 0x02) { 466 aprint_normal("ATA33 controller\n"); 467 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 468 } else { 469 aprint_normal("controller\n"); 470 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 471 } 472 break; 473 case PCI_PRODUCT_VIATECH_VT82C596A: 474 aprint_normal("VT82C596A (Apollo Pro) "); 475 if (PCI_REVISION(pcib_class) >= 0x12) { 476 aprint_normal("ATA66 controller\n"); 477 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 478 } else { 479 aprint_normal("ATA33 controller\n"); 480 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 481 } 482 break; 483 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 484 aprint_normal("VT82C686A (Apollo KX133) "); 485 if (PCI_REVISION(pcib_class) >= 0x40) { 486 aprint_normal("ATA100 controller\n"); 487 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 488 } else { 489 aprint_normal("ATA66 controller\n"); 490 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 491 } 492 break; 493 case PCI_PRODUCT_VIATECH_VT8231: 494 aprint_normal("VT8231 ATA100 controller\n"); 495 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 496 break; 497 case PCI_PRODUCT_VIATECH_VT8233: 498 aprint_normal("VT8233 ATA100 controller\n"); 499 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 500 break; 501 case PCI_PRODUCT_VIATECH_VT8233A: 502 aprint_normal("VT8233A ATA133 controller\n"); 503 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 504 break; 505 case PCI_PRODUCT_VIATECH_VT8235: 506 aprint_normal("VT8235 ATA133 controller\n"); 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 508 break; 509 case PCI_PRODUCT_VIATECH_VT8237: 510 aprint_normal("VT8237 ATA133 controller\n"); 511 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 512 break; 513 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 514 aprint_normal("VT8237A ATA133 controller\n"); 515 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 516 break; 517 case PCI_PRODUCT_VIATECH_CX700: 518 aprint_normal("CX700 ATA133 controller\n"); 519 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 520 break; 521 case PCI_PRODUCT_VIATECH_VT8251: 522 aprint_normal("VT8251 ATA133 controller\n"); 523 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 524 break; 525 default: 526 unknown: 527 aprint_normal("unknown VIA ATA controller\n"); 528 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 529 } 530 sc->sc_apo_regbase = APO_VIA_REGBASE; 531 break; 532 case PCI_VENDOR_AMD: 533 switch (sc->sc_pp->ide_product) { 534 case PCI_PRODUCT_AMD_PBC8111_IDE: 535 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 536 break; 537 case PCI_PRODUCT_AMD_CS5536_IDE: 538 case PCI_PRODUCT_AMD_PBC766_IDE: 539 case PCI_PRODUCT_AMD_PBC768_IDE: 540 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 541 break; 542 default: 543 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 544 } 545 sc->sc_apo_regbase = APO_AMD_REGBASE; 546 break; 547 case PCI_VENDOR_NVIDIA: 548 switch (sc->sc_pp->ide_product) { 549 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 550 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 551 break; 552 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 553 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 554 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 555 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 556 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 557 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 558 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 559 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 560 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 561 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 562 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 563 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 564 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 566 break; 567 } 568 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 569 break; 570 default: 571 panic("via_chip_map: unknown vendor"); 572 } 573 574 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 575 "bus-master DMA support present"); 576 pciide_mapreg_dma(sc, pa); 577 aprint_verbose("\n"); 578 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 579 if (sc->sc_dma_ok) { 580 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 581 sc->sc_wdcdev.irqack = pciide_irqack; 582 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 583 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 584 } 585 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 586 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 587 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 588 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 589 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 590 591 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 592 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 593 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 594 595 wdc_allocate_regs(&sc->sc_wdcdev); 596 597 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 598 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 599 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 600 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 601 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 602 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 603 DEBUG_PROBE); 604 605 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 606 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 607 channel++) { 608 cp = &sc->pciide_channels[channel]; 609 if (pciide_chansetup(sc, channel, interface) == 0) 610 continue; 611 612 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 613 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 614 "%s channel ignored (disabled)\n", cp->name); 615 cp->ata_channel.ch_flags |= ATACH_DISABLED; 616 continue; 617 } 618 via_mapchan(pa, cp, interface, pciide_pci_intr); 619 } 620 } 621 622 static void 623 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 624 pcireg_t interface, int (*pci_intr)(void *)) 625 { 626 struct ata_channel *wdc_cp; 627 struct pciide_softc *sc; 628 prop_bool_t compat_nat_enable; 629 630 wdc_cp = &cp->ata_channel; 631 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 632 compat_nat_enable = prop_dictionary_get( 633 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 634 "use-compat-native-irq"); 635 636 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 637 /* native mode with irq 14/15 requested? */ 638 if (compat_nat_enable != NULL && 639 prop_bool_true(compat_nat_enable)) 640 via_mapregs_compat_native(pa, cp); 641 else 642 pciide_mapregs_native(pa, cp, pci_intr); 643 } else { 644 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 645 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 646 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 647 } 648 wdcattach(wdc_cp); 649 } 650 651 /* 652 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 653 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 654 * programmed to use a single native PCI irq alone. So we install an interrupt 655 * handler for each channel, as in compatibility mode. 656 */ 657 static void 658 via_mapregs_compat_native(const struct pci_attach_args *pa, 659 struct pciide_channel *cp) 660 { 661 struct ata_channel *wdc_cp; 662 struct pciide_softc *sc; 663 664 wdc_cp = &cp->ata_channel; 665 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 666 667 /* XXX prevent pciide_mapregs_native from installing a handler */ 668 if (sc->sc_pci_ih == NULL) 669 sc->sc_pci_ih = (void *)~0; 670 pciide_mapregs_native(pa, cp, NULL); 671 672 /* interrupts are fixed to 14/15, as in compatibility mode */ 673 cp->compat = 1; 674 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 675 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 676 cp->ih = pciide_machdep_compat_intr_establish( 677 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 678 pciide_compat_intr, cp); 679 if (cp->ih == NULL) { 680 #endif 681 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 682 "no compatibility interrupt for " 683 "use by %s channel\n", cp->name); 684 wdc_cp->ch_flags |= ATACH_DISABLED; 685 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 686 } 687 sc->sc_pci_ih = cp->ih; /* XXX */ 688 #endif 689 } 690 } 691 692 static void 693 via_setup_channel(struct ata_channel *chp) 694 { 695 u_int32_t udmatim_reg, datatim_reg; 696 u_int8_t idedma_ctl; 697 int mode, drive, s; 698 struct ata_drive_datas *drvp; 699 struct atac_softc *atac = chp->ch_atac; 700 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 701 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 702 #ifndef PCIIDE_AMD756_ENABLEDMA 703 int rev = PCI_REVISION( 704 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 705 #endif 706 707 idedma_ctl = 0; 708 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 709 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 710 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 711 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 712 713 /* setup DMA if needed */ 714 pciide_channel_dma_setup(cp); 715 716 for (drive = 0; drive < 2; drive++) { 717 drvp = &chp->ch_drive[drive]; 718 /* If no drive, skip */ 719 if ((drvp->drive_flags & DRIVE) == 0) 720 continue; 721 /* add timing values, setup DMA if needed */ 722 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 723 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 724 mode = drvp->PIO_mode; 725 goto pio; 726 } 727 if ((atac->atac_cap & ATAC_CAP_UDMA) && 728 (drvp->drive_flags & DRIVE_UDMA)) { 729 /* use Ultra/DMA */ 730 s = splbio(); 731 drvp->drive_flags &= ~DRIVE_DMA; 732 splx(s); 733 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 734 APO_UDMA_EN_MTH(chp->ch_channel, drive); 735 switch (PCI_VENDOR(sc->sc_pci_id)) { 736 case PCI_VENDOR_VIATECH: 737 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 738 /* 8233a */ 739 udmatim_reg |= APO_UDMA_TIME( 740 chp->ch_channel, 741 drive, 742 via_udma133_tim[drvp->UDMA_mode]); 743 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 744 /* 686b */ 745 udmatim_reg |= APO_UDMA_TIME( 746 chp->ch_channel, 747 drive, 748 via_udma100_tim[drvp->UDMA_mode]); 749 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 750 /* 596b or 686a */ 751 udmatim_reg |= APO_UDMA_CLK66( 752 chp->ch_channel); 753 udmatim_reg |= APO_UDMA_TIME( 754 chp->ch_channel, 755 drive, 756 via_udma66_tim[drvp->UDMA_mode]); 757 } else { 758 /* 596a or 586b */ 759 udmatim_reg |= APO_UDMA_TIME( 760 chp->ch_channel, 761 drive, 762 via_udma33_tim[drvp->UDMA_mode]); 763 } 764 break; 765 case PCI_VENDOR_AMD: 766 case PCI_VENDOR_NVIDIA: 767 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 768 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 769 break; 770 } 771 /* can use PIO timings, MW DMA unused */ 772 mode = drvp->PIO_mode; 773 } else { 774 /* use Multiword DMA, but only if revision is OK */ 775 s = splbio(); 776 drvp->drive_flags &= ~DRIVE_UDMA; 777 splx(s); 778 #ifndef PCIIDE_AMD756_ENABLEDMA 779 /* 780 * The workaround doesn't seem to be necessary 781 * with all drives, so it can be disabled by 782 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 783 * triggered. 784 */ 785 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 786 sc->sc_pp->ide_product == 787 PCI_PRODUCT_AMD_PBC756_IDE && 788 AMD756_CHIPREV_DISABLEDMA(rev)) { 789 aprint_normal( 790 "%s:%d:%d: multi-word DMA disabled due " 791 "to chip revision\n", 792 device_xname( 793 sc->sc_wdcdev.sc_atac.atac_dev), 794 chp->ch_channel, drive); 795 mode = drvp->PIO_mode; 796 s = splbio(); 797 drvp->drive_flags &= ~DRIVE_DMA; 798 splx(s); 799 goto pio; 800 } 801 #endif 802 /* mode = min(pio, dma+2) */ 803 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 804 mode = drvp->PIO_mode; 805 else 806 mode = drvp->DMA_mode + 2; 807 } 808 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 809 810 pio: /* setup PIO mode */ 811 if (mode <= 2) { 812 drvp->DMA_mode = 0; 813 drvp->PIO_mode = 0; 814 mode = 0; 815 } else { 816 drvp->PIO_mode = mode; 817 drvp->DMA_mode = mode - 2; 818 } 819 datatim_reg |= 820 APO_DATATIM_PULSE(chp->ch_channel, drive, 821 apollo_pio_set[mode]) | 822 APO_DATATIM_RECOV(chp->ch_channel, drive, 823 apollo_pio_rec[mode]); 824 } 825 if (idedma_ctl != 0) { 826 /* Add software bits in status register */ 827 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 828 idedma_ctl); 829 } 830 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 831 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 832 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 833 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 834 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 835 } 836 837 static int 838 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 839 { 840 pcireg_t csr; 841 int maptype, ret; 842 843 if (pciide_chipen(sc, pa) == 0) 844 return 0; 845 846 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 847 "bus-master DMA support present"); 848 pciide_mapreg_dma(sc, pa); 849 aprint_verbose("\n"); 850 851 if (sc->sc_dma_ok) { 852 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 853 sc->sc_wdcdev.irqack = pciide_irqack; 854 } 855 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 856 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 857 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 858 859 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 860 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 861 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 862 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 863 864 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 865 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 866 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 867 868 wdc_allocate_regs(&sc->sc_wdcdev); 869 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 870 PCI_MAPREG_START + 0x14); 871 switch(maptype) { 872 case PCI_MAPREG_TYPE_IO: 873 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 874 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 875 NULL, &sc->sc_ba5_ss); 876 break; 877 case PCI_MAPREG_MEM_TYPE_32BIT: 878 /* 879 * Enable memory-space access if it isn't already there. 880 */ 881 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 882 PCI_COMMAND_STATUS_REG); 883 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 884 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 885 886 pci_conf_write(pa->pa_pc, pa->pa_tag, 887 PCI_COMMAND_STATUS_REG, 888 csr | PCI_COMMAND_MEM_ENABLE); 889 } 890 891 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 892 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 893 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 894 NULL, &sc->sc_ba5_ss); 895 break; 896 default: 897 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 898 "couldn't map sata regs, unsupported maptype (0x%x)\n", 899 maptype); 900 return 0; 901 } 902 if (ret != 0) { 903 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 904 "couldn't map sata regs\n"); 905 return 0; 906 } 907 return 1; 908 } 909 910 static void 911 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa0, 912 int satareg_shift) 913 { 914 struct pciide_channel *cp; 915 struct ata_channel *wdc_cp; 916 struct wdc_regs *wdr; 917 struct pci_attach_args pacopy, *pa; 918 pcireg_t interface; 919 int channel; 920 921 pacopy = *pa0; 922 pa = &pacopy; 923 interface = PCI_INTERFACE(pa->pa_class); 924 925 if (via_sata_chip_map_common(sc, pa) == 0) 926 return; 927 928 if (interface == 0) { 929 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 930 DEBUG_PROBE); 931 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 932 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 933 } 934 935 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 936 channel++) { 937 cp = &sc->pciide_channels[channel]; 938 if (pciide_chansetup(sc, channel, interface) == 0) 939 continue; 940 wdc_cp = &cp->ata_channel; 941 wdr = CHAN_TO_WDC_REGS(wdc_cp); 942 wdr->sata_iot = sc->sc_ba5_st; 943 wdr->sata_baseioh = sc->sc_ba5_sh; 944 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 945 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 946 &wdr->sata_status) != 0) { 947 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 948 "couldn't map channel %d sata_status regs\n", 949 wdc_cp->ch_channel); 950 continue; 951 } 952 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 953 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 954 &wdr->sata_error) != 0) { 955 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 956 "couldn't map channel %d sata_error regs\n", 957 wdc_cp->ch_channel); 958 continue; 959 } 960 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 961 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 962 &wdr->sata_control) != 0) { 963 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 964 "couldn't map channel %d sata_control regs\n", 965 wdc_cp->ch_channel); 966 continue; 967 } 968 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 969 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 970 } 971 } 972 973 static void 974 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 975 { 976 via_sata_chip_map(sc, pa, 6); 977 } 978 979 static void 980 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 981 { 982 via_sata_chip_map(sc, pa, 7); 983 } 984 985 static void 986 via_sata_chip_map_new(struct pciide_softc *sc, 987 const struct pci_attach_args *pa0) 988 { 989 struct pciide_channel *cp; 990 struct ata_channel *wdc_cp; 991 struct wdc_regs *wdr; 992 struct pci_attach_args pacopy, *pa; 993 pcireg_t interface; 994 int channel; 995 pci_intr_handle_t intrhandle; 996 const char *intrstr; 997 int i; 998 999 pacopy = *pa0; 1000 pa = &pacopy; 1001 interface = PCI_INTERFACE(pa->pa_class); 1002 1003 if (via_sata_chip_map_common(sc, pa) == 0) 1004 return; 1005 1006 if (interface == 0) { 1007 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1008 DEBUG_PROBE); 1009 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1010 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1011 } 1012 1013 if (pci_intr_map(pa, &intrhandle) != 0) { 1014 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1015 "couldn't map native-PCI interrupt\n"); 1016 return; 1017 } 1018 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1019 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1020 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1021 if (sc->sc_pci_ih == NULL) { 1022 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1023 "couldn't establish native-PCI interrupt"); 1024 if (intrstr != NULL) 1025 aprint_error(" at %s", intrstr); 1026 aprint_error("\n"); 1027 return; 1028 } 1029 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1030 "using %s for native-PCI interrupt\n", 1031 intrstr ? intrstr : "unknown interrupt"); 1032 1033 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1034 channel++) { 1035 cp = &sc->pciide_channels[channel]; 1036 if (pciide_chansetup(sc, channel, interface) == 0) 1037 continue; 1038 cp->ata_channel.ch_ndrive = 1; 1039 wdc_cp = &cp->ata_channel; 1040 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1041 1042 wdr->sata_iot = sc->sc_ba5_st; 1043 wdr->sata_baseioh = sc->sc_ba5_sh; 1044 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1045 (wdc_cp->ch_channel << 6) + 0x0, 4, 1046 &wdr->sata_status) != 0) { 1047 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1048 "couldn't map channel %d sata_status regs\n", 1049 wdc_cp->ch_channel); 1050 continue; 1051 } 1052 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1053 (wdc_cp->ch_channel << 6) + 0x4, 4, 1054 &wdr->sata_error) != 0) { 1055 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1056 "couldn't map channel %d sata_error regs\n", 1057 wdc_cp->ch_channel); 1058 continue; 1059 } 1060 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1061 (wdc_cp->ch_channel << 6) + 0x8, 4, 1062 &wdr->sata_control) != 0) { 1063 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1064 "couldn't map channel %d sata_control regs\n", 1065 wdc_cp->ch_channel); 1066 continue; 1067 } 1068 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1069 1070 if (pci_mapreg_map(pa, (PCI_MAPREG_START + (4 * (channel))), 1071 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1072 NULL, &wdr->cmd_ios) != 0) { 1073 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1074 "couldn't map %s channel regs\n", cp->name); 1075 } 1076 wdr->ctl_iot = wdr->cmd_iot; 1077 for (i = 0; i < WDC_NREG; i++) { 1078 if (bus_space_subregion(wdr->cmd_iot, 1079 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1080 &wdr->cmd_iohs[i]) != 0) { 1081 aprint_error_dev( 1082 sc->sc_wdcdev.sc_atac.atac_dev, 1083 "couldn't subregion %s " 1084 "channel cmd regs\n", cp->name); 1085 return; 1086 } 1087 } 1088 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1089 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1090 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1091 "couldn't map channel %d ctl regs\n", channel); 1092 return; 1093 } 1094 wdc_init_shadow_regs(wdc_cp); 1095 wdr->data32iot = wdr->cmd_iot; 1096 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1097 wdcattach(wdc_cp); 1098 } 1099 } 1100