1 /* $NetBSD: universe_pci.c,v 1.9 2009/03/14 21:04:21 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1999 5 * Matthias Drochner. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Common functions for PCI-VME-interfaces using the 31 * Newbridge/Tundra Universe II chip (CA91C142). 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: universe_pci.c,v 1.9 2009/03/14 21:04:21 dsl Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 /*#include <dev/pci/pcidevs.h>*/ 44 45 #include <sys/bus.h> 46 47 #include <dev/vme/vmereg.h> 48 #include <dev/vme/vmevar.h> 49 50 #include <dev/ic/universereg.h> 51 #include <dev/pci/universe_pci_var.h> 52 53 int univ_pci_intr(void *); 54 55 #define read_csr_4(d, reg) \ 56 bus_space_read_4(d->csrt, d->csrh, offsetof(struct universereg, reg)) 57 #define write_csr_4(d, reg, val) \ 58 bus_space_write_4(d->csrt, d->csrh, offsetof(struct universereg, reg), val) 59 60 #define _pso(i) offsetof(struct universereg, __CONCAT(pcislv, i)) 61 static int pcislvoffsets[8] = { 62 _pso(0), _pso(1), _pso(2), _pso(3), 63 _pso(4), _pso(5), _pso(6), _pso(7) 64 }; 65 #undef _pso 66 67 #define read_pcislv(d, idx, reg) \ 68 bus_space_read_4(d->csrt, d->csrh, \ 69 pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg)) 70 #define write_pcislv(d, idx, reg, val) \ 71 bus_space_write_4(d->csrt, d->csrh, \ 72 pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg), val) 73 74 75 #define _vso(i) offsetof(struct universereg, __CONCAT(vmeslv, i)) 76 static int vmeslvoffsets[8] = { 77 _vso(0), _vso(1), _vso(2), _vso(3), 78 _vso(4), _vso(5), _vso(6), _vso(7) 79 }; 80 #undef _vso 81 82 #define read_vmeslv(d, idx, reg) \ 83 bus_space_read_4(d->csrt, d->csrh, \ 84 vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg)) 85 #define write_vmeslv(d, idx, reg, val) \ 86 bus_space_write_4(d->csrt, d->csrh, \ 87 vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg), val) 88 89 int 90 univ_pci_attach(d, pa, name, inthdl, intcookie) 91 struct univ_pci_data *d; 92 struct pci_attach_args *pa; 93 const char *name; 94 void (*inthdl)(void *, int, int); 95 void *intcookie; 96 { 97 pci_chipset_tag_t pc = pa->pa_pc; 98 pci_intr_handle_t ih; 99 const char *intrstr = NULL; 100 u_int32_t reg; 101 int i; 102 103 d->pc = pc; 104 strncpy(d->devname, name, sizeof(d->devname)); 105 d->devname[sizeof(d->devname) - 1] = '\0'; 106 107 if (pci_mapreg_map(pa, 0x10, 108 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 109 0, &d->csrt, &d->csrh, NULL, NULL) && 110 pci_mapreg_map(pa, 0x14, 111 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 112 0, &d->csrt, &d->csrh, NULL, NULL) && 113 pci_mapreg_map(pa, 0x10, 114 PCI_MAPREG_TYPE_IO, 115 0, &d->csrt, &d->csrh, NULL, NULL) && 116 pci_mapreg_map(pa, 0x14, 117 PCI_MAPREG_TYPE_IO, 118 0, &d->csrt, &d->csrh, NULL, NULL)) 119 return (-1); 120 121 /* name sure the chip is in a sane state */ 122 write_csr_4(d, lint_en, 0); /* mask all PCI interrupts */ 123 write_csr_4(d, vint_en, 0); /* mask all VME interrupts */ 124 write_csr_4(d, dgcs, 0x40000000); /* stop DMA activity */ 125 for (i = 0; i < 8; i++) { 126 univ_pci_unmapvme(d, i); 127 univ_pci_unmappci(d, i); 128 } 129 write_csr_4(d, slsi, 0); /* disable "special PCI slave image" */ 130 131 /* enable DMA */ 132 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 133 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 134 PCI_COMMAND_MASTER_ENABLE); 135 136 reg = read_csr_4(d, misc_ctl); 137 aprint_normal("%s: ", name); 138 if (reg & 0x00020000) /* SYSCON */ 139 aprint_normal("VME bus controller, "); 140 reg = read_csr_4(d, mast_ctl); 141 aprint_normal("requesting at VME bus level %d\n", (reg >> 22) & 3); 142 143 /* Map and establish the PCI interrupt. */ 144 if (pci_intr_map(pa, &ih)) { 145 aprint_error("%s: couldn't map interrupt\n", name); 146 return (-1); 147 } 148 intrstr = pci_intr_string(pc, ih); 149 /* 150 * Use a low interrupt level (the lowest?). 151 * We will raise before calling a subdevice's handler. 152 */ 153 d->ih = pci_intr_establish(pc, ih, IPL_BIO, univ_pci_intr, d); 154 if (d->ih == NULL) { 155 aprint_error("%s: couldn't establish interrupt", name); 156 if (intrstr != NULL) 157 aprint_normal(" at %s", intrstr); 158 aprint_normal("\n"); 159 return (-1); 160 } 161 aprint_normal("%s: interrupting at %s\n", name, intrstr); 162 163 /* handle all VME interrupts (XXX should be configurable) */ 164 d->vmeinthandler = inthdl; 165 d->vmeintcookie = intcookie; 166 write_csr_4(d, lint_stat, 0x00ff37ff); /* ack all pending IRQs */ 167 write_csr_4(d, lint_en, 0x000000fe); /* enable VME IRQ 1..7 */ 168 169 return (0); 170 } 171 172 int 173 univ_pci_mapvme(struct univ_pci_data *d, int wnd, vme_addr_t vmebase, u_int32_t len, vme_am_t am, vme_datasize_t datawidth, u_int32_t pcibase) 174 { 175 u_int32_t ctl = 0x80000000; 176 177 switch (am & VME_AM_ADRSIZEMASK) { 178 case VME_AM_A32: 179 ctl |= 0x00020000; 180 break; 181 case VME_AM_A24: 182 ctl |= 0x00010000; 183 break; 184 case VME_AM_A16: 185 break; 186 default: 187 return (EINVAL); 188 } 189 if (am & VME_AM_SUPER) 190 ctl |= 0x00001000; 191 if ((am & VME_AM_MODEMASK) == VME_AM_PRG) 192 ctl |= 0x00004000; 193 if (datawidth & VME_D32) 194 ctl |= 0x00800000; 195 else if (datawidth & VME_D16) 196 ctl |= 0x00400000; 197 else if (!(datawidth & VME_D8)) 198 return (EINVAL); 199 200 #ifdef UNIV_DEBUG 201 printf("%s: wnd %d, map VME %x-%x to %x, ctl=%x\n", 202 d->devname, wnd, vmebase, vmebase + len, pcibase, ctl); 203 #endif 204 205 write_pcislv(d, wnd, lsi_bs, pcibase); 206 write_pcislv(d, wnd, lsi_bd, pcibase + len); 207 write_pcislv(d, wnd, lsi_to, vmebase - pcibase); 208 write_pcislv(d, wnd, lsi_ctl, ctl); 209 return (0); 210 } 211 212 void 213 univ_pci_unmapvme(struct univ_pci_data *d, int wnd) 214 { 215 #ifdef UNIV_DEBUG 216 printf("%s: unmap VME wnd %d\n", d->devname, wnd); 217 #endif 218 write_pcislv(d, wnd, lsi_ctl, 0); 219 } 220 221 222 int 223 univ_pci_mappci(struct univ_pci_data *d, int wnd, u_int32_t pcibase, u_int32_t len, vme_addr_t vmebase, vme_am_t am) 224 { 225 u_int32_t ctl = 0x80000000; 226 227 switch (am & VME_AM_ADRSIZEMASK) { 228 case VME_AM_A32: 229 ctl |= 0x00020000; 230 break; 231 case VME_AM_A24: 232 ctl |= 0x00010000; 233 break; 234 case VME_AM_A16: 235 break; 236 default: 237 return (EINVAL); 238 } 239 if (am & VME_AM_SUPER) 240 ctl |= 0x00200000; 241 else 242 ctl |= 0x00300000; /* both */ 243 if ((am & VME_AM_MODEMASK) == VME_AM_PRG) 244 ctl |= 0x00800000; 245 else 246 ctl |= 0x00c00000; /* both */ 247 248 #ifdef UNIV_DEBUG 249 printf("%s: wnd %d, map PCI %x-%x to %x, ctl=%x\n", 250 d->devname, wnd, pcibase, pcibase + len, vmebase, ctl); 251 #endif 252 253 write_vmeslv(d, wnd, vsi_bs, vmebase); 254 write_vmeslv(d, wnd, vsi_bd, vmebase + len); 255 write_vmeslv(d, wnd, vsi_to, pcibase - vmebase); 256 write_vmeslv(d, wnd, vsi_ctl, ctl); 257 return (0); 258 } 259 260 void 261 univ_pci_unmappci(struct univ_pci_data *d, int wnd) 262 { 263 #ifdef UNIV_DEBUG 264 printf("%s: unmap PCI wnd %d\n", d->devname, wnd); 265 #endif 266 write_vmeslv(d, wnd, vsi_ctl, 0); 267 } 268 269 int 270 univ_pci_vmebuserr(struct univ_pci_data *d, int clear) 271 { 272 u_int32_t pcicsr; 273 274 pcicsr = read_csr_4(d, pci_csr); 275 if ((pcicsr & 0xf8000000) && clear) 276 write_csr_4(d, pci_csr, pcicsr | 0xf8000000); 277 return (pcicsr & 0x08000000); /* target abort */ 278 } 279 280 int 281 univ_pci_intr(void *v) 282 { 283 struct univ_pci_data *d = v; 284 u_int32_t intcsr; 285 int i, vec; 286 287 intcsr = read_csr_4(d, lint_stat) & 0xffffff; 288 if (!intcsr) 289 return (0); 290 291 /* ack everything */ 292 write_csr_4(d, lint_stat, intcsr); 293 #ifdef UNIV_DEBUG 294 printf("%s: intr, lint_stat=%x\n", d->devname, intcsr); 295 #endif 296 if (intcsr & 0x000000fe) { /* VME interrupt */ 297 for (i = 7; i >= 1; i--) { 298 if (!(intcsr & (1 << i))) 299 continue; 300 vec = read_csr_4(d, v_statid[i - 1]); 301 if (vec & 0x100) { 302 printf("%s: err irq %d\n", d->devname, i); 303 continue; 304 } 305 if (d->vmeinthandler) 306 (*d->vmeinthandler)(d->vmeintcookie, i, vec); 307 } 308 } 309 310 return (1); 311 } 312