1 /* $NetBSD: ubsec.c,v 1.1 2003/08/01 00:08:55 jonathan Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.127 2003/06/04 14:04:58 jason Exp $ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #undef UBSEC_DEBUG 38 39 /* 40 * uBsec 5[56]01, bcm580xx, bcm582x hardware crypto accelerator 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/proc.h> 46 #include <sys/endian.h> 47 #ifdef __NetBSD__ 48 #define letoh16 htole16 49 #define letoh32 htole32 50 #define UBSEC_NO_RNG /* until statistically tested */ 51 #endif 52 #include <sys/errno.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/mbuf.h> 56 #include <sys/device.h> 57 #include <sys/queue.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <opencrypto/cryptodev.h> 62 #include <opencrypto/cryptosoft.h> 63 #ifdef __OpenBSD__ 64 #include <dev/rndvar.h> 65 #include <sys/md5k.h> 66 #else 67 #include <sys/rnd.h> 68 #include <sys/md5.h> 69 #endif 70 #include <sys/sha1.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/ubsecreg.h> 77 #include <dev/pci/ubsecvar.h> 78 79 /* 80 * Prototypes and count for the pci_device structure 81 */ 82 static int ubsec_probe(struct device *, struct cfdata *, void *); 83 static void ubsec_attach(struct device *, struct device *, void *); 84 static void ubsec_reset_board(struct ubsec_softc *); 85 static void ubsec_init_board(struct ubsec_softc *); 86 static void ubsec_init_pciregs(struct pci_attach_args *pa); 87 static void ubsec_cleanchip(struct ubsec_softc *); 88 static void ubsec_totalreset(struct ubsec_softc *); 89 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 90 91 #ifdef __OpenBSD__ 92 struct cfattach ubsec_ca = { 93 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 94 }; 95 96 struct cfdriver ubsec_cd = { 97 0, "ubsec", DV_DULL 98 }; 99 #else 100 CFATTACH_DECL(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 101 NULL, NULL); 102 extern struct cfdriver ubsec_cd; 103 #endif 104 105 /* patchable */ 106 #ifdef UBSEC_DEBUG 107 extern int ubsec_debug; 108 int ubsec_debug=1; 109 #endif 110 111 static int ubsec_intr(void *); 112 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 113 static int ubsec_freesession(void*, u_int64_t); 114 static int ubsec_process(void*, struct cryptop *, int hint); 115 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 116 static void ubsec_feed(struct ubsec_softc *); 117 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 118 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 119 static void ubsec_feed2(struct ubsec_softc *); 120 #ifndef UBSEC_NO_RNG 121 static void ubsec_rng(void *); 122 #endif /* UBSEC_NO_RNG */ 123 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 124 struct ubsec_dma_alloc *, int); 125 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 126 static int ubsec_dmamap_aligned(bus_dmamap_t); 127 128 #ifdef __OpenBSD__ 129 struct ubsec_softc *ubsec_kfind(struct cryptkop *); 130 #endif 131 132 static int ubsec_kprocess(void*, struct cryptkop *, int); 133 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 134 struct cryptkop *, int); 135 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 136 struct cryptkop *, int); 137 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 138 struct cryptkop *, int); 139 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 140 static int ubsec_ksigbits(struct crparam *); 141 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 142 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 143 144 #ifdef UBSEC_DEBUG 145 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 146 static void ubsec_dump_mcr(struct ubsec_mcr *); 147 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 148 #endif 149 150 #define READ_REG(sc,r) \ 151 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 152 153 #define WRITE_REG(sc,reg,val) \ 154 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 155 156 #define SWAP32(x) (x) = htole32(ntohl((x))) 157 #ifndef HTOLE32 158 #define HTOLE32(x) (x) = htole32(x) 159 #endif 160 161 struct ubsec_stats ubsecstats; 162 163 /* 164 * ubsec_maxbatch controls the number of crypto ops to voluntarily 165 * collect into one submission to the hardware. This batching happens 166 * when ops are dispatched from the crypto subsystem with a hint that 167 * more are to follow immediately. These ops must also not be marked 168 * with a ``no delay'' flag. 169 */ 170 static int ubsec_maxbatch = 1; 171 #ifdef SYSCTL_INT 172 SYSCTL_INT(_kern, OID_AUTO, ubsec_maxbatch, CTLFLAG_RW, &ubsec_maxbatch, 173 0, "Broadcom driver: max ops to batch w/o interrupt"); 174 #endif 175 176 /* 177 * ubsec_maxaggr controls the number of crypto ops to submit to the 178 * hardware as a unit. This aggregation reduces the number of interrupts 179 * to the host at the expense of increased latency (for all but the last 180 * operation). For network traffic setting this to one yields the highest 181 * performance but at the expense of more interrupt processing. 182 */ 183 static int ubsec_maxaggr = 1; 184 #ifdef SYSCTL_INT 185 SYSCTL_INT(_kern, OID_AUTO, ubsec_maxaggr, CTLFLAG_RW, &ubsec_maxaggr, 186 0, "Broadcom driver: max ops to aggregate under one interrupt"); 187 #endif 188 189 static int 190 ubsec_probe(parent, match, aux) 191 struct device *parent; 192 struct cfdata *match; 193 void *aux; 194 { 195 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 196 197 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BLUESTEEL && 198 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BLUESTEEL_5501 || 199 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BLUESTEEL_5601)) 200 return (1); 201 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 202 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5801 || 203 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5802 || 204 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5805 || 205 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5820 || 206 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5821 || 207 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5822 || 208 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5823)) 209 return (1); 210 211 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 212 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SCA1K || 213 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_5821)) 214 return (1); 215 216 return (0); 217 } 218 219 void 220 ubsec_attach(parent, self, aux) 221 struct device *parent, *self; 222 void *aux; 223 { 224 struct ubsec_softc *sc = (struct ubsec_softc *)self; 225 struct pci_attach_args *pa = aux; 226 pci_chipset_tag_t pc = pa->pa_pc; 227 pci_intr_handle_t ih; 228 const char *intrstr = NULL; 229 struct ubsec_dma *dmap; 230 bus_size_t iosize; 231 int mapreg; 232 u_int32_t cmd, i; 233 234 SIMPLEQ_INIT(&sc->sc_queue); 235 SIMPLEQ_INIT(&sc->sc_qchip); 236 SIMPLEQ_INIT(&sc->sc_queue2); 237 SIMPLEQ_INIT(&sc->sc_qchip2); 238 SIMPLEQ_INIT(&sc->sc_q2free); 239 240 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 241 242 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BLUESTEEL && 243 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BLUESTEEL_5601) 244 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 245 246 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 247 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5802 || 248 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5805)) 249 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 250 251 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 252 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5820 || 253 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5822)) 254 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 255 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 256 257 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 258 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5821 || 259 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5822 || 260 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5823)) || 261 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 262 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SCA1K || 263 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_5821))) { 264 /* NB: the 5821/5822 defines some additional status bits */ 265 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 266 BS_STAT_MCR2_ALLEMPTY; 267 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 268 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 269 } 270 271 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 272 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 273 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 274 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 275 276 if (!(cmd & PCI_COMMAND_MEM_ENABLE)) { 277 printf(": failed to enable memory mapping\n"); 278 return; 279 } 280 281 if (!(cmd & PCI_COMMAND_MASTER_ENABLE)) { 282 printf(": failed to enable bus mastering\n"); 283 return; 284 } 285 286 #ifdef __OpenBSD__ 287 mapreg= pci_mapreg_map(pa, BS_BAR, PCI_MAPREG_TYPE_MEM, 0, 288 &sc->sc_st, &sc->sc_sh, NULL, &iosize, 0); 289 #else 290 mapreg= pci_mapreg_map(pa, BS_BAR, PCI_MAPREG_TYPE_MEM, 0, 291 &sc->sc_st, &sc->sc_sh, &iosize, 0); 292 #endif 293 294 if (mapreg) { 295 printf(": can't find mem space\n"); 296 return; 297 } 298 sc->sc_dmat = pa->pa_dmat; 299 300 if (pci_intr_map(pa, &ih)) { 301 printf(": couldn't map interrupt\n"); 302 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); 303 return; 304 } 305 intrstr = pci_intr_string(pc, ih); 306 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ubsec_intr, sc 307 /*, self->dv_xname*/); 308 if (sc->sc_ih == NULL) { 309 printf(": couldn't establish interrupt"); 310 if (intrstr != NULL) 311 printf(" at %s", intrstr); 312 printf("\n"); 313 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); 314 return; 315 } 316 317 sc->sc_cid = crypto_get_driverid(0); 318 if (sc->sc_cid < 0) { 319 pci_intr_disestablish(pc, sc->sc_ih); 320 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); 321 return; 322 } 323 324 SIMPLEQ_INIT(&sc->sc_freequeue); 325 dmap = sc->sc_dmaa; 326 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 327 struct ubsec_q *q; 328 329 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 330 M_DEVBUF, M_NOWAIT); 331 if (q == NULL) { 332 printf(": can't allocate queue buffers\n"); 333 break; 334 } 335 336 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 337 &dmap->d_alloc, 0)) { 338 printf(": can't allocate dma buffers\n"); 339 free(q, M_DEVBUF); 340 break; 341 } 342 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 343 344 q->q_dma = dmap; 345 sc->sc_queuea[i] = q; 346 347 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 348 } 349 350 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 351 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 352 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 353 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 354 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 355 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 356 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 357 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 358 359 /* 360 * Reset Broadcom chip 361 */ 362 ubsec_reset_board(sc); 363 364 /* 365 * Init Broadcom specific PCI settings 366 */ 367 ubsec_init_pciregs(pa); 368 369 /* 370 * Init Broadcom chip 371 */ 372 ubsec_init_board(sc); 373 374 printf(": %s", intrstr); 375 376 #ifndef UBSEC_NO_RNG 377 if (sc->sc_flags & UBS_FLAGS_RNG) { 378 sc->sc_statmask |= BS_STAT_MCR2_DONE; 379 380 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 381 &sc->sc_rng.rng_q.q_mcr, 0)) 382 goto skip_rng; 383 384 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 385 &sc->sc_rng.rng_q.q_ctx, 0)) { 386 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 387 goto skip_rng; 388 } 389 390 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 391 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 392 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 393 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 394 goto skip_rng; 395 } 396 397 if (hz >= 100) 398 sc->sc_rnghz = hz / 100; 399 else 400 sc->sc_rnghz = 1; 401 #ifdef __OpenBSD__ 402 timeout_set(&sc->sc_rngto, ubsec_rng, sc); 403 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 404 #else 405 callout_init(&sc->sc_rngto); 406 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 407 #endif 408 printf(", rng"); 409 skip_rng: 410 ; 411 } 412 #endif /* UBSEC_NO_RNG */ 413 414 if (sc->sc_flags & UBS_FLAGS_KEY) { 415 sc->sc_statmask |= BS_STAT_MCR2_DONE; 416 417 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 418 ubsec_kprocess, sc); 419 #if 0 420 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 421 ubsec_kprocess, sc); 422 #endif 423 } 424 425 printf("\n"); 426 } 427 428 /* 429 * UBSEC Interrupt routine 430 */ 431 int 432 ubsec_intr(void *arg) 433 { 434 struct ubsec_softc *sc = arg; 435 volatile u_int32_t stat; 436 struct ubsec_q *q; 437 struct ubsec_dma *dmap; 438 int npkts = 0, i; 439 440 stat = READ_REG(sc, BS_STAT); 441 stat &= sc->sc_statmask; 442 if (stat == 0) { 443 return (0); 444 } 445 446 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 447 448 /* 449 * Check to see if we have any packets waiting for us 450 */ 451 if ((stat & BS_STAT_MCR1_DONE)) { 452 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 453 q = SIMPLEQ_FIRST(&sc->sc_qchip); 454 dmap = q->q_dma; 455 456 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 457 break; 458 459 q = SIMPLEQ_FIRST(&sc->sc_qchip); 460 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 461 462 npkts = q->q_nstacked_mcrs; 463 sc->sc_nqchip -= 1+npkts; 464 /* 465 * search for further sc_qchip ubsec_q's that share 466 * the same MCR, and complete them too, they must be 467 * at the top. 468 */ 469 for (i = 0; i < npkts; i++) { 470 if(q->q_stacked_mcr[i]) 471 ubsec_callback(sc, q->q_stacked_mcr[i]); 472 else 473 break; 474 } 475 ubsec_callback(sc, q); 476 } 477 478 /* 479 * Don't send any more packet to chip if there has been 480 * a DMAERR. 481 */ 482 if (!(stat & BS_STAT_DMAERR)) 483 ubsec_feed(sc); 484 } 485 486 /* 487 * Check to see if we have any key setups/rng's waiting for us 488 */ 489 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 490 (stat & BS_STAT_MCR2_DONE)) { 491 struct ubsec_q2 *q2; 492 struct ubsec_mcr *mcr; 493 494 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 495 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 496 497 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 498 0, q2->q_mcr.dma_map->dm_mapsize, 499 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 500 501 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 502 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 503 bus_dmamap_sync(sc->sc_dmat, 504 q2->q_mcr.dma_map, 0, 505 q2->q_mcr.dma_map->dm_mapsize, 506 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 507 break; 508 } 509 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 510 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 511 ubsec_callback2(sc, q2); 512 /* 513 * Don't send any more packet to chip if there has been 514 * a DMAERR. 515 */ 516 if (!(stat & BS_STAT_DMAERR)) 517 ubsec_feed2(sc); 518 } 519 } 520 521 /* 522 * Check to see if we got any DMA Error 523 */ 524 if (stat & BS_STAT_DMAERR) { 525 #ifdef UBSEC_DEBUG 526 if (ubsec_debug) { 527 volatile u_int32_t a = READ_REG(sc, BS_ERR); 528 529 printf("%s: dmaerr %s@%08x\n", sc->sc_dv.dv_xname, 530 (a & BS_ERR_READ) ? "read" : "write", 531 a & BS_ERR_ADDR); 532 } 533 #endif /* UBSEC_DEBUG */ 534 ubsecstats.hst_dmaerr++; 535 ubsec_totalreset(sc); 536 ubsec_feed(sc); 537 } 538 539 if (sc->sc_needwakeup) { /* XXX check high watermark */ 540 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 541 #ifdef UBSEC_DEBUG 542 if (ubsec_debug) 543 printf("%s: wakeup crypto (%x)\n", sc->sc_dv.dv_xname, 544 sc->sc_needwakeup); 545 #endif /* UBSEC_DEBUG */ 546 sc->sc_needwakeup &= ~wakeup; 547 crypto_unblock(sc->sc_cid, wakeup); 548 } 549 return (1); 550 } 551 552 /* 553 * ubsec_feed() - aggregate and post requests to chip 554 * OpenBSD comments: 555 * It is assumed that the caller set splnet() 556 */ 557 static void 558 ubsec_feed(struct ubsec_softc *sc) 559 { 560 struct ubsec_q *q, *q2; 561 int npkts, i; 562 void *v; 563 u_int32_t stat; 564 #ifdef UBSEC_DEBUG 565 static int max; 566 #endif /* UBSEC_DEBUG */ 567 568 npkts = sc->sc_nqueue; 569 if (npkts > ubsecstats.hst_maxqueue) 570 ubsecstats.hst_maxqueue = npkts; 571 if (npkts < 2) 572 goto feed1; 573 574 /* 575 * Decide how many ops to combine in a single MCR. We cannot 576 * aggregate more than UBS_MAX_AGGR because this is the number 577 * of slots defined in the data structure. Otherwise we clamp 578 * based on the tunable parameter ubsec_maxaggr. Note that 579 * aggregation can happen in two ways: either by batching ops 580 * from above or because the h/w backs up and throttles us. 581 * Aggregating ops reduces the number of interrupts to the host 582 * but also (potentially) increases the latency for processing 583 * completed ops as we only get an interrupt when all aggregated 584 * ops have completed. 585 */ 586 if (npkts > UBS_MAX_AGGR) 587 npkts = UBS_MAX_AGGR; 588 if (npkts > ubsec_maxaggr) 589 npkts = ubsec_maxaggr; 590 if (npkts > ubsecstats.hst_maxbatch) 591 ubsecstats.hst_maxbatch = npkts; 592 if (npkts < 2) 593 goto feed1; 594 ubsecstats.hst_totbatch += npkts-1; 595 596 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 597 if (stat & BS_STAT_DMAERR) { 598 ubsec_totalreset(sc); 599 ubsecstats.hst_dmaerr++; 600 } else { 601 ubsecstats.hst_mcr1full++; 602 } 603 return; 604 } 605 606 #ifdef UBSEC_DEBUG 607 if (ubsec_debug) 608 printf("merging %d records\n", npkts); 609 /* XXX temporary aggregation statistics reporting code */ 610 if (max < npkts) { 611 max = npkts; 612 printf("%s: new max aggregate %d\n", sc->sc_dv.dv_xname, max); 613 } 614 #endif /* UBSEC_DEBUG */ 615 616 q = SIMPLEQ_FIRST(&sc->sc_queue); 617 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 618 --sc->sc_nqueue; 619 620 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 621 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 622 if (q->q_dst_map != NULL) 623 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 624 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 625 626 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 627 628 for (i = 0; i < q->q_nstacked_mcrs; i++) { 629 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 630 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 631 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 632 if (q2->q_dst_map != NULL) 633 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 634 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 635 q2= SIMPLEQ_FIRST(&sc->sc_queue); 636 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 637 --sc->sc_nqueue; 638 639 v = ((void *)&q2->q_dma->d_dma->d_mcr); 640 v = (char*)v + (sizeof(struct ubsec_mcr) - 641 sizeof(struct ubsec_mcr_add)); 642 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 643 q->q_stacked_mcr[i] = q2; 644 } 645 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 646 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 647 sc->sc_nqchip += npkts; 648 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 649 ubsecstats.hst_maxqchip = sc->sc_nqchip; 650 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 651 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 653 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 654 offsetof(struct ubsec_dmachunk, d_mcr)); 655 return; 656 657 feed1: 658 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 659 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 660 if (stat & BS_STAT_DMAERR) { 661 ubsec_totalreset(sc); 662 ubsecstats.hst_dmaerr++; 663 } else { 664 ubsecstats.hst_mcr1full++; 665 } 666 break; 667 } 668 669 q = SIMPLEQ_FIRST(&sc->sc_queue); 670 671 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 672 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 673 if (q->q_dst_map != NULL) 674 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 675 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 676 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 677 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 679 680 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 681 offsetof(struct ubsec_dmachunk, d_mcr)); 682 #ifdef UBSEC_DEBUG 683 if (ubsec_debug) 684 printf("feed: q->chip %p %08x stat %08x\n", 685 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 686 stat); 687 #endif /* UBSEC_DEBUG */ 688 q = SIMPLEQ_FIRST(&sc->sc_queue); 689 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 690 --sc->sc_nqueue; 691 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 692 sc->sc_nqchip++; 693 } 694 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 695 ubsecstats.hst_maxqchip = sc->sc_nqchip; 696 } 697 698 /* 699 * Allocate a new 'session' and return an encoded session id. 'sidp' 700 * contains our registration id, and should contain an encoded session 701 * id on successful allocation. 702 */ 703 static int 704 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 705 { 706 struct cryptoini *c, *encini = NULL, *macini = NULL; 707 struct ubsec_softc *sc; 708 struct ubsec_session *ses = NULL; 709 MD5_CTX md5ctx; 710 SHA1_CTX sha1ctx; 711 int i, sesn; 712 713 if (sidp == NULL || cri == NULL || sc == NULL) 714 return (EINVAL); 715 716 #ifdef __OpenBSD__ 717 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 718 sc = ubsec_cd.cd_devs[i]; 719 if (sc == NULL || sc->sc_cid == (*sidp)) 720 break; 721 } 722 if (sc == NULL) 723 return (EINVAL); 724 #else 725 sc = arg; 726 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 727 #endif /* __OpenBSD__ */ 728 729 for (c = cri; c != NULL; c = c->cri_next) { 730 if (c->cri_alg == CRYPTO_MD5_HMAC || 731 c->cri_alg == CRYPTO_SHA1_HMAC) { 732 if (macini) 733 return (EINVAL); 734 macini = c; 735 } else if (c->cri_alg == CRYPTO_DES_CBC || 736 c->cri_alg == CRYPTO_3DES_CBC) { 737 if (encini) 738 return (EINVAL); 739 encini = c; 740 } else 741 return (EINVAL); 742 } 743 if (encini == NULL && macini == NULL) 744 return (EINVAL); 745 746 if (sc->sc_sessions == NULL) { 747 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 748 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 749 if (ses == NULL) 750 return (ENOMEM); 751 sesn = 0; 752 sc->sc_nsessions = 1; 753 } else { 754 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 755 if (sc->sc_sessions[sesn].ses_used == 0) { 756 ses = &sc->sc_sessions[sesn]; 757 break; 758 } 759 } 760 761 if (ses == NULL) { 762 sesn = sc->sc_nsessions; 763 ses = (struct ubsec_session *)malloc((sesn + 1) * 764 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 765 if (ses == NULL) 766 return (ENOMEM); 767 bcopy(sc->sc_sessions, ses, sesn * 768 sizeof(struct ubsec_session)); 769 bzero(sc->sc_sessions, sesn * 770 sizeof(struct ubsec_session)); 771 free(sc->sc_sessions, M_DEVBUF); 772 sc->sc_sessions = ses; 773 ses = &sc->sc_sessions[sesn]; 774 sc->sc_nsessions++; 775 } 776 } 777 778 bzero(ses, sizeof(struct ubsec_session)); 779 ses->ses_used = 1; 780 if (encini) { 781 /* get an IV, network byte order */ 782 #ifdef __NetBSD__ 783 rnd_extract_data(ses->ses_iv, 784 sizeof(ses->ses_iv), RND_EXTRACT_ANY); 785 #else 786 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv)); 787 #endif 788 789 /* Go ahead and compute key in ubsec's byte order */ 790 if (encini->cri_alg == CRYPTO_DES_CBC) { 791 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 792 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 793 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 794 } else 795 bcopy(encini->cri_key, ses->ses_deskey, 24); 796 797 SWAP32(ses->ses_deskey[0]); 798 SWAP32(ses->ses_deskey[1]); 799 SWAP32(ses->ses_deskey[2]); 800 SWAP32(ses->ses_deskey[3]); 801 SWAP32(ses->ses_deskey[4]); 802 SWAP32(ses->ses_deskey[5]); 803 } 804 805 if (macini) { 806 for (i = 0; i < macini->cri_klen / 8; i++) 807 macini->cri_key[i] ^= HMAC_IPAD_VAL; 808 809 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 810 MD5Init(&md5ctx); 811 MD5Update(&md5ctx, macini->cri_key, 812 macini->cri_klen / 8); 813 MD5Update(&md5ctx, hmac_ipad_buffer, 814 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 815 bcopy(md5ctx.state, ses->ses_hminner, 816 sizeof(md5ctx.state)); 817 } else { 818 SHA1Init(&sha1ctx); 819 SHA1Update(&sha1ctx, macini->cri_key, 820 macini->cri_klen / 8); 821 SHA1Update(&sha1ctx, hmac_ipad_buffer, 822 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 823 bcopy(sha1ctx.state, ses->ses_hminner, 824 sizeof(sha1ctx.state)); 825 } 826 827 for (i = 0; i < macini->cri_klen / 8; i++) 828 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 829 830 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 831 MD5Init(&md5ctx); 832 MD5Update(&md5ctx, macini->cri_key, 833 macini->cri_klen / 8); 834 MD5Update(&md5ctx, hmac_opad_buffer, 835 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 836 bcopy(md5ctx.state, ses->ses_hmouter, 837 sizeof(md5ctx.state)); 838 } else { 839 SHA1Init(&sha1ctx); 840 SHA1Update(&sha1ctx, macini->cri_key, 841 macini->cri_klen / 8); 842 SHA1Update(&sha1ctx, hmac_opad_buffer, 843 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 844 bcopy(sha1ctx.state, ses->ses_hmouter, 845 sizeof(sha1ctx.state)); 846 } 847 848 for (i = 0; i < macini->cri_klen / 8; i++) 849 macini->cri_key[i] ^= HMAC_OPAD_VAL; 850 } 851 852 *sidp = UBSEC_SID(sc->sc_dv.dv_unit, sesn); 853 return (0); 854 } 855 856 /* 857 * Deallocate a session. 858 */ 859 static int 860 ubsec_freesession(void *arg, u_int64_t tid) 861 { 862 struct ubsec_softc *sc; 863 int session; 864 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 865 866 #ifdef __OpenBSD__ 867 int card; 868 869 card = UBSEC_CARD(sid); 870 if (card >= ubsec_cd.cd_ndevs || ubsec_cd.cd_devs[card] == NULL) 871 return (EINVAL); 872 sc = ubsec_cd.cd_devs[card]; 873 #else 874 sc = arg; 875 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 876 #endif 877 878 session = UBSEC_SESSION(sid); 879 if (session >= sc->sc_nsessions) 880 return (EINVAL); 881 882 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 883 return (0); 884 } 885 886 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 887 static void 888 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 889 { 890 struct ubsec_operand *op = arg; 891 892 KASSERT(nsegs <= UBS_MAX_SCATTER 893 /*, ("Too many DMA segments returned when mapping operand")*/); 894 #ifdef UBSEC_DEBUG 895 if (ubsec_debug) 896 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 897 (u_int) mapsize, nsegs); 898 #endif 899 op->mapsize = mapsize; 900 op->nsegs = nsegs; 901 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 902 } 903 #endif 904 905 static int 906 ubsec_process(void *arg, struct cryptop *crp, int hint) 907 { 908 struct ubsec_q *q = NULL; 909 #ifdef __OpenBSD__ 910 int card; 911 #endif 912 int err = 0, i, j, s, nicealign; 913 struct ubsec_softc *sc; 914 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 915 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 916 int sskip, dskip, stheend, dtheend; 917 int16_t coffset; 918 struct ubsec_session *ses; 919 struct ubsec_pktctx ctx; 920 struct ubsec_dma *dmap = NULL; 921 922 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 923 ubsecstats.hst_invalid++; 924 return (EINVAL); 925 } 926 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 927 ubsecstats.hst_badsession++; 928 return (EINVAL); 929 } 930 #ifdef __OpenBSD__ 931 card = UBSEC_CARD(crp->crp_sid); 932 if (card >= ubsec_cd.cd_ndevs || ubsec_cd.cd_devs[card] == NULL) { 933 ubsecstats.hst_invalid++; 934 return (EINVAL); 935 } 936 sc = ubsec_cd.cd_devs[card]; 937 #else 938 sc = arg; 939 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 940 #endif 941 942 943 944 s = splnet(); 945 946 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 947 ubsecstats.hst_queuefull++; 948 sc->sc_needwakeup |= CRYPTO_SYMQ; 949 splx(s); 950 return(ERESTART); 951 } 952 953 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 954 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 955 splx(s); 956 957 dmap = q->q_dma; /* Save dma pointer */ 958 bzero(q, sizeof(struct ubsec_q)); 959 bzero(&ctx, sizeof(ctx)); 960 961 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 962 q->q_dma = dmap; 963 ses = &sc->sc_sessions[q->q_sesn]; 964 965 if (crp->crp_flags & CRYPTO_F_IMBUF) { 966 q->q_src_m = (struct mbuf *)crp->crp_buf; 967 q->q_dst_m = (struct mbuf *)crp->crp_buf; 968 } else if (crp->crp_flags & CRYPTO_F_IOV) { 969 q->q_src_io = (struct uio *)crp->crp_buf; 970 q->q_dst_io = (struct uio *)crp->crp_buf; 971 } else { 972 ubsecstats.hst_badflags++; 973 err = EINVAL; 974 goto errout; /* XXX we don't handle contiguous blocks! */ 975 } 976 977 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 978 979 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 980 dmap->d_dma->d_mcr.mcr_flags = 0; 981 q->q_crp = crp; 982 983 crd1 = crp->crp_desc; 984 if (crd1 == NULL) { 985 ubsecstats.hst_nodesc++; 986 err = EINVAL; 987 goto errout; 988 } 989 crd2 = crd1->crd_next; 990 991 if (crd2 == NULL) { 992 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 993 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 994 maccrd = crd1; 995 enccrd = NULL; 996 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 997 crd1->crd_alg == CRYPTO_3DES_CBC) { 998 maccrd = NULL; 999 enccrd = crd1; 1000 } else { 1001 ubsecstats.hst_badalg++; 1002 err = EINVAL; 1003 goto errout; 1004 } 1005 } else { 1006 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1007 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1008 (crd2->crd_alg == CRYPTO_DES_CBC || 1009 crd2->crd_alg == CRYPTO_3DES_CBC) && 1010 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1011 maccrd = crd1; 1012 enccrd = crd2; 1013 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1014 crd1->crd_alg == CRYPTO_3DES_CBC) && 1015 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1016 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1017 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1018 enccrd = crd1; 1019 maccrd = crd2; 1020 } else { 1021 /* 1022 * We cannot order the ubsec as requested 1023 */ 1024 ubsecstats.hst_badalg++; 1025 err = EINVAL; 1026 goto errout; 1027 } 1028 } 1029 1030 if (enccrd) { 1031 encoffset = enccrd->crd_skip; 1032 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1033 1034 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1035 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1036 1037 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1038 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1039 else { 1040 ctx.pc_iv[0] = ses->ses_iv[0]; 1041 ctx.pc_iv[1] = ses->ses_iv[1]; 1042 } 1043 1044 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1045 if (crp->crp_flags & CRYPTO_F_IMBUF) 1046 m_copyback(q->q_src_m, 1047 enccrd->crd_inject, 1048 8, (caddr_t)ctx.pc_iv); 1049 else if (crp->crp_flags & CRYPTO_F_IOV) 1050 cuio_copyback(q->q_src_io, 1051 enccrd->crd_inject, 1052 8, (caddr_t)ctx.pc_iv); 1053 } 1054 } else { 1055 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1056 1057 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1058 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1059 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1060 m_copydata(q->q_src_m, enccrd->crd_inject, 1061 8, (caddr_t)ctx.pc_iv); 1062 else if (crp->crp_flags & CRYPTO_F_IOV) 1063 cuio_copydata(q->q_src_io, 1064 enccrd->crd_inject, 8, 1065 (caddr_t)ctx.pc_iv); 1066 } 1067 1068 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1069 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1070 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1071 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1072 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1073 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1074 SWAP32(ctx.pc_iv[0]); 1075 SWAP32(ctx.pc_iv[1]); 1076 } 1077 1078 if (maccrd) { 1079 macoffset = maccrd->crd_skip; 1080 1081 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1082 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1083 else 1084 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1085 1086 for (i = 0; i < 5; i++) { 1087 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1088 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1089 1090 HTOLE32(ctx.pc_hminner[i]); 1091 HTOLE32(ctx.pc_hmouter[i]); 1092 } 1093 } 1094 1095 if (enccrd && maccrd) { 1096 /* 1097 * ubsec cannot handle packets where the end of encryption 1098 * and authentication are not the same, or where the 1099 * encrypted part begins before the authenticated part. 1100 */ 1101 if ((encoffset + enccrd->crd_len) != 1102 (macoffset + maccrd->crd_len)) { 1103 ubsecstats.hst_lenmismatch++; 1104 err = EINVAL; 1105 goto errout; 1106 } 1107 if (enccrd->crd_skip < maccrd->crd_skip) { 1108 ubsecstats.hst_skipmismatch++; 1109 err = EINVAL; 1110 goto errout; 1111 } 1112 sskip = maccrd->crd_skip; 1113 cpskip = dskip = enccrd->crd_skip; 1114 stheend = maccrd->crd_len; 1115 dtheend = enccrd->crd_len; 1116 coffset = enccrd->crd_skip - maccrd->crd_skip; 1117 cpoffset = cpskip + dtheend; 1118 #ifdef UBSEC_DEBUG 1119 if (ubsec_debug) { 1120 printf("mac: skip %d, len %d, inject %d\n", 1121 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1122 printf("enc: skip %d, len %d, inject %d\n", 1123 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1124 printf("src: skip %d, len %d\n", sskip, stheend); 1125 printf("dst: skip %d, len %d\n", dskip, dtheend); 1126 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1127 coffset, stheend, cpskip, cpoffset); 1128 } 1129 #endif 1130 } else { 1131 cpskip = dskip = sskip = macoffset + encoffset; 1132 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1133 cpoffset = cpskip + dtheend; 1134 coffset = 0; 1135 } 1136 ctx.pc_offset = htole16(coffset >> 2); 1137 1138 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1139 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1140 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1141 err = ENOMEM; 1142 goto errout; 1143 } 1144 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1145 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1146 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1147 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1148 q->q_src_map = NULL; 1149 ubsecstats.hst_noload++; 1150 err = ENOMEM; 1151 goto errout; 1152 } 1153 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1154 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1155 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1156 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1157 q->q_src_map = NULL; 1158 ubsecstats.hst_noload++; 1159 err = ENOMEM; 1160 goto errout; 1161 } 1162 } 1163 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1164 1165 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1166 1167 #ifdef UBSEC_DEBUG 1168 if (ubsec_debug) 1169 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1170 #endif 1171 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1172 struct ubsec_pktbuf *pb; 1173 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1174 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1175 1176 if (sskip >= packl) { 1177 sskip -= packl; 1178 continue; 1179 } 1180 1181 packl -= sskip; 1182 packp += sskip; 1183 sskip = 0; 1184 1185 if (packl > 0xfffc) { 1186 err = EIO; 1187 goto errout; 1188 } 1189 1190 if (j == 0) 1191 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1192 else 1193 pb = &dmap->d_dma->d_sbuf[j - 1]; 1194 1195 pb->pb_addr = htole32(packp); 1196 1197 if (stheend) { 1198 if (packl > stheend) { 1199 pb->pb_len = htole32(stheend); 1200 stheend = 0; 1201 } else { 1202 pb->pb_len = htole32(packl); 1203 stheend -= packl; 1204 } 1205 } else 1206 pb->pb_len = htole32(packl); 1207 1208 if ((i + 1) == q->q_src_map->dm_nsegs) 1209 pb->pb_next = 0; 1210 else 1211 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1212 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1213 j++; 1214 } 1215 1216 if (enccrd == NULL && maccrd != NULL) { 1217 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1218 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1219 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1220 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1221 #ifdef UBSEC_DEBUG 1222 if (ubsec_debug) 1223 printf("opkt: %x %x %x\n", 1224 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1225 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1226 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1227 1228 #endif 1229 } else { 1230 if (crp->crp_flags & CRYPTO_F_IOV) { 1231 if (!nicealign) { 1232 ubsecstats.hst_iovmisaligned++; 1233 err = EINVAL; 1234 goto errout; 1235 } 1236 /* XXX: ``what the heck's that'' 0xfff0? */ 1237 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1238 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1239 &q->q_dst_map) != 0) { 1240 ubsecstats.hst_nomap++; 1241 err = ENOMEM; 1242 goto errout; 1243 } 1244 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1245 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1246 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1247 q->q_dst_map = NULL; 1248 ubsecstats.hst_noload++; 1249 err = ENOMEM; 1250 goto errout; 1251 } 1252 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1253 if (nicealign) { 1254 q->q_dst_m = q->q_src_m; 1255 q->q_dst_map = q->q_src_map; 1256 } else { 1257 int totlen, len; 1258 struct mbuf *m, *top, **mp; 1259 1260 ubsecstats.hst_unaligned++; 1261 totlen = q->q_src_map->dm_mapsize; 1262 if (q->q_src_m->m_flags & M_PKTHDR) { 1263 len = MHLEN; 1264 MGETHDR(m, M_DONTWAIT, MT_DATA); 1265 /*XXX FIXME: m_dup_pkthdr */ 1266 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1267 m_free(m); 1268 m = NULL; 1269 } 1270 } else { 1271 len = MLEN; 1272 MGET(m, M_DONTWAIT, MT_DATA); 1273 } 1274 if (m == NULL) { 1275 ubsecstats.hst_nombuf++; 1276 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1277 goto errout; 1278 } 1279 if (len == MHLEN) 1280 /*XXX was M_DUP_PKTHDR*/ 1281 M_COPY_PKTHDR(m, q->q_src_m); 1282 if (totlen >= MINCLSIZE) { 1283 MCLGET(m, M_DONTWAIT); 1284 if ((m->m_flags & M_EXT) == 0) { 1285 m_free(m); 1286 ubsecstats.hst_nomcl++; 1287 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1288 goto errout; 1289 } 1290 len = MCLBYTES; 1291 } 1292 m->m_len = len; 1293 top = NULL; 1294 mp = ⊤ 1295 1296 while (totlen > 0) { 1297 if (top) { 1298 MGET(m, M_DONTWAIT, MT_DATA); 1299 if (m == NULL) { 1300 m_freem(top); 1301 ubsecstats.hst_nombuf++; 1302 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1303 goto errout; 1304 } 1305 len = MLEN; 1306 } 1307 if (top && totlen >= MINCLSIZE) { 1308 MCLGET(m, M_DONTWAIT); 1309 if ((m->m_flags & M_EXT) == 0) { 1310 *mp = m; 1311 m_freem(top); 1312 ubsecstats.hst_nomcl++; 1313 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1314 goto errout; 1315 } 1316 len = MCLBYTES; 1317 } 1318 m->m_len = len = min(totlen, len); 1319 totlen -= len; 1320 *mp = m; 1321 mp = &m->m_next; 1322 } 1323 q->q_dst_m = top; 1324 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1325 cpskip, cpoffset); 1326 /* XXX again, what the heck is that 0xfff0? */ 1327 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1328 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1329 &q->q_dst_map) != 0) { 1330 ubsecstats.hst_nomap++; 1331 err = ENOMEM; 1332 goto errout; 1333 } 1334 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1335 q->q_dst_map, q->q_dst_m, 1336 BUS_DMA_NOWAIT) != 0) { 1337 bus_dmamap_destroy(sc->sc_dmat, 1338 q->q_dst_map); 1339 q->q_dst_map = NULL; 1340 ubsecstats.hst_noload++; 1341 err = ENOMEM; 1342 goto errout; 1343 } 1344 } 1345 } else { 1346 ubsecstats.hst_badflags++; 1347 err = EINVAL; 1348 goto errout; 1349 } 1350 1351 #ifdef UBSEC_DEBUG 1352 if (ubsec_debug) 1353 printf("dst skip: %d\n", dskip); 1354 #endif 1355 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1356 struct ubsec_pktbuf *pb; 1357 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1358 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1359 1360 if (dskip >= packl) { 1361 dskip -= packl; 1362 continue; 1363 } 1364 1365 packl -= dskip; 1366 packp += dskip; 1367 dskip = 0; 1368 1369 if (packl > 0xfffc) { 1370 err = EIO; 1371 goto errout; 1372 } 1373 1374 if (j == 0) 1375 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1376 else 1377 pb = &dmap->d_dma->d_dbuf[j - 1]; 1378 1379 pb->pb_addr = htole32(packp); 1380 1381 if (dtheend) { 1382 if (packl > dtheend) { 1383 pb->pb_len = htole32(dtheend); 1384 dtheend = 0; 1385 } else { 1386 pb->pb_len = htole32(packl); 1387 dtheend -= packl; 1388 } 1389 } else 1390 pb->pb_len = htole32(packl); 1391 1392 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1393 if (maccrd) 1394 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1395 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1396 else 1397 pb->pb_next = 0; 1398 } else 1399 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1400 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1401 j++; 1402 } 1403 } 1404 1405 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1406 offsetof(struct ubsec_dmachunk, d_ctx)); 1407 1408 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1409 struct ubsec_pktctx_long *ctxl; 1410 1411 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1412 offsetof(struct ubsec_dmachunk, d_ctx)); 1413 1414 /* transform small context into long context */ 1415 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1416 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1417 ctxl->pc_flags = ctx.pc_flags; 1418 ctxl->pc_offset = ctx.pc_offset; 1419 for (i = 0; i < 6; i++) 1420 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1421 for (i = 0; i < 5; i++) 1422 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1423 for (i = 0; i < 5; i++) 1424 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1425 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1426 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1427 } else 1428 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1429 offsetof(struct ubsec_dmachunk, d_ctx), 1430 sizeof(struct ubsec_pktctx)); 1431 1432 s = splnet(); 1433 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1434 sc->sc_nqueue++; 1435 ubsecstats.hst_ipackets++; 1436 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1437 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1438 ubsec_feed(sc); 1439 splx(s); 1440 return (0); 1441 1442 errout: 1443 if (q != NULL) { 1444 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1445 m_freem(q->q_dst_m); 1446 1447 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1448 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1449 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1450 } 1451 if (q->q_src_map != NULL) { 1452 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1453 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1454 } 1455 1456 s = splnet(); 1457 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1458 splx(s); 1459 } 1460 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1461 if (err == EINVAL) 1462 ubsecstats.hst_invalid++; 1463 else 1464 ubsecstats.hst_nomem++; 1465 #endif 1466 if (err != ERESTART) { 1467 crp->crp_etype = err; 1468 crypto_done(crp); 1469 } else { 1470 sc->sc_needwakeup |= CRYPTO_SYMQ; 1471 } 1472 return (err); 1473 } 1474 1475 void 1476 ubsec_callback(sc, q) 1477 struct ubsec_softc *sc; 1478 struct ubsec_q *q; 1479 { 1480 struct cryptop *crp = (struct cryptop *)q->q_crp; 1481 struct cryptodesc *crd; 1482 struct ubsec_dma *dmap = q->q_dma; 1483 1484 ubsecstats.hst_opackets++; 1485 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1486 1487 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1488 dmap->d_alloc.dma_map->dm_mapsize, 1489 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1490 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1491 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1492 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1493 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1494 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1495 } 1496 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1497 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1498 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1499 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1500 1501 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1502 m_freem(q->q_src_m); 1503 crp->crp_buf = (caddr_t)q->q_dst_m; 1504 } 1505 1506 /* copy out IV for future use */ 1507 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1508 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1509 if (crd->crd_alg != CRYPTO_DES_CBC && 1510 crd->crd_alg != CRYPTO_3DES_CBC) 1511 continue; 1512 if (crp->crp_flags & CRYPTO_F_IMBUF) 1513 m_copydata((struct mbuf *)crp->crp_buf, 1514 crd->crd_skip + crd->crd_len - 8, 8, 1515 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1516 else if (crp->crp_flags & CRYPTO_F_IOV) { 1517 cuio_copydata((struct uio *)crp->crp_buf, 1518 crd->crd_skip + crd->crd_len - 8, 8, 1519 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1520 } 1521 break; 1522 } 1523 } 1524 1525 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1526 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1527 crd->crd_alg != CRYPTO_SHA1_HMAC) 1528 continue; 1529 if (crp->crp_flags & CRYPTO_F_IMBUF) 1530 m_copyback((struct mbuf *)crp->crp_buf, 1531 crd->crd_inject, 12, 1532 (caddr_t)dmap->d_dma->d_macbuf); 1533 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1534 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1535 crp->crp_mac, 12); 1536 break; 1537 } 1538 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1539 crypto_done(crp); 1540 } 1541 1542 static void 1543 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1544 { 1545 int i, j, dlen, slen; 1546 caddr_t dptr, sptr; 1547 1548 j = 0; 1549 sptr = srcm->m_data; 1550 slen = srcm->m_len; 1551 dptr = dstm->m_data; 1552 dlen = dstm->m_len; 1553 1554 while (1) { 1555 for (i = 0; i < min(slen, dlen); i++) { 1556 if (j < hoffset || j >= toffset) 1557 *dptr++ = *sptr++; 1558 slen--; 1559 dlen--; 1560 j++; 1561 } 1562 if (slen == 0) { 1563 srcm = srcm->m_next; 1564 if (srcm == NULL) 1565 return; 1566 sptr = srcm->m_data; 1567 slen = srcm->m_len; 1568 } 1569 if (dlen == 0) { 1570 dstm = dstm->m_next; 1571 if (dstm == NULL) 1572 return; 1573 dptr = dstm->m_data; 1574 dlen = dstm->m_len; 1575 } 1576 } 1577 } 1578 1579 /* 1580 * feed the key generator, must be called at splnet() or higher. 1581 */ 1582 static void 1583 ubsec_feed2(struct ubsec_softc *sc) 1584 { 1585 struct ubsec_q2 *q; 1586 1587 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1588 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1589 break; 1590 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1591 1592 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1593 q->q_mcr.dma_map->dm_mapsize, 1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1595 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1596 q->q_ctx.dma_map->dm_mapsize, 1597 BUS_DMASYNC_PREWRITE); 1598 1599 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1600 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1601 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1602 --sc->sc_nqueue2; 1603 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1604 } 1605 } 1606 1607 /* 1608 * Callback for handling random numbers 1609 */ 1610 static void 1611 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1612 { 1613 struct cryptkop *krp; 1614 struct ubsec_ctx_keyop *ctx; 1615 1616 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1617 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1618 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1619 1620 switch (q->q_type) { 1621 #ifndef UBSEC_NO_RNG 1622 case UBS_CTXOP_RNGSHA1: 1623 case UBS_CTXOP_RNGBYPASS: { 1624 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1625 u_int32_t *p; 1626 int i; 1627 1628 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1629 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1630 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 1631 #ifndef __NetBSD__ 1632 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) 1633 add_true_randomness(letoh32(*p)); 1634 rng->rng_used = 0; 1635 #else 1636 /* XXX NetBSD rnd subsystem too weak */ 1637 i = 0; (void)i; /* shut off gcc warnings */ 1638 #endif 1639 #ifdef __OpenBSD__ 1640 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 1641 #else 1642 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1643 #endif 1644 break; 1645 } 1646 #endif 1647 case UBS_CTXOP_MODEXP: { 1648 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1649 u_int rlen, clen; 1650 1651 krp = me->me_krp; 1652 rlen = (me->me_modbits + 7) / 8; 1653 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1654 1655 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 1656 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1657 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 1658 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1659 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 1660 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1661 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 1662 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1663 1664 if (clen < rlen) 1665 krp->krp_status = E2BIG; 1666 else { 1667 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1668 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1669 (krp->krp_param[krp->krp_iparams].crp_nbits 1670 + 7) / 8); 1671 bcopy(me->me_C.dma_vaddr, 1672 krp->krp_param[krp->krp_iparams].crp_p, 1673 (me->me_modbits + 7) / 8); 1674 } else 1675 ubsec_kshift_l(me->me_shiftbits, 1676 me->me_C.dma_vaddr, me->me_normbits, 1677 krp->krp_param[krp->krp_iparams].crp_p, 1678 krp->krp_param[krp->krp_iparams].crp_nbits); 1679 } 1680 1681 crypto_kdone(krp); 1682 1683 /* bzero all potentially sensitive data */ 1684 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1685 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1686 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1687 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1688 1689 /* Can't free here, so put us on the free list. */ 1690 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1691 break; 1692 } 1693 case UBS_CTXOP_RSAPRIV: { 1694 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1695 u_int len; 1696 1697 krp = rp->rpr_krp; 1698 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 1699 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1700 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 1701 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1702 1703 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1704 bcopy(rp->rpr_msgout.dma_vaddr, 1705 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1706 1707 crypto_kdone(krp); 1708 1709 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1710 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1711 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1712 1713 /* Can't free here, so put us on the free list. */ 1714 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1715 break; 1716 } 1717 default: 1718 printf("%s: unknown ctx op: %x\n", sc->sc_dv.dv_xname, 1719 letoh16(ctx->ctx_op)); 1720 break; 1721 } 1722 } 1723 1724 #ifndef UBSEC_NO_RNG 1725 static void 1726 ubsec_rng(void *vsc) 1727 { 1728 struct ubsec_softc *sc = vsc; 1729 struct ubsec_q2_rng *rng = &sc->sc_rng; 1730 struct ubsec_mcr *mcr; 1731 struct ubsec_ctx_rngbypass *ctx; 1732 int s; 1733 1734 s = splnet(); 1735 if (rng->rng_used) { 1736 splx(s); 1737 return; 1738 } 1739 sc->sc_nqueue2++; 1740 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1741 goto out; 1742 1743 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1744 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1745 1746 mcr->mcr_pkts = htole16(1); 1747 mcr->mcr_flags = 0; 1748 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1749 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1750 mcr->mcr_ipktbuf.pb_len = 0; 1751 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1752 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1753 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1754 UBS_PKTBUF_LEN); 1755 mcr->mcr_opktbuf.pb_next = 0; 1756 1757 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1758 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 1759 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 1760 1761 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1762 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1763 1764 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1765 rng->rng_used = 1; 1766 ubsec_feed2(sc); 1767 ubsecstats.hst_rng++; 1768 splx(s); 1769 1770 return; 1771 1772 out: 1773 /* 1774 * Something weird happened, generate our own call back. 1775 */ 1776 sc->sc_nqueue2--; 1777 splx(s); 1778 #ifdef __OpenBSD__ 1779 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 1780 #else 1781 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1782 #endif 1783 } 1784 #endif /* UBSEC_NO_RNG */ 1785 1786 static int 1787 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 1788 struct ubsec_dma_alloc *dma,int mapflags) 1789 { 1790 int r; 1791 1792 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1793 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 1794 goto fail_0; 1795 1796 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1797 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1798 goto fail_1; 1799 1800 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1801 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1802 goto fail_2; 1803 1804 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1805 size, NULL, BUS_DMA_NOWAIT)) != 0) 1806 goto fail_3; 1807 1808 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1809 dma->dma_size = size; 1810 return (0); 1811 1812 fail_3: 1813 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1814 fail_2: 1815 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1816 fail_1: 1817 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1818 fail_0: 1819 dma->dma_map = NULL; 1820 return (r); 1821 } 1822 1823 static void 1824 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1825 { 1826 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1827 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 1828 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1829 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1830 } 1831 1832 /* 1833 * Resets the board. Values in the regesters are left as is 1834 * from the reset (i.e. initial values are assigned elsewhere). 1835 */ 1836 static void 1837 ubsec_reset_board(struct ubsec_softc *sc) 1838 { 1839 volatile u_int32_t ctrl; 1840 1841 ctrl = READ_REG(sc, BS_CTRL); 1842 ctrl |= BS_CTRL_RESET; 1843 WRITE_REG(sc, BS_CTRL, ctrl); 1844 1845 /* 1846 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1847 */ 1848 DELAY(10); 1849 } 1850 1851 /* 1852 * Init Broadcom registers 1853 */ 1854 static void 1855 ubsec_init_board(struct ubsec_softc *sc) 1856 { 1857 u_int32_t ctrl; 1858 1859 ctrl = READ_REG(sc, BS_CTRL); 1860 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1861 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1862 1863 /* 1864 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 1865 * anyone got hw docs? 1866 */ 1867 if (sc->sc_flags & UBS_FLAGS_KEY) 1868 ctrl |= BS_CTRL_MCR2INT; 1869 else 1870 ctrl &= ~BS_CTRL_MCR2INT; 1871 1872 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1873 ctrl &= ~BS_CTRL_SWNORM; 1874 1875 WRITE_REG(sc, BS_CTRL, ctrl); 1876 } 1877 1878 /* 1879 * Init Broadcom PCI registers 1880 */ 1881 static void 1882 ubsec_init_pciregs(pa) 1883 struct pci_attach_args *pa; 1884 { 1885 pci_chipset_tag_t pc = pa->pa_pc; 1886 u_int32_t misc; 1887 1888 /* 1889 * This will set the cache line size to 1, this will 1890 * force the BCM58xx chip just to do burst read/writes. 1891 * Cache line read/writes are to slow 1892 */ 1893 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 1894 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 1895 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 1896 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 1897 } 1898 1899 /* 1900 * Clean up after a chip crash. 1901 * It is assumed that the caller in splnet() 1902 */ 1903 static void 1904 ubsec_cleanchip(struct ubsec_softc *sc) 1905 { 1906 struct ubsec_q *q; 1907 1908 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1909 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1910 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 1911 ubsec_free_q(sc, q); 1912 } 1913 sc->sc_nqchip = 0; 1914 } 1915 1916 /* 1917 * free a ubsec_q 1918 * It is assumed that the caller is within splnet() 1919 */ 1920 static int 1921 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1922 { 1923 struct ubsec_q *q2; 1924 struct cryptop *crp; 1925 int npkts; 1926 int i; 1927 1928 npkts = q->q_nstacked_mcrs; 1929 1930 for (i = 0; i < npkts; i++) { 1931 if(q->q_stacked_mcr[i]) { 1932 q2 = q->q_stacked_mcr[i]; 1933 1934 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1935 m_freem(q2->q_dst_m); 1936 1937 crp = (struct cryptop *)q2->q_crp; 1938 1939 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 1940 1941 crp->crp_etype = EFAULT; 1942 crypto_done(crp); 1943 } else { 1944 break; 1945 } 1946 } 1947 1948 /* 1949 * Free header MCR 1950 */ 1951 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1952 m_freem(q->q_dst_m); 1953 1954 crp = (struct cryptop *)q->q_crp; 1955 1956 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1957 1958 crp->crp_etype = EFAULT; 1959 crypto_done(crp); 1960 return(0); 1961 } 1962 1963 /* 1964 * Routine to reset the chip and clean up. 1965 * It is assumed that the caller is in splnet() 1966 */ 1967 static void 1968 ubsec_totalreset(struct ubsec_softc *sc) 1969 { 1970 ubsec_reset_board(sc); 1971 ubsec_init_board(sc); 1972 ubsec_cleanchip(sc); 1973 } 1974 1975 static int 1976 ubsec_dmamap_aligned(bus_dmamap_t map) 1977 { 1978 int i; 1979 1980 for (i = 0; i < map->dm_nsegs; i++) { 1981 if (map->dm_segs[i].ds_addr & 3) 1982 return (0); 1983 if ((i != (map->dm_nsegs - 1)) && 1984 (map->dm_segs[i].ds_len & 3)) 1985 return (0); 1986 } 1987 return (1); 1988 } 1989 1990 #ifdef __OpenBSD__ 1991 struct ubsec_softc * 1992 ubsec_kfind(krp) 1993 struct cryptkop *krp; 1994 { 1995 struct ubsec_softc *sc; 1996 int i; 1997 1998 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 1999 sc = ubsec_cd.cd_devs[i]; 2000 if (sc == NULL) 2001 continue; 2002 if (sc->sc_cid == krp->krp_hid) 2003 return (sc); 2004 } 2005 return (NULL); 2006 } 2007 #endif 2008 2009 static void 2010 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2011 { 2012 switch (q->q_type) { 2013 case UBS_CTXOP_MODEXP: { 2014 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2015 2016 ubsec_dma_free(sc, &me->me_q.q_mcr); 2017 ubsec_dma_free(sc, &me->me_q.q_ctx); 2018 ubsec_dma_free(sc, &me->me_M); 2019 ubsec_dma_free(sc, &me->me_E); 2020 ubsec_dma_free(sc, &me->me_C); 2021 ubsec_dma_free(sc, &me->me_epb); 2022 free(me, M_DEVBUF); 2023 break; 2024 } 2025 case UBS_CTXOP_RSAPRIV: { 2026 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2027 2028 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2029 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2030 ubsec_dma_free(sc, &rp->rpr_msgin); 2031 ubsec_dma_free(sc, &rp->rpr_msgout); 2032 free(rp, M_DEVBUF); 2033 break; 2034 } 2035 default: 2036 printf("%s: invalid kfree 0x%x\n", sc->sc_dv.dv_xname, 2037 q->q_type); 2038 break; 2039 } 2040 } 2041 2042 static int 2043 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2044 { 2045 struct ubsec_softc *sc; 2046 int r; 2047 2048 if (krp == NULL || krp->krp_callback == NULL) 2049 return (EINVAL); 2050 #ifdef __OpenBSD__ 2051 if ((sc = ubsec_kfind(krp)) == NULL) 2052 return (EINVAL); 2053 #else 2054 sc = arg; 2055 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2056 #endif 2057 2058 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2059 struct ubsec_q2 *q; 2060 2061 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2062 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2063 ubsec_kfree(sc, q); 2064 } 2065 2066 switch (krp->krp_op) { 2067 case CRK_MOD_EXP: 2068 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2069 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2070 else 2071 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2072 break; 2073 case CRK_MOD_EXP_CRT: 2074 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2075 break; 2076 default: 2077 printf("%s: kprocess: invalid op 0x%x\n", 2078 sc->sc_dv.dv_xname, krp->krp_op); 2079 krp->krp_status = EOPNOTSUPP; 2080 crypto_kdone(krp); 2081 r = 0; 2082 } 2083 return (r); 2084 } 2085 2086 /* 2087 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2088 */ 2089 static int 2090 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2091 int hint) 2092 { 2093 struct ubsec_q2_modexp *me; 2094 struct ubsec_mcr *mcr; 2095 struct ubsec_ctx_modexp *ctx; 2096 struct ubsec_pktbuf *epb; 2097 int s, err = 0; 2098 u_int nbits, normbits, mbits, shiftbits, ebits; 2099 2100 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2101 if (me == NULL) { 2102 err = ENOMEM; 2103 goto errout; 2104 } 2105 bzero(me, sizeof *me); 2106 me->me_krp = krp; 2107 me->me_q.q_type = UBS_CTXOP_MODEXP; 2108 2109 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2110 if (nbits <= 512) 2111 normbits = 512; 2112 else if (nbits <= 768) 2113 normbits = 768; 2114 else if (nbits <= 1024) 2115 normbits = 1024; 2116 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2117 normbits = 1536; 2118 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2119 normbits = 2048; 2120 else { 2121 err = E2BIG; 2122 goto errout; 2123 } 2124 2125 shiftbits = normbits - nbits; 2126 2127 me->me_modbits = nbits; 2128 me->me_shiftbits = shiftbits; 2129 me->me_normbits = normbits; 2130 2131 /* Sanity check: result bits must be >= true modulus bits. */ 2132 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2133 err = ERANGE; 2134 goto errout; 2135 } 2136 2137 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2138 &me->me_q.q_mcr, 0)) { 2139 err = ENOMEM; 2140 goto errout; 2141 } 2142 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2143 2144 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2145 &me->me_q.q_ctx, 0)) { 2146 err = ENOMEM; 2147 goto errout; 2148 } 2149 2150 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2151 if (mbits > nbits) { 2152 err = E2BIG; 2153 goto errout; 2154 } 2155 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2156 err = ENOMEM; 2157 goto errout; 2158 } 2159 ubsec_kshift_r(shiftbits, 2160 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2161 me->me_M.dma_vaddr, normbits); 2162 2163 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2164 err = ENOMEM; 2165 goto errout; 2166 } 2167 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2168 2169 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2170 if (ebits > nbits) { 2171 err = E2BIG; 2172 goto errout; 2173 } 2174 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2175 err = ENOMEM; 2176 goto errout; 2177 } 2178 ubsec_kshift_r(shiftbits, 2179 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2180 me->me_E.dma_vaddr, normbits); 2181 2182 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2183 &me->me_epb, 0)) { 2184 err = ENOMEM; 2185 goto errout; 2186 } 2187 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2188 epb->pb_addr = htole32(me->me_E.dma_paddr); 2189 epb->pb_next = 0; 2190 epb->pb_len = htole32(normbits / 8); 2191 2192 #ifdef UBSEC_DEBUG 2193 if (ubsec_debug) { 2194 printf("Epb "); 2195 ubsec_dump_pb(epb); 2196 } 2197 #endif 2198 2199 mcr->mcr_pkts = htole16(1); 2200 mcr->mcr_flags = 0; 2201 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2202 mcr->mcr_reserved = 0; 2203 mcr->mcr_pktlen = 0; 2204 2205 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2206 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2207 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2208 2209 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2210 mcr->mcr_opktbuf.pb_next = 0; 2211 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2212 2213 #ifdef DIAGNOSTIC 2214 /* Misaligned output buffer will hang the chip. */ 2215 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2216 panic("%s: modexp invalid addr 0x%x", 2217 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_addr)); 2218 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2219 panic("%s: modexp invalid len 0x%x", 2220 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_len)); 2221 #endif 2222 2223 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2224 bzero(ctx, sizeof(*ctx)); 2225 ubsec_kshift_r(shiftbits, 2226 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2227 ctx->me_N, normbits); 2228 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2229 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2230 ctx->me_E_len = htole16(nbits); 2231 ctx->me_N_len = htole16(nbits); 2232 2233 #ifdef UBSEC_DEBUG 2234 if (ubsec_debug) { 2235 ubsec_dump_mcr(mcr); 2236 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2237 } 2238 #endif 2239 2240 /* 2241 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2242 * everything else. 2243 */ 2244 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2245 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2246 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2247 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2248 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2249 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2250 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2251 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2252 2253 /* Enqueue and we're done... */ 2254 s = splnet(); 2255 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2256 ubsec_feed2(sc); 2257 ubsecstats.hst_modexp++; 2258 splx(s); 2259 2260 return (0); 2261 2262 errout: 2263 if (me != NULL) { 2264 if (me->me_q.q_mcr.dma_map != NULL) 2265 ubsec_dma_free(sc, &me->me_q.q_mcr); 2266 if (me->me_q.q_ctx.dma_map != NULL) { 2267 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2268 ubsec_dma_free(sc, &me->me_q.q_ctx); 2269 } 2270 if (me->me_M.dma_map != NULL) { 2271 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2272 ubsec_dma_free(sc, &me->me_M); 2273 } 2274 if (me->me_E.dma_map != NULL) { 2275 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2276 ubsec_dma_free(sc, &me->me_E); 2277 } 2278 if (me->me_C.dma_map != NULL) { 2279 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2280 ubsec_dma_free(sc, &me->me_C); 2281 } 2282 if (me->me_epb.dma_map != NULL) 2283 ubsec_dma_free(sc, &me->me_epb); 2284 free(me, M_DEVBUF); 2285 } 2286 krp->krp_status = err; 2287 crypto_kdone(krp); 2288 return (0); 2289 } 2290 2291 /* 2292 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2293 */ 2294 static int 2295 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2296 int hint) 2297 { 2298 struct ubsec_q2_modexp *me; 2299 struct ubsec_mcr *mcr; 2300 struct ubsec_ctx_modexp *ctx; 2301 struct ubsec_pktbuf *epb; 2302 int s, err = 0; 2303 u_int nbits, normbits, mbits, shiftbits, ebits; 2304 2305 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2306 if (me == NULL) { 2307 err = ENOMEM; 2308 goto errout; 2309 } 2310 bzero(me, sizeof *me); 2311 me->me_krp = krp; 2312 me->me_q.q_type = UBS_CTXOP_MODEXP; 2313 2314 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2315 if (nbits <= 512) 2316 normbits = 512; 2317 else if (nbits <= 768) 2318 normbits = 768; 2319 else if (nbits <= 1024) 2320 normbits = 1024; 2321 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2322 normbits = 1536; 2323 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2324 normbits = 2048; 2325 else { 2326 err = E2BIG; 2327 goto errout; 2328 } 2329 2330 shiftbits = normbits - nbits; 2331 2332 /* XXX ??? */ 2333 me->me_modbits = nbits; 2334 me->me_shiftbits = shiftbits; 2335 me->me_normbits = normbits; 2336 2337 /* Sanity check: result bits must be >= true modulus bits. */ 2338 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2339 err = ERANGE; 2340 goto errout; 2341 } 2342 2343 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2344 &me->me_q.q_mcr, 0)) { 2345 err = ENOMEM; 2346 goto errout; 2347 } 2348 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2349 2350 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2351 &me->me_q.q_ctx, 0)) { 2352 err = ENOMEM; 2353 goto errout; 2354 } 2355 2356 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2357 if (mbits > nbits) { 2358 err = E2BIG; 2359 goto errout; 2360 } 2361 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2362 err = ENOMEM; 2363 goto errout; 2364 } 2365 bzero(me->me_M.dma_vaddr, normbits / 8); 2366 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2367 me->me_M.dma_vaddr, (mbits + 7) / 8); 2368 2369 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2370 err = ENOMEM; 2371 goto errout; 2372 } 2373 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2374 2375 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2376 if (ebits > nbits) { 2377 err = E2BIG; 2378 goto errout; 2379 } 2380 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2381 err = ENOMEM; 2382 goto errout; 2383 } 2384 bzero(me->me_E.dma_vaddr, normbits / 8); 2385 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2386 me->me_E.dma_vaddr, (ebits + 7) / 8); 2387 2388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2389 &me->me_epb, 0)) { 2390 err = ENOMEM; 2391 goto errout; 2392 } 2393 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2394 epb->pb_addr = htole32(me->me_E.dma_paddr); 2395 epb->pb_next = 0; 2396 epb->pb_len = htole32((ebits + 7) / 8); 2397 2398 #ifdef UBSEC_DEBUG 2399 if (ubsec_debug) { 2400 printf("Epb "); 2401 ubsec_dump_pb(epb); 2402 } 2403 #endif 2404 2405 mcr->mcr_pkts = htole16(1); 2406 mcr->mcr_flags = 0; 2407 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2408 mcr->mcr_reserved = 0; 2409 mcr->mcr_pktlen = 0; 2410 2411 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2412 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2413 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2414 2415 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2416 mcr->mcr_opktbuf.pb_next = 0; 2417 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2418 2419 #ifdef DIAGNOSTIC 2420 /* Misaligned output buffer will hang the chip. */ 2421 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2422 panic("%s: modexp invalid addr 0x%x", 2423 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_addr)); 2424 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2425 panic("%s: modexp invalid len 0x%x", 2426 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_len)); 2427 #endif 2428 2429 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2430 bzero(ctx, sizeof(*ctx)); 2431 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2432 (nbits + 7) / 8); 2433 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2434 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2435 ctx->me_E_len = htole16(ebits); 2436 ctx->me_N_len = htole16(nbits); 2437 2438 #ifdef UBSEC_DEBUG 2439 if (ubsec_debug) { 2440 ubsec_dump_mcr(mcr); 2441 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2442 } 2443 #endif 2444 2445 /* 2446 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2447 * everything else. 2448 */ 2449 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2450 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2451 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2452 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2453 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2454 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2455 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2456 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2457 2458 /* Enqueue and we're done... */ 2459 s = splnet(); 2460 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2461 ubsec_feed2(sc); 2462 splx(s); 2463 2464 return (0); 2465 2466 errout: 2467 if (me != NULL) { 2468 if (me->me_q.q_mcr.dma_map != NULL) 2469 ubsec_dma_free(sc, &me->me_q.q_mcr); 2470 if (me->me_q.q_ctx.dma_map != NULL) { 2471 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2472 ubsec_dma_free(sc, &me->me_q.q_ctx); 2473 } 2474 if (me->me_M.dma_map != NULL) { 2475 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2476 ubsec_dma_free(sc, &me->me_M); 2477 } 2478 if (me->me_E.dma_map != NULL) { 2479 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2480 ubsec_dma_free(sc, &me->me_E); 2481 } 2482 if (me->me_C.dma_map != NULL) { 2483 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2484 ubsec_dma_free(sc, &me->me_C); 2485 } 2486 if (me->me_epb.dma_map != NULL) 2487 ubsec_dma_free(sc, &me->me_epb); 2488 free(me, M_DEVBUF); 2489 } 2490 krp->krp_status = err; 2491 crypto_kdone(krp); 2492 return (0); 2493 } 2494 2495 static int 2496 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2497 int hint) 2498 { 2499 struct ubsec_q2_rsapriv *rp = NULL; 2500 struct ubsec_mcr *mcr; 2501 struct ubsec_ctx_rsapriv *ctx; 2502 int s, err = 0; 2503 u_int padlen, msglen; 2504 2505 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2506 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2507 if (msglen > padlen) 2508 padlen = msglen; 2509 2510 if (padlen <= 256) 2511 padlen = 256; 2512 else if (padlen <= 384) 2513 padlen = 384; 2514 else if (padlen <= 512) 2515 padlen = 512; 2516 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2517 padlen = 768; 2518 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2519 padlen = 1024; 2520 else { 2521 err = E2BIG; 2522 goto errout; 2523 } 2524 2525 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2526 err = E2BIG; 2527 goto errout; 2528 } 2529 2530 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2531 err = E2BIG; 2532 goto errout; 2533 } 2534 2535 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2536 err = E2BIG; 2537 goto errout; 2538 } 2539 2540 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2541 if (rp == NULL) 2542 return (ENOMEM); 2543 bzero(rp, sizeof *rp); 2544 rp->rpr_krp = krp; 2545 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2546 2547 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2548 &rp->rpr_q.q_mcr, 0)) { 2549 err = ENOMEM; 2550 goto errout; 2551 } 2552 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2553 2554 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2555 &rp->rpr_q.q_ctx, 0)) { 2556 err = ENOMEM; 2557 goto errout; 2558 } 2559 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2560 bzero(ctx, sizeof *ctx); 2561 2562 /* Copy in p */ 2563 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2564 &ctx->rpr_buf[0 * (padlen / 8)], 2565 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2566 2567 /* Copy in q */ 2568 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2569 &ctx->rpr_buf[1 * (padlen / 8)], 2570 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2571 2572 /* Copy in dp */ 2573 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2574 &ctx->rpr_buf[2 * (padlen / 8)], 2575 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2576 2577 /* Copy in dq */ 2578 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2579 &ctx->rpr_buf[3 * (padlen / 8)], 2580 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2581 2582 /* Copy in pinv */ 2583 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2584 &ctx->rpr_buf[4 * (padlen / 8)], 2585 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2586 2587 msglen = padlen * 2; 2588 2589 /* Copy in input message (aligned buffer/length). */ 2590 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2591 /* Is this likely? */ 2592 err = E2BIG; 2593 goto errout; 2594 } 2595 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2596 err = ENOMEM; 2597 goto errout; 2598 } 2599 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2600 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2601 rp->rpr_msgin.dma_vaddr, 2602 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2603 2604 /* Prepare space for output message (aligned buffer/length). */ 2605 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2606 /* Is this likely? */ 2607 err = E2BIG; 2608 goto errout; 2609 } 2610 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2611 err = ENOMEM; 2612 goto errout; 2613 } 2614 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2615 2616 mcr->mcr_pkts = htole16(1); 2617 mcr->mcr_flags = 0; 2618 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2619 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2620 mcr->mcr_ipktbuf.pb_next = 0; 2621 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2622 mcr->mcr_reserved = 0; 2623 mcr->mcr_pktlen = htole16(msglen); 2624 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2625 mcr->mcr_opktbuf.pb_next = 0; 2626 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2627 2628 #ifdef DIAGNOSTIC 2629 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2630 panic("%s: rsapriv: invalid msgin %p(0x%x)", 2631 sc->sc_dv.dv_xname, rp->rpr_msgin.dma_paddr, 2632 rp->rpr_msgin.dma_size); 2633 } 2634 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2635 panic("%s: rsapriv: invalid msgout %p(0x%x)", 2636 sc->sc_dv.dv_xname, rp->rpr_msgout.dma_paddr, 2637 rp->rpr_msgout.dma_size); 2638 } 2639 #endif 2640 2641 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2642 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2643 ctx->rpr_q_len = htole16(padlen); 2644 ctx->rpr_p_len = htole16(padlen); 2645 2646 /* 2647 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2648 * everything else. 2649 */ 2650 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 2651 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2652 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 2653 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2654 2655 /* Enqueue and we're done... */ 2656 s = splnet(); 2657 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2658 ubsec_feed2(sc); 2659 ubsecstats.hst_modexpcrt++; 2660 splx(s); 2661 return (0); 2662 2663 errout: 2664 if (rp != NULL) { 2665 if (rp->rpr_q.q_mcr.dma_map != NULL) 2666 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2667 if (rp->rpr_msgin.dma_map != NULL) { 2668 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2669 ubsec_dma_free(sc, &rp->rpr_msgin); 2670 } 2671 if (rp->rpr_msgout.dma_map != NULL) { 2672 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2673 ubsec_dma_free(sc, &rp->rpr_msgout); 2674 } 2675 free(rp, M_DEVBUF); 2676 } 2677 krp->krp_status = err; 2678 crypto_kdone(krp); 2679 return (0); 2680 } 2681 2682 #ifdef UBSEC_DEBUG 2683 static void 2684 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2685 { 2686 printf("addr 0x%x (0x%x) next 0x%x\n", 2687 pb->pb_addr, pb->pb_len, pb->pb_next); 2688 } 2689 2690 static void 2691 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 2692 { 2693 printf("CTX (0x%x):\n", c->ctx_len); 2694 switch (letoh16(c->ctx_op)) { 2695 case UBS_CTXOP_RNGBYPASS: 2696 case UBS_CTXOP_RNGSHA1: 2697 break; 2698 case UBS_CTXOP_MODEXP: 2699 { 2700 struct ubsec_ctx_modexp *cx = (void *)c; 2701 int i, len; 2702 2703 printf(" Elen %u, Nlen %u\n", 2704 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2705 len = (cx->me_N_len + 7)/8; 2706 for (i = 0; i < len; i++) 2707 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2708 printf("\n"); 2709 break; 2710 } 2711 default: 2712 printf("unknown context: %x\n", c->ctx_op); 2713 } 2714 printf("END CTX\n"); 2715 } 2716 2717 static void 2718 ubsec_dump_mcr(struct ubsec_mcr *mcr) 2719 { 2720 volatile struct ubsec_mcr_add *ma; 2721 int i; 2722 2723 printf("MCR:\n"); 2724 printf(" pkts: %u, flags 0x%x\n", 2725 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2726 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2727 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2728 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2729 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2730 letoh16(ma->mcr_reserved)); 2731 printf(" %d: ipkt ", i); 2732 ubsec_dump_pb(&ma->mcr_ipktbuf); 2733 printf(" %d: opkt ", i); 2734 ubsec_dump_pb(&ma->mcr_opktbuf); 2735 ma++; 2736 } 2737 printf("END MCR\n"); 2738 } 2739 #endif /* UBSEC_DEBUG */ 2740 2741 /* 2742 * Return the number of significant bits of a big number. 2743 */ 2744 static int 2745 ubsec_ksigbits(struct crparam *cr) 2746 { 2747 u_int plen = (cr->crp_nbits + 7) / 8; 2748 int i, sig = plen * 8; 2749 u_int8_t c, *p = cr->crp_p; 2750 2751 for (i = plen - 1; i >= 0; i--) { 2752 c = p[i]; 2753 if (c != 0) { 2754 while ((c & 0x80) == 0) { 2755 sig--; 2756 c <<= 1; 2757 } 2758 break; 2759 } 2760 sig -= 8; 2761 } 2762 return (sig); 2763 } 2764 2765 static void 2766 ubsec_kshift_r(shiftbits, src, srcbits, dst, dstbits) 2767 u_int shiftbits, srcbits, dstbits; 2768 u_int8_t *src, *dst; 2769 { 2770 u_int slen, dlen; 2771 int i, si, di, n; 2772 2773 slen = (srcbits + 7) / 8; 2774 dlen = (dstbits + 7) / 8; 2775 2776 for (i = 0; i < slen; i++) 2777 dst[i] = src[i]; 2778 for (i = 0; i < dlen - slen; i++) 2779 dst[slen + i] = 0; 2780 2781 n = shiftbits / 8; 2782 if (n != 0) { 2783 si = dlen - n - 1; 2784 di = dlen - 1; 2785 while (si >= 0) 2786 dst[di--] = dst[si--]; 2787 while (di >= 0) 2788 dst[di--] = 0; 2789 } 2790 2791 n = shiftbits % 8; 2792 if (n != 0) { 2793 for (i = dlen - 1; i > 0; i--) 2794 dst[i] = (dst[i] << n) | 2795 (dst[i - 1] >> (8 - n)); 2796 dst[0] = dst[0] << n; 2797 } 2798 } 2799 2800 static void 2801 ubsec_kshift_l(shiftbits, src, srcbits, dst, dstbits) 2802 u_int shiftbits, srcbits, dstbits; 2803 u_int8_t *src, *dst; 2804 { 2805 int slen, dlen, i, n; 2806 2807 slen = (srcbits + 7) / 8; 2808 dlen = (dstbits + 7) / 8; 2809 2810 n = shiftbits / 8; 2811 for (i = 0; i < slen; i++) 2812 dst[i] = src[i + n]; 2813 for (i = 0; i < dlen - slen; i++) 2814 dst[slen + i] = 0; 2815 2816 n = shiftbits % 8; 2817 if (n != 0) { 2818 for (i = 0; i < (dlen - 1); i++) 2819 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2820 dst[dlen - 1] = dst[dlen - 1] >> n; 2821 } 2822 } 2823