1 /* $NetBSD: ubsec.c,v 1.47 2019/11/10 21:16:36 chs Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.143 2009/03/27 13:31:30 reyk Exp$ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.47 2019/11/10 21:16:36 chs Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, 58xx hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #ifdef __NetBSD__ 51 #define UBSEC_NO_RNG /* hangs on attach */ 52 #define letoh16 htole16 53 #define letoh32 htole32 54 #endif 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/mbuf.h> 59 #include <sys/device.h> 60 #include <sys/module.h> 61 #include <sys/queue.h> 62 #include <sys/sysctl.h> 63 64 #include <opencrypto/cryptodev.h> 65 #include <opencrypto/xform.h> 66 #ifdef __OpenBSD__ 67 #include <dev/rndvar.h> 68 #include <sys/md5k.h> 69 #else 70 #include <sys/cprng.h> 71 #include <sys/md5.h> 72 #include <sys/rndpool.h> 73 #include <sys/rndsource.h> 74 #endif 75 #include <sys/sha1.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/ubsecreg.h> 82 #include <dev/pci/ubsecvar.h> 83 84 /* 85 * Prototypes and count for the pci_device structure 86 */ 87 static int ubsec_probe(device_t, cfdata_t, void *); 88 static void ubsec_attach(device_t, device_t, void *); 89 static int ubsec_detach(device_t, int); 90 static int ubsec_sysctl_init(void); 91 static void ubsec_reset_board(struct ubsec_softc *); 92 static void ubsec_init_board(struct ubsec_softc *); 93 static void ubsec_init_pciregs(struct pci_attach_args *pa); 94 static void ubsec_cleanchip(struct ubsec_softc *); 95 static void ubsec_totalreset(struct ubsec_softc *); 96 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 97 98 #ifdef __OpenBSD__ 99 struct cfattach ubsec_ca = { 100 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 101 }; 102 103 struct cfdriver ubsec_cd = { 104 0, "ubsec", DV_DULL 105 }; 106 #else 107 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 108 ubsec_detach, NULL); 109 extern struct cfdriver ubsec_cd; 110 #endif 111 112 /* patchable */ 113 #ifdef UBSEC_DEBUG 114 extern int ubsec_debug; 115 int ubsec_debug=1; 116 #endif 117 118 static int ubsec_intr(void *); 119 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 120 static int ubsec_freesession(void*, u_int64_t); 121 static int ubsec_process(void*, struct cryptop *, int hint); 122 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 123 static void ubsec_feed(struct ubsec_softc *); 124 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 125 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 126 static void ubsec_feed2(struct ubsec_softc *); 127 static void ubsec_feed4(struct ubsec_softc *); 128 #ifndef UBSEC_NO_RNG 129 static void ubsec_rng(void *); 130 static void ubsec_rng_locked(void *); 131 static void ubsec_rng_get(size_t, void *); 132 #endif /* UBSEC_NO_RNG */ 133 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 134 struct ubsec_dma_alloc *, int); 135 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 136 static int ubsec_dmamap_aligned(bus_dmamap_t); 137 138 static int ubsec_kprocess(void*, struct cryptkop *, int); 139 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 140 struct cryptkop *, int); 141 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 142 struct cryptkop *, int); 143 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 144 struct cryptkop *, int); 145 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 146 static int ubsec_ksigbits(struct crparam *); 147 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 148 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 149 150 #ifdef UBSEC_DEBUG 151 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 152 static void ubsec_dump_mcr(struct ubsec_mcr *); 153 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 154 #endif 155 156 #define READ_REG(sc,r) \ 157 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 158 159 #define WRITE_REG(sc,reg,val) \ 160 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 161 162 #define SWAP32(x) (x) = htole32(ntohl((x))) 163 #ifndef HTOLE32 164 #define HTOLE32(x) (x) = htole32(x) 165 #endif 166 167 struct ubsec_stats ubsecstats; 168 169 static struct sysctllog *ubsec_sysctllog; 170 171 /* 172 * ubsec_maxbatch controls the number of crypto ops to voluntarily 173 * collect into one submission to the hardware. This batching happens 174 * when ops are dispatched from the crypto subsystem with a hint that 175 * more are to follow immediately. These ops must also not be marked 176 * with a ``no delay'' flag. 177 */ 178 static int ubsec_maxbatch = 1; 179 180 /* 181 * ubsec_maxaggr controls the number of crypto ops to submit to the 182 * hardware as a unit. This aggregation reduces the number of interrupts 183 * to the host at the expense of increased latency (for all but the last 184 * operation). For network traffic setting this to one yields the highest 185 * performance but at the expense of more interrupt processing. 186 */ 187 static int ubsec_maxaggr = 1; 188 189 static const struct ubsec_product { 190 pci_vendor_id_t ubsec_vendor; 191 pci_product_id_t ubsec_product; 192 int ubsec_flags; 193 int ubsec_statmask; 194 int ubsec_maxaggr; 195 const char *ubsec_name; 196 } ubsec_products[] = { 197 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 198 0, 199 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 200 UBS_MIN_AGGR, 201 "Bluesteel 5501" 202 }, 203 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 204 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 205 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 206 UBS_MIN_AGGR, 207 "Bluesteel 5601" 208 }, 209 210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 211 0, 212 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 213 UBS_MIN_AGGR, 214 "Broadcom BCM5801" 215 }, 216 217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 218 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 219 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 220 UBS_MIN_AGGR, 221 "Broadcom BCM5802" 222 }, 223 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 225 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 226 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 227 UBS_MIN_AGGR, 228 "Broadcom BCM5805" 229 }, 230 231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 232 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 233 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 234 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 235 UBS_MIN_AGGR, 236 "Broadcom BCM5820" 237 }, 238 239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 240 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 241 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 242 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 243 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 244 UBS_MIN_AGGR, 245 "Broadcom BCM5821" 246 }, 247 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 248 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 249 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 250 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 251 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 252 UBS_MIN_AGGR, 253 "Sun Crypto Accelerator 1000" 254 }, 255 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 256 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 257 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 258 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 259 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 260 UBS_MIN_AGGR, 261 "Broadcom BCM5821 (Sun)" 262 }, 263 264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 265 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 266 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 267 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 268 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 269 UBS_MIN_AGGR, 270 "Broadcom BCM5822" 271 }, 272 273 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 274 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 275 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 276 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 277 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 278 UBS_MIN_AGGR, 279 "Broadcom BCM5823" 280 }, 281 282 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, 283 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 284 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 285 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 286 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 287 UBS_MIN_AGGR, 288 "Broadcom BCM5825" 289 }, 290 291 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, 292 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 293 UBS_FLAGS_LONGCTX | 294 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 295 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 296 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 297 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 298 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 299 UBS_MAX_AGGR, 300 "Broadcom BCM5860" 301 }, 302 303 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, 304 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 305 UBS_FLAGS_LONGCTX | 306 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 307 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 308 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 309 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 310 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 311 UBS_MAX_AGGR, 312 "Broadcom BCM5861" 313 }, 314 315 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, 316 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 317 UBS_FLAGS_LONGCTX | 318 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 319 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 320 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 321 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 322 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 323 UBS_MAX_AGGR, 324 "Broadcom BCM5862" 325 }, 326 327 { 0, 0, 328 0, 329 0, 330 0, 331 NULL 332 } 333 }; 334 335 static const struct ubsec_product * 336 ubsec_lookup(const struct pci_attach_args *pa) 337 { 338 const struct ubsec_product *up; 339 340 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 341 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 342 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 343 return (up); 344 } 345 return (NULL); 346 } 347 348 static int 349 ubsec_probe(device_t parent, cfdata_t match, void *aux) 350 { 351 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 352 353 if (ubsec_lookup(pa) != NULL) 354 return (1); 355 356 return (0); 357 } 358 359 static void 360 ubsec_attach(device_t parent, device_t self, void *aux) 361 { 362 struct ubsec_softc *sc = device_private(self); 363 struct pci_attach_args *pa = aux; 364 const struct ubsec_product *up; 365 pci_chipset_tag_t pc = pa->pa_pc; 366 pci_intr_handle_t ih; 367 const char *intrstr = NULL; 368 pcireg_t memtype; 369 struct ubsec_dma *dmap; 370 u_int32_t cmd, i; 371 char intrbuf[PCI_INTRSTR_LEN]; 372 373 sc->sc_dev = self; 374 sc->sc_pct = pc; 375 376 up = ubsec_lookup(pa); 377 if (up == NULL) { 378 printf("\n"); 379 panic("ubsec_attach: impossible"); 380 } 381 382 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 383 384 SIMPLEQ_INIT(&sc->sc_queue); 385 SIMPLEQ_INIT(&sc->sc_qchip); 386 SIMPLEQ_INIT(&sc->sc_queue2); 387 SIMPLEQ_INIT(&sc->sc_qchip2); 388 SIMPLEQ_INIT(&sc->sc_queue4); 389 SIMPLEQ_INIT(&sc->sc_qchip4); 390 SIMPLEQ_INIT(&sc->sc_q2free); 391 392 sc->sc_flags = up->ubsec_flags; 393 sc->sc_statmask = up->ubsec_statmask; 394 sc->sc_maxaggr = up->ubsec_maxaggr; 395 396 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 397 cmd |= PCI_COMMAND_MASTER_ENABLE; 398 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 399 400 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); 401 if (pci_mapreg_map(pa, BS_BAR, memtype, 0, 402 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { 403 aprint_error_dev(self, "can't find mem space"); 404 return; 405 } 406 407 sc->sc_dmat = pa->pa_dmat; 408 409 if (pci_intr_map(pa, &ih)) { 410 aprint_error_dev(self, "couldn't map interrupt\n"); 411 return; 412 } 413 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 414 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ubsec_intr, sc, 415 device_xname(self)); 416 if (sc->sc_ih == NULL) { 417 aprint_error_dev(self, "couldn't establish interrupt"); 418 if (intrstr != NULL) 419 aprint_error(" at %s", intrstr); 420 aprint_error("\n"); 421 return; 422 } 423 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 424 425 sc->sc_cid = crypto_get_driverid(0); 426 if (sc->sc_cid < 0) { 427 aprint_error_dev(self, "couldn't get crypto driver id\n"); 428 pci_intr_disestablish(pc, sc->sc_ih); 429 return; 430 } 431 432 sc->sc_rng_need = RND_POOLBITS / NBBY; 433 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 434 435 SIMPLEQ_INIT(&sc->sc_freequeue); 436 dmap = sc->sc_dmaa; 437 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 438 struct ubsec_q *q; 439 440 q = malloc(sizeof(struct ubsec_q), M_DEVBUF, M_ZERO|M_WAITOK); 441 442 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 443 &dmap->d_alloc, 0)) { 444 aprint_error_dev(self, "can't allocate dma buffers\n"); 445 free(q, M_DEVBUF); 446 break; 447 } 448 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 449 450 q->q_dma = dmap; 451 sc->sc_queuea[i] = q; 452 453 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 454 } 455 456 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 457 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 458 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 459 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 460 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 461 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 462 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 463 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 464 if (sc->sc_flags & UBS_FLAGS_AES) { 465 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 466 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 467 } 468 469 /* 470 * Reset Broadcom chip 471 */ 472 ubsec_reset_board(sc); 473 474 /* 475 * Init Broadcom specific PCI settings 476 */ 477 ubsec_init_pciregs(pa); 478 479 /* 480 * Init Broadcom chip 481 */ 482 ubsec_init_board(sc); 483 484 #ifndef UBSEC_NO_RNG 485 if (sc->sc_flags & UBS_FLAGS_RNG) { 486 if (sc->sc_flags & UBS_FLAGS_RNG4) 487 sc->sc_statmask |= BS_STAT_MCR4_DONE; 488 else 489 sc->sc_statmask |= BS_STAT_MCR2_DONE; 490 491 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 492 &sc->sc_rng.rng_q.q_mcr, 0)) 493 goto skip_rng; 494 495 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 496 &sc->sc_rng.rng_q.q_ctx, 0)) { 497 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 498 goto skip_rng; 499 } 500 501 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 502 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 503 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 504 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 505 goto skip_rng; 506 } 507 508 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 509 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 510 RND_TYPE_RNG, 511 RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 512 if (hz >= 100) 513 sc->sc_rnghz = hz / 100; 514 else 515 sc->sc_rnghz = 1; 516 #ifdef __OpenBSD__ 517 timeout_set(&sc->sc_rngto, ubsec_rng, sc); 518 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 519 #else 520 callout_init(&sc->sc_rngto, 0); 521 callout_setfunc(&sc->sc_rngto, ubsec_rng, sc); 522 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 523 #endif 524 skip_rng: 525 if (sc->sc_rnghz) 526 aprint_normal_dev(self, 527 "random number generator enabled\n"); 528 else 529 aprint_error_dev(self, 530 "WARNING: random number generator disabled\n"); 531 } 532 #endif /* UBSEC_NO_RNG */ 533 534 if (sc->sc_flags & UBS_FLAGS_KEY) { 535 sc->sc_statmask |= BS_STAT_MCR2_DONE; 536 537 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 538 ubsec_kprocess, sc); 539 #if 0 540 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 541 ubsec_kprocess, sc); 542 #endif 543 } 544 } 545 546 static int 547 ubsec_detach(device_t self, int flags) 548 { 549 struct ubsec_softc *sc = device_private(self); 550 struct ubsec_q *q, *qtmp; 551 volatile u_int32_t ctrl; 552 553 /* disable interrupts */ 554 /* XXX wait/abort current ops? where is DMAERR enabled? */ 555 ctrl = READ_REG(sc, BS_CTRL); 556 557 ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR); 558 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 559 ctrl &= ~BS_CTRL_MCR4INT; 560 561 WRITE_REG(sc, BS_CTRL, ctrl); 562 563 #ifndef UBSEC_NO_RNG 564 if (sc->sc_flags & UBS_FLAGS_RNG) { 565 callout_halt(&sc->sc_rngto, NULL); 566 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 567 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 568 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 569 rnd_detach_source(&sc->sc_rnd_source); 570 } 571 #endif /* UBSEC_NO_RNG */ 572 573 crypto_unregister_all(sc->sc_cid); 574 575 mutex_spin_enter(&sc->sc_mtx); 576 577 ubsec_totalreset(sc); /* XXX leaves the chip running */ 578 579 SIMPLEQ_FOREACH_SAFE(q, &sc->sc_freequeue, q_next, qtmp) { 580 ubsec_dma_free(sc, &q->q_dma->d_alloc); 581 if (q->q_src_map != NULL) 582 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 583 if (q->q_cached_dst_map != NULL) 584 bus_dmamap_destroy(sc->sc_dmat, q->q_cached_dst_map); 585 free(q, M_DEVBUF); 586 } 587 588 mutex_spin_exit(&sc->sc_mtx); 589 590 if (sc->sc_ih != NULL) { 591 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 592 sc->sc_ih = NULL; 593 } 594 595 if (sc->sc_memsize != 0) { 596 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_memsize); 597 sc->sc_memsize = 0; 598 } 599 600 return 0; 601 } 602 603 MODULE(MODULE_CLASS_DRIVER, ubsec, "pci,opencrypto"); 604 605 #ifdef _MODULE 606 #include "ioconf.c" 607 #endif 608 609 static int 610 ubsec_modcmd(modcmd_t cmd, void *data) 611 { 612 int error = 0; 613 614 switch (cmd) { 615 case MODULE_CMD_INIT: 616 #ifdef _MODULE 617 error = config_init_component(cfdriver_ioconf_ubsec, 618 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 619 #endif 620 if (error == 0) 621 error = ubsec_sysctl_init(); 622 return error; 623 case MODULE_CMD_FINI: 624 if (ubsec_sysctllog != NULL) 625 sysctl_teardown(&ubsec_sysctllog); 626 #ifdef _MODULE 627 error = config_fini_component(cfdriver_ioconf_ubsec, 628 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 629 #endif 630 return error; 631 default: 632 return ENOTTY; 633 } 634 } 635 636 static int 637 ubsec_sysctl_init(void) 638 { 639 const struct sysctlnode *node = NULL; 640 641 ubsec_sysctllog = NULL; 642 643 sysctl_createv(&ubsec_sysctllog, 0, NULL, &node, 644 CTLFLAG_PERMANENT, 645 CTLTYPE_NODE, "ubsec", 646 SYSCTL_DESCR("ubsec opetions"), 647 NULL, 0, NULL, 0, 648 CTL_HW, CTL_CREATE, CTL_EOL); 649 sysctl_createv(&ubsec_sysctllog, 0, &node, NULL, 650 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 651 CTLTYPE_INT, "maxbatch", 652 SYSCTL_DESCR("max ops to batch w/o interrupt"), 653 NULL, 0, &ubsec_maxbatch, 0, 654 CTL_CREATE, CTL_EOL); 655 sysctl_createv(&ubsec_sysctllog, 0, &node, NULL, 656 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 657 CTLTYPE_INT, "maxaggr", 658 SYSCTL_DESCR("max ops to aggregate under one interrupt"), 659 NULL, 0, &ubsec_maxaggr, 0, 660 CTL_CREATE, CTL_EOL); 661 662 return 0; 663 } 664 665 /* 666 * UBSEC Interrupt routine 667 */ 668 static int 669 ubsec_intr(void *arg) 670 { 671 struct ubsec_softc *sc = arg; 672 volatile u_int32_t stat; 673 struct ubsec_q *q; 674 struct ubsec_dma *dmap; 675 int flags; 676 int npkts = 0, i; 677 678 mutex_spin_enter(&sc->sc_mtx); 679 stat = READ_REG(sc, BS_STAT); 680 stat &= sc->sc_statmask; 681 if (stat == 0) { 682 mutex_spin_exit(&sc->sc_mtx); 683 return (0); 684 } 685 686 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 687 688 /* 689 * Check to see if we have any packets waiting for us 690 */ 691 if ((stat & BS_STAT_MCR1_DONE)) { 692 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 693 q = SIMPLEQ_FIRST(&sc->sc_qchip); 694 dmap = q->q_dma; 695 696 if ((dmap->d_dma->d_mcr.mcr_flags 697 & htole16(UBS_MCR_DONE)) == 0) 698 break; 699 700 q = SIMPLEQ_FIRST(&sc->sc_qchip); 701 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 702 703 npkts = q->q_nstacked_mcrs; 704 sc->sc_nqchip -= 1+npkts; 705 /* 706 * search for further sc_qchip ubsec_q's that share 707 * the same MCR, and complete them too, they must be 708 * at the top. 709 */ 710 for (i = 0; i < npkts; i++) { 711 if(q->q_stacked_mcr[i]) 712 ubsec_callback(sc, q->q_stacked_mcr[i]); 713 else 714 break; 715 } 716 ubsec_callback(sc, q); 717 } 718 719 /* 720 * Don't send any more packet to chip if there has been 721 * a DMAERR. 722 */ 723 if (!(stat & BS_STAT_DMAERR)) 724 ubsec_feed(sc); 725 } 726 727 /* 728 * Check to see if we have any key setups/rng's waiting for us 729 */ 730 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 731 (stat & BS_STAT_MCR2_DONE)) { 732 struct ubsec_q2 *q2; 733 struct ubsec_mcr *mcr; 734 735 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 736 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 737 738 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 739 0, q2->q_mcr.dma_map->dm_mapsize, 740 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 741 742 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 743 744 /* A bug in new devices requires to swap this field */ 745 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 746 flags = htole16(mcr->mcr_flags); 747 else 748 flags = mcr->mcr_flags; 749 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 750 bus_dmamap_sync(sc->sc_dmat, 751 q2->q_mcr.dma_map, 0, 752 q2->q_mcr.dma_map->dm_mapsize, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 break; 755 } 756 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 757 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 758 ubsec_callback2(sc, q2); 759 /* 760 * Don't send any more packet to chip if there has been 761 * a DMAERR. 762 */ 763 if (!(stat & BS_STAT_DMAERR)) 764 ubsec_feed2(sc); 765 } 766 } 767 if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { 768 struct ubsec_q2 *q2; 769 struct ubsec_mcr *mcr; 770 771 while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { 772 q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); 773 774 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 775 0, q2->q_mcr.dma_map->dm_mapsize, 776 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 777 778 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 779 780 /* A bug in new devices requires to swap this field */ 781 flags = htole16(mcr->mcr_flags); 782 783 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 784 bus_dmamap_sync(sc->sc_dmat, 785 q2->q_mcr.dma_map, 0, 786 q2->q_mcr.dma_map->dm_mapsize, 787 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 788 break; 789 } 790 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); 791 ubsec_callback2(sc, q2); 792 /* 793 * Don't send any more packet to chip if there has been 794 * a DMAERR. 795 */ 796 if (!(stat & BS_STAT_DMAERR)) 797 ubsec_feed4(sc); 798 } 799 } 800 801 /* 802 * Check to see if we got any DMA Error 803 */ 804 if (stat & BS_STAT_DMAERR) { 805 #ifdef UBSEC_DEBUG 806 if (ubsec_debug) { 807 volatile u_int32_t a = READ_REG(sc, BS_ERR); 808 809 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 810 (a & BS_ERR_READ) ? "read" : "write", 811 a & BS_ERR_ADDR); 812 } 813 #endif /* UBSEC_DEBUG */ 814 ubsecstats.hst_dmaerr++; 815 ubsec_totalreset(sc); 816 ubsec_feed(sc); 817 } 818 819 if (sc->sc_needwakeup) { /* XXX check high watermark */ 820 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 821 #ifdef UBSEC_DEBUG 822 if (ubsec_debug) 823 printf("%s: wakeup crypto (%x)\n", 824 device_xname(sc->sc_dev), sc->sc_needwakeup); 825 #endif /* UBSEC_DEBUG */ 826 sc->sc_needwakeup &= ~wkeup; 827 crypto_unblock(sc->sc_cid, wkeup); 828 } 829 mutex_spin_exit(&sc->sc_mtx); 830 return (1); 831 } 832 833 /* 834 * ubsec_feed() - aggregate and post requests to chip 835 * OpenBSD comments: 836 * It is assumed that the caller set splnet() 837 */ 838 static void 839 ubsec_feed(struct ubsec_softc *sc) 840 { 841 struct ubsec_q *q, *q2; 842 int npkts, i; 843 void *v; 844 u_int32_t stat; 845 #ifdef UBSEC_DEBUG 846 static int max; 847 #endif /* UBSEC_DEBUG */ 848 849 npkts = sc->sc_nqueue; 850 if (npkts > ubsecstats.hst_maxqueue) 851 ubsecstats.hst_maxqueue = npkts; 852 if (npkts < 2) 853 goto feed1; 854 855 /* 856 * Decide how many ops to combine in a single MCR. We cannot 857 * aggregate more than UBS_MAX_AGGR because this is the number 858 * of slots defined in the data structure. Otherwise we clamp 859 * based on the tunable parameter ubsec_maxaggr. Note that 860 * aggregation can happen in two ways: either by batching ops 861 * from above or because the h/w backs up and throttles us. 862 * Aggregating ops reduces the number of interrupts to the host 863 * but also (potentially) increases the latency for processing 864 * completed ops as we only get an interrupt when all aggregated 865 * ops have completed. 866 */ 867 if (npkts > sc->sc_maxaggr) 868 npkts = sc->sc_maxaggr; 869 if (npkts > ubsec_maxaggr) 870 npkts = ubsec_maxaggr; 871 if (npkts > ubsecstats.hst_maxbatch) 872 ubsecstats.hst_maxbatch = npkts; 873 if (npkts < 2) 874 goto feed1; 875 ubsecstats.hst_totbatch += npkts-1; 876 877 if ((stat = READ_REG(sc, BS_STAT)) 878 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 879 if (stat & BS_STAT_DMAERR) { 880 ubsec_totalreset(sc); 881 ubsecstats.hst_dmaerr++; 882 } else { 883 ubsecstats.hst_mcr1full++; 884 } 885 return; 886 } 887 888 #ifdef UBSEC_DEBUG 889 if (ubsec_debug) 890 printf("merging %d records\n", npkts); 891 /* XXX temporary aggregation statistics reporting code */ 892 if (max < npkts) { 893 max = npkts; 894 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), 895 max); 896 } 897 #endif /* UBSEC_DEBUG */ 898 899 q = SIMPLEQ_FIRST(&sc->sc_queue); 900 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 901 --sc->sc_nqueue; 902 903 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 904 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 905 if (q->q_dst_map != NULL) 906 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 907 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 908 909 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 910 911 for (i = 0; i < q->q_nstacked_mcrs; i++) { 912 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 913 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 914 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 915 if (q2->q_dst_map != NULL) 916 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 917 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 918 q2= SIMPLEQ_FIRST(&sc->sc_queue); 919 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 920 --sc->sc_nqueue; 921 922 v = ((void *)&q2->q_dma->d_dma->d_mcr); 923 v = (char*)v + (sizeof(struct ubsec_mcr) - 924 sizeof(struct ubsec_mcr_add)); 925 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, 926 sizeof(struct ubsec_mcr_add)); 927 q->q_stacked_mcr[i] = q2; 928 } 929 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 930 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 931 sc->sc_nqchip += npkts; 932 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 933 ubsecstats.hst_maxqchip = sc->sc_nqchip; 934 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 935 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 936 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 937 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 938 offsetof(struct ubsec_dmachunk, d_mcr)); 939 return; 940 941 feed1: 942 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 943 if ((stat = READ_REG(sc, BS_STAT)) 944 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 945 if (stat & BS_STAT_DMAERR) { 946 ubsec_totalreset(sc); 947 ubsecstats.hst_dmaerr++; 948 } else { 949 ubsecstats.hst_mcr1full++; 950 } 951 break; 952 } 953 954 q = SIMPLEQ_FIRST(&sc->sc_queue); 955 956 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 957 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 958 if (q->q_dst_map != NULL) 959 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 960 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 961 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 962 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 963 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 964 965 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 966 offsetof(struct ubsec_dmachunk, d_mcr)); 967 #ifdef UBSEC_DEBUG 968 if (ubsec_debug) 969 printf("feed: q->chip %p %08x stat %08x\n", 970 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 971 stat); 972 #endif /* UBSEC_DEBUG */ 973 q = SIMPLEQ_FIRST(&sc->sc_queue); 974 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 975 --sc->sc_nqueue; 976 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 977 sc->sc_nqchip++; 978 } 979 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 980 ubsecstats.hst_maxqchip = sc->sc_nqchip; 981 } 982 983 /* 984 * Allocate a new 'session' and return an encoded session id. 'sidp' 985 * contains our registration id, and should contain an encoded session 986 * id on successful allocation. 987 */ 988 static int 989 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 990 { 991 struct cryptoini *c, *encini = NULL, *macini = NULL; 992 struct ubsec_softc *sc; 993 struct ubsec_session *ses = NULL; 994 MD5_CTX md5ctx; 995 SHA1_CTX sha1ctx; 996 int i, sesn; 997 998 sc = arg; 999 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 1000 1001 if (sidp == NULL || cri == NULL || sc == NULL) 1002 return (EINVAL); 1003 1004 for (c = cri; c != NULL; c = c->cri_next) { 1005 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 1006 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 1007 if (macini) 1008 return (EINVAL); 1009 macini = c; 1010 } else if (c->cri_alg == CRYPTO_DES_CBC || 1011 c->cri_alg == CRYPTO_3DES_CBC || 1012 c->cri_alg == CRYPTO_AES_CBC) { 1013 if (encini) 1014 return (EINVAL); 1015 encini = c; 1016 } else 1017 return (EINVAL); 1018 } 1019 if (encini == NULL && macini == NULL) 1020 return (EINVAL); 1021 1022 if (encini && encini->cri_alg == CRYPTO_AES_CBC) { 1023 switch (encini->cri_klen) { 1024 case 128: 1025 case 192: 1026 case 256: 1027 break; 1028 default: 1029 return (EINVAL); 1030 } 1031 } 1032 1033 if (sc->sc_sessions == NULL) { 1034 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 1035 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1036 if (ses == NULL) 1037 return (ENOMEM); 1038 sesn = 0; 1039 sc->sc_nsessions = 1; 1040 } else { 1041 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 1042 if (sc->sc_sessions[sesn].ses_used == 0) { 1043 ses = &sc->sc_sessions[sesn]; 1044 break; 1045 } 1046 } 1047 1048 if (ses == NULL) { 1049 sesn = sc->sc_nsessions; 1050 ses = (struct ubsec_session *)malloc((sesn + 1) * 1051 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1052 if (ses == NULL) 1053 return (ENOMEM); 1054 memcpy(ses, sc->sc_sessions, sesn * 1055 sizeof(struct ubsec_session)); 1056 memset(sc->sc_sessions, 0, sesn * 1057 sizeof(struct ubsec_session)); 1058 free(sc->sc_sessions, M_DEVBUF); 1059 sc->sc_sessions = ses; 1060 ses = &sc->sc_sessions[sesn]; 1061 sc->sc_nsessions++; 1062 } 1063 } 1064 1065 memset(ses, 0, sizeof(struct ubsec_session)); 1066 ses->ses_used = 1; 1067 if (encini) { 1068 /* get an IV, network byte order */ 1069 #ifdef __NetBSD__ 1070 cprng_fast(ses->ses_iv, sizeof(ses->ses_iv)); 1071 #else 1072 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv)); 1073 #endif 1074 1075 /* Go ahead and compute key in ubsec's byte order */ 1076 if (encini->cri_alg == CRYPTO_AES_CBC) { 1077 memcpy(ses->ses_key, encini->cri_key, 1078 encini->cri_klen / 8); 1079 } 1080 if (encini->cri_alg == CRYPTO_DES_CBC) { 1081 memcpy(&ses->ses_key[0], encini->cri_key, 8); 1082 memcpy(&ses->ses_key[2], encini->cri_key, 8); 1083 memcpy(&ses->ses_key[4], encini->cri_key, 8); 1084 } else 1085 memcpy(ses->ses_key, encini->cri_key, 24); 1086 1087 SWAP32(ses->ses_key[0]); 1088 SWAP32(ses->ses_key[1]); 1089 SWAP32(ses->ses_key[2]); 1090 SWAP32(ses->ses_key[3]); 1091 SWAP32(ses->ses_key[4]); 1092 SWAP32(ses->ses_key[5]); 1093 } 1094 1095 if (macini) { 1096 for (i = 0; i < macini->cri_klen / 8; i++) 1097 macini->cri_key[i] ^= HMAC_IPAD_VAL; 1098 1099 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1100 MD5Init(&md5ctx); 1101 MD5Update(&md5ctx, macini->cri_key, 1102 macini->cri_klen / 8); 1103 MD5Update(&md5ctx, hmac_ipad_buffer, 1104 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1105 memcpy(ses->ses_hminner, md5ctx.state, 1106 sizeof(md5ctx.state)); 1107 } else { 1108 SHA1Init(&sha1ctx); 1109 SHA1Update(&sha1ctx, macini->cri_key, 1110 macini->cri_klen / 8); 1111 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1112 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1113 memcpy(ses->ses_hminner, sha1ctx.state, 1114 sizeof(sha1ctx.state)); 1115 } 1116 1117 for (i = 0; i < macini->cri_klen / 8; i++) 1118 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1119 1120 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1121 MD5Init(&md5ctx); 1122 MD5Update(&md5ctx, macini->cri_key, 1123 macini->cri_klen / 8); 1124 MD5Update(&md5ctx, hmac_opad_buffer, 1125 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1126 memcpy(ses->ses_hmouter, md5ctx.state, 1127 sizeof(md5ctx.state)); 1128 } else { 1129 SHA1Init(&sha1ctx); 1130 SHA1Update(&sha1ctx, macini->cri_key, 1131 macini->cri_klen / 8); 1132 SHA1Update(&sha1ctx, hmac_opad_buffer, 1133 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1134 memcpy(ses->ses_hmouter, sha1ctx.state, 1135 sizeof(sha1ctx.state)); 1136 } 1137 1138 for (i = 0; i < macini->cri_klen / 8; i++) 1139 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1140 } 1141 1142 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 1143 return (0); 1144 } 1145 1146 /* 1147 * Deallocate a session. 1148 */ 1149 static int 1150 ubsec_freesession(void *arg, u_int64_t tid) 1151 { 1152 struct ubsec_softc *sc; 1153 int session; 1154 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1155 1156 sc = arg; 1157 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 1158 1159 session = UBSEC_SESSION(sid); 1160 if (session >= sc->sc_nsessions) 1161 return (EINVAL); 1162 1163 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 1164 return (0); 1165 } 1166 1167 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 1168 static void 1169 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1170 int error) 1171 { 1172 struct ubsec_operand *op = arg; 1173 1174 KASSERT(nsegs <= UBS_MAX_SCATTER 1175 /*, ("Too many DMA segments returned when mapping operand")*/); 1176 #ifdef UBSEC_DEBUG 1177 if (ubsec_debug) 1178 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1179 (u_int) mapsize, nsegs); 1180 #endif 1181 op->mapsize = mapsize; 1182 op->nsegs = nsegs; 1183 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 1184 } 1185 #endif 1186 1187 static int 1188 ubsec_process(void *arg, struct cryptop *crp, int hint) 1189 { 1190 struct ubsec_q *q = NULL; 1191 #ifdef __OpenBSD__ 1192 int card; 1193 #endif 1194 int err = 0, i, j, nicealign; 1195 struct ubsec_softc *sc; 1196 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1197 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1198 int sskip, dskip, stheend, dtheend; 1199 int16_t coffset; 1200 struct ubsec_session *ses, key; 1201 struct ubsec_dma *dmap = NULL; 1202 u_int16_t flags = 0; 1203 int ivlen = 0, keylen = 0; 1204 1205 sc = arg; 1206 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 1207 1208 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1209 ubsecstats.hst_invalid++; 1210 return (EINVAL); 1211 } 1212 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1213 ubsecstats.hst_badsession++; 1214 return (EINVAL); 1215 } 1216 1217 mutex_spin_enter(&sc->sc_mtx); 1218 1219 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1220 ubsecstats.hst_queuefull++; 1221 sc->sc_needwakeup |= CRYPTO_SYMQ; 1222 mutex_spin_exit(&sc->sc_mtx); 1223 return(ERESTART); 1224 } 1225 1226 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1227 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 1228 mutex_spin_exit(&sc->sc_mtx); 1229 1230 dmap = q->q_dma; /* Save dma pointer */ 1231 /* don't lose the cached dmamaps q_src_map and q_cached_dst_map */ 1232 memset(q, 0, offsetof(struct ubsec_q, q_src_map)); 1233 memset(&key, 0, sizeof(key)); 1234 1235 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1236 q->q_dma = dmap; 1237 ses = &sc->sc_sessions[q->q_sesn]; 1238 1239 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1240 q->q_src_m = (struct mbuf *)crp->crp_buf; 1241 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1242 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1243 q->q_src_io = (struct uio *)crp->crp_buf; 1244 q->q_dst_io = (struct uio *)crp->crp_buf; 1245 } else { 1246 ubsecstats.hst_badflags++; 1247 err = EINVAL; 1248 goto errout; /* XXX we don't handle contiguous blocks! */ 1249 } 1250 1251 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 1252 1253 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1254 dmap->d_dma->d_mcr.mcr_flags = 0; 1255 q->q_crp = crp; 1256 1257 crd1 = crp->crp_desc; 1258 if (crd1 == NULL) { 1259 ubsecstats.hst_nodesc++; 1260 err = EINVAL; 1261 goto errout; 1262 } 1263 crd2 = crd1->crd_next; 1264 1265 if (crd2 == NULL) { 1266 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1267 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1268 maccrd = crd1; 1269 enccrd = NULL; 1270 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1271 crd1->crd_alg == CRYPTO_3DES_CBC || 1272 crd1->crd_alg == CRYPTO_AES_CBC) { 1273 maccrd = NULL; 1274 enccrd = crd1; 1275 } else { 1276 ubsecstats.hst_badalg++; 1277 err = EINVAL; 1278 goto errout; 1279 } 1280 } else { 1281 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1282 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1283 (crd2->crd_alg == CRYPTO_DES_CBC || 1284 crd2->crd_alg == CRYPTO_3DES_CBC || 1285 crd2->crd_alg == CRYPTO_AES_CBC) && 1286 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1287 maccrd = crd1; 1288 enccrd = crd2; 1289 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1290 crd1->crd_alg == CRYPTO_3DES_CBC || 1291 crd1->crd_alg == CRYPTO_AES_CBC) && 1292 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1293 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1294 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1295 enccrd = crd1; 1296 maccrd = crd2; 1297 } else { 1298 /* 1299 * We cannot order the ubsec as requested 1300 */ 1301 ubsecstats.hst_badalg++; 1302 err = EINVAL; 1303 goto errout; 1304 } 1305 } 1306 1307 if (enccrd) { 1308 if (enccrd->crd_alg == CRYPTO_AES_CBC) { 1309 if ((sc->sc_flags & UBS_FLAGS_AES) == 0) { 1310 /* 1311 * We cannot order the ubsec as requested 1312 */ 1313 ubsecstats.hst_badalg++; 1314 err = EINVAL; 1315 goto errout; 1316 } 1317 flags |= htole16(UBS_PKTCTX_ENC_AES); 1318 switch (enccrd->crd_klen) { 1319 case 128: 1320 case 192: 1321 case 256: 1322 keylen = enccrd->crd_klen / 8; 1323 break; 1324 default: 1325 err = EINVAL; 1326 goto errout; 1327 } 1328 ivlen = 16; 1329 } else { 1330 flags |= htole16(UBS_PKTCTX_ENC_3DES); 1331 ivlen = 8; 1332 keylen = 24; 1333 } 1334 1335 encoffset = enccrd->crd_skip; 1336 1337 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1338 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1339 1340 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1341 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1342 else { 1343 for (i = 0; i < (ivlen / 4); i++) 1344 key.ses_iv[i] = ses->ses_iv[i]; 1345 } 1346 1347 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1348 if (crp->crp_flags & CRYPTO_F_IMBUF) 1349 m_copyback(q->q_src_m, 1350 enccrd->crd_inject, 1351 ivlen, (void *)key.ses_iv); 1352 else if (crp->crp_flags & CRYPTO_F_IOV) 1353 cuio_copyback(q->q_src_io, 1354 enccrd->crd_inject, 1355 ivlen, (void *)key.ses_iv); 1356 } 1357 } else { 1358 flags |= htole16(UBS_PKTCTX_INBOUND); 1359 1360 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1361 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1362 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1363 m_copydata(q->q_src_m, enccrd->crd_inject, 1364 ivlen, (void *)key.ses_iv); 1365 else if (crp->crp_flags & CRYPTO_F_IOV) 1366 cuio_copydata(q->q_src_io, 1367 enccrd->crd_inject, 8, 1368 (void *)key.ses_iv); 1369 } 1370 1371 for (i = 0; i < (keylen / 4); i++) 1372 key.ses_key[i] = ses->ses_key[i]; 1373 for (i = 0; i < (ivlen / 4); i++) 1374 SWAP32(key.ses_iv[i]); 1375 } 1376 1377 if (maccrd) { 1378 macoffset = maccrd->crd_skip; 1379 1380 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1381 flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1382 else 1383 flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1384 1385 for (i = 0; i < 5; i++) { 1386 key.ses_hminner[i] = ses->ses_hminner[i]; 1387 key.ses_hmouter[i] = ses->ses_hmouter[i]; 1388 1389 HTOLE32(key.ses_hminner[i]); 1390 HTOLE32(key.ses_hmouter[i]); 1391 } 1392 } 1393 1394 if (enccrd && maccrd) { 1395 /* 1396 * ubsec cannot handle packets where the end of encryption 1397 * and authentication are not the same, or where the 1398 * encrypted part begins before the authenticated part. 1399 */ 1400 if ((encoffset + enccrd->crd_len) != 1401 (macoffset + maccrd->crd_len)) { 1402 ubsecstats.hst_lenmismatch++; 1403 err = EINVAL; 1404 goto errout; 1405 } 1406 if (enccrd->crd_skip < maccrd->crd_skip) { 1407 ubsecstats.hst_skipmismatch++; 1408 err = EINVAL; 1409 goto errout; 1410 } 1411 sskip = maccrd->crd_skip; 1412 cpskip = dskip = enccrd->crd_skip; 1413 stheend = maccrd->crd_len; 1414 dtheend = enccrd->crd_len; 1415 coffset = enccrd->crd_skip - maccrd->crd_skip; 1416 cpoffset = cpskip + dtheend; 1417 #ifdef UBSEC_DEBUG 1418 if (ubsec_debug) { 1419 printf("mac: skip %d, len %d, inject %d\n", 1420 maccrd->crd_skip, maccrd->crd_len, 1421 maccrd->crd_inject); 1422 printf("enc: skip %d, len %d, inject %d\n", 1423 enccrd->crd_skip, enccrd->crd_len, 1424 enccrd->crd_inject); 1425 printf("src: skip %d, len %d\n", sskip, stheend); 1426 printf("dst: skip %d, len %d\n", dskip, dtheend); 1427 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1428 coffset, stheend, cpskip, cpoffset); 1429 } 1430 #endif 1431 } else { 1432 cpskip = dskip = sskip = macoffset + encoffset; 1433 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1434 cpoffset = cpskip + dtheend; 1435 coffset = 0; 1436 } 1437 1438 if (q->q_src_map == NULL) { 1439 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1440 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1441 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1442 err = ENOMEM; 1443 goto errout; 1444 } 1445 } 1446 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1447 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1448 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1449 ubsecstats.hst_noload++; 1450 err = ENOMEM; 1451 goto errout; 1452 } 1453 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1454 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1455 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1456 ubsecstats.hst_noload++; 1457 err = ENOMEM; 1458 goto errout; 1459 } 1460 } 1461 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1462 1463 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1464 1465 #ifdef UBSEC_DEBUG 1466 if (ubsec_debug) 1467 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1468 #endif 1469 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1470 struct ubsec_pktbuf *pb; 1471 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1472 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1473 1474 if (sskip >= packl) { 1475 sskip -= packl; 1476 continue; 1477 } 1478 1479 packl -= sskip; 1480 packp += sskip; 1481 sskip = 0; 1482 1483 if (packl > 0xfffc) { 1484 err = EIO; 1485 goto errout; 1486 } 1487 1488 if (j == 0) 1489 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1490 else 1491 pb = &dmap->d_dma->d_sbuf[j - 1]; 1492 1493 pb->pb_addr = htole32(packp); 1494 1495 if (stheend) { 1496 if (packl > stheend) { 1497 pb->pb_len = htole32(stheend); 1498 stheend = 0; 1499 } else { 1500 pb->pb_len = htole32(packl); 1501 stheend -= packl; 1502 } 1503 } else 1504 pb->pb_len = htole32(packl); 1505 1506 if ((i + 1) == q->q_src_map->dm_nsegs) 1507 pb->pb_next = 0; 1508 else 1509 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1510 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1511 j++; 1512 } 1513 1514 if (enccrd == NULL && maccrd != NULL) { 1515 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1516 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1517 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1518 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1519 #ifdef UBSEC_DEBUG 1520 if (ubsec_debug) 1521 printf("opkt: %x %x %x\n", 1522 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1523 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1524 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1525 1526 #endif 1527 } else { 1528 if (crp->crp_flags & CRYPTO_F_IOV) { 1529 if (!nicealign) { 1530 ubsecstats.hst_iovmisaligned++; 1531 err = EINVAL; 1532 goto errout; 1533 } 1534 if (q->q_dst_map == NULL) { 1535 if (q->q_cached_dst_map == NULL) { 1536 /* 1537 * XXX: ``what the heck's that'' 1538 * 0xfff0? 1539 */ 1540 if (bus_dmamap_create(sc->sc_dmat, 1541 0xfff0, UBS_MAX_SCATTER, 0xfff0, 0, 1542 BUS_DMA_NOWAIT, 1543 &q->q_cached_dst_map) != 0) { 1544 ubsecstats.hst_nomap++; 1545 err = ENOMEM; 1546 goto errout; 1547 } 1548 } 1549 q->q_dst_map = q->q_cached_dst_map; 1550 } 1551 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1552 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1553 ubsecstats.hst_noload++; 1554 err = ENOMEM; 1555 goto errout; 1556 } 1557 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1558 if (nicealign) { 1559 q->q_dst_m = q->q_src_m; 1560 q->q_dst_map = q->q_src_map; 1561 } else { 1562 int totlen, len; 1563 struct mbuf *m, *top, **mp; 1564 1565 ubsecstats.hst_unaligned++; 1566 totlen = q->q_src_map->dm_mapsize; 1567 if (q->q_src_m->m_flags & M_PKTHDR) { 1568 len = MHLEN; 1569 MGETHDR(m, M_DONTWAIT, MT_DATA); 1570 /*XXX FIXME: m_dup_pkthdr */ 1571 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1572 m_free(m); 1573 m = NULL; 1574 } 1575 } else { 1576 len = MLEN; 1577 MGET(m, M_DONTWAIT, MT_DATA); 1578 } 1579 if (m == NULL) { 1580 ubsecstats.hst_nombuf++; 1581 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1582 goto errout; 1583 } 1584 if (len == MHLEN) 1585 /*XXX was M_DUP_PKTHDR*/ 1586 m_copy_pkthdr(m, q->q_src_m); 1587 if (totlen >= MINCLSIZE) { 1588 MCLGET(m, M_DONTWAIT); 1589 if ((m->m_flags & M_EXT) == 0) { 1590 m_free(m); 1591 ubsecstats.hst_nomcl++; 1592 err = sc->sc_nqueue 1593 ? ERESTART : ENOMEM; 1594 goto errout; 1595 } 1596 len = MCLBYTES; 1597 } 1598 m->m_len = len; 1599 top = NULL; 1600 mp = ⊤ 1601 1602 while (totlen > 0) { 1603 if (top) { 1604 MGET(m, M_DONTWAIT, MT_DATA); 1605 if (m == NULL) { 1606 m_freem(top); 1607 ubsecstats.hst_nombuf++; 1608 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1609 goto errout; 1610 } 1611 len = MLEN; 1612 } 1613 if (top && totlen >= MINCLSIZE) { 1614 MCLGET(m, M_DONTWAIT); 1615 if ((m->m_flags & M_EXT) == 0) { 1616 *mp = m; 1617 m_freem(top); 1618 ubsecstats.hst_nomcl++; 1619 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1620 goto errout; 1621 } 1622 len = MCLBYTES; 1623 } 1624 m->m_len = len = uimin(totlen, len); 1625 totlen -= len; 1626 *mp = m; 1627 mp = &m->m_next; 1628 } 1629 q->q_dst_m = top; 1630 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1631 cpskip, cpoffset); 1632 if (q->q_dst_map == NULL) { 1633 if (q->q_cached_dst_map == NULL) { 1634 /* XXX again, what the heck is that 0xfff0? */ 1635 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1636 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1637 &q->q_cached_dst_map) != 0) { 1638 ubsecstats.hst_nomap++; 1639 err = ENOMEM; 1640 goto errout; 1641 } 1642 } 1643 q->q_dst_map = q->q_cached_dst_map; 1644 } 1645 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1646 q->q_dst_map, q->q_dst_m, 1647 BUS_DMA_NOWAIT) != 0) { 1648 ubsecstats.hst_noload++; 1649 err = ENOMEM; 1650 goto errout; 1651 } 1652 } 1653 } else { 1654 ubsecstats.hst_badflags++; 1655 err = EINVAL; 1656 goto errout; 1657 } 1658 1659 #ifdef UBSEC_DEBUG 1660 if (ubsec_debug) 1661 printf("dst skip: %d\n", dskip); 1662 #endif 1663 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1664 struct ubsec_pktbuf *pb; 1665 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1666 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1667 1668 if (dskip >= packl) { 1669 dskip -= packl; 1670 continue; 1671 } 1672 1673 packl -= dskip; 1674 packp += dskip; 1675 dskip = 0; 1676 1677 if (packl > 0xfffc) { 1678 err = EIO; 1679 goto errout; 1680 } 1681 1682 if (j == 0) 1683 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1684 else 1685 pb = &dmap->d_dma->d_dbuf[j - 1]; 1686 1687 pb->pb_addr = htole32(packp); 1688 1689 if (dtheend) { 1690 if (packl > dtheend) { 1691 pb->pb_len = htole32(dtheend); 1692 dtheend = 0; 1693 } else { 1694 pb->pb_len = htole32(packl); 1695 dtheend -= packl; 1696 } 1697 } else 1698 pb->pb_len = htole32(packl); 1699 1700 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1701 if (maccrd) 1702 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1703 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1704 else 1705 pb->pb_next = 0; 1706 } else 1707 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1708 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1709 j++; 1710 } 1711 } 1712 1713 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1714 offsetof(struct ubsec_dmachunk, d_ctx)); 1715 1716 if (enccrd && enccrd->crd_alg == CRYPTO_AES_CBC) { 1717 struct ubsec_pktctx_aes128 *aes128; 1718 struct ubsec_pktctx_aes192 *aes192; 1719 struct ubsec_pktctx_aes256 *aes256; 1720 struct ubsec_pktctx_hdr *ph; 1721 u_int8_t *ctx; 1722 1723 ctx = (u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1724 offsetof(struct ubsec_dmachunk, d_ctx); 1725 1726 ph = (struct ubsec_pktctx_hdr *)ctx; 1727 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); 1728 ph->ph_flags = flags; 1729 ph->ph_offset = htole16(coffset >> 2); 1730 1731 switch (enccrd->crd_klen) { 1732 case 128: 1733 aes128 = (struct ubsec_pktctx_aes128 *)ctx; 1734 ph->ph_len = htole16(sizeof(*aes128)); 1735 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_128); 1736 for (i = 0; i < 4; i++) 1737 aes128->pc_aeskey[i] = key.ses_key[i]; 1738 for (i = 0; i < 5; i++) 1739 aes128->pc_hminner[i] = key.ses_hminner[i]; 1740 for (i = 0; i < 5; i++) 1741 aes128->pc_hmouter[i] = key.ses_hmouter[i]; 1742 for (i = 0; i < 4; i++) 1743 aes128->pc_iv[i] = key.ses_iv[i]; 1744 break; 1745 case 192: 1746 aes192 = (struct ubsec_pktctx_aes192 *)ctx; 1747 ph->ph_len = htole16(sizeof(*aes192)); 1748 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_192); 1749 for (i = 0; i < 6; i++) 1750 aes192->pc_aeskey[i] = key.ses_key[i]; 1751 for (i = 0; i < 5; i++) 1752 aes192->pc_hminner[i] = key.ses_hminner[i]; 1753 for (i = 0; i < 5; i++) 1754 aes192->pc_hmouter[i] = key.ses_hmouter[i]; 1755 for (i = 0; i < 4; i++) 1756 aes192->pc_iv[i] = key.ses_iv[i]; 1757 break; 1758 case 256: 1759 aes256 = (struct ubsec_pktctx_aes256 *)ctx; 1760 ph->ph_len = htole16(sizeof(*aes256)); 1761 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_256); 1762 for (i = 0; i < 8; i++) 1763 aes256->pc_aeskey[i] = key.ses_key[i]; 1764 for (i = 0; i < 5; i++) 1765 aes256->pc_hminner[i] = key.ses_hminner[i]; 1766 for (i = 0; i < 5; i++) 1767 aes256->pc_hmouter[i] = key.ses_hmouter[i]; 1768 for (i = 0; i < 4; i++) 1769 aes256->pc_iv[i] = key.ses_iv[i]; 1770 break; 1771 } 1772 } else if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1773 struct ubsec_pktctx_3des *ctx; 1774 struct ubsec_pktctx_hdr *ph; 1775 1776 ctx = (struct ubsec_pktctx_3des *) 1777 ((u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1778 offsetof(struct ubsec_dmachunk, d_ctx)); 1779 1780 ph = (struct ubsec_pktctx_hdr *)ctx; 1781 ph->ph_len = htole16(sizeof(*ctx)); 1782 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_3DES); 1783 ph->ph_flags = flags; 1784 ph->ph_offset = htole16(coffset >> 2); 1785 1786 for (i = 0; i < 6; i++) 1787 ctx->pc_deskey[i] = key.ses_key[i]; 1788 for (i = 0; i < 5; i++) 1789 ctx->pc_hminner[i] = key.ses_hminner[i]; 1790 for (i = 0; i < 5; i++) 1791 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1792 for (i = 0; i < 2; i++) 1793 ctx->pc_iv[i] = key.ses_iv[i]; 1794 } else { 1795 struct ubsec_pktctx *ctx = (struct ubsec_pktctx *) 1796 ((u_int8_t *)dmap->d_alloc.dma_vaddr + 1797 offsetof(struct ubsec_dmachunk, d_ctx)); 1798 1799 ctx->pc_flags = flags; 1800 ctx->pc_offset = htole16(coffset >> 2); 1801 for (i = 0; i < 6; i++) 1802 ctx->pc_deskey[i] = key.ses_key[i]; 1803 for (i = 0; i < 5; i++) 1804 ctx->pc_hminner[i] = key.ses_hminner[i]; 1805 for (i = 0; i < 5; i++) 1806 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1807 for (i = 0; i < 2; i++) 1808 ctx->pc_iv[i] = key.ses_iv[i]; 1809 } 1810 1811 mutex_spin_enter(&sc->sc_mtx); 1812 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1813 sc->sc_nqueue++; 1814 ubsecstats.hst_ipackets++; 1815 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1816 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1817 ubsec_feed(sc); 1818 mutex_spin_exit(&sc->sc_mtx); 1819 return (0); 1820 1821 errout: 1822 if (q != NULL) { 1823 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1824 m_freem(q->q_dst_m); 1825 1826 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1827 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1828 } 1829 if (q->q_src_map != NULL) { 1830 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1831 } 1832 1833 mutex_spin_enter(&sc->sc_mtx); 1834 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1835 mutex_spin_exit(&sc->sc_mtx); 1836 } 1837 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1838 if (err == EINVAL) 1839 ubsecstats.hst_invalid++; 1840 else 1841 ubsecstats.hst_nomem++; 1842 #endif 1843 if (err != ERESTART) { 1844 crp->crp_etype = err; 1845 crypto_done(crp); 1846 } else { 1847 sc->sc_needwakeup |= CRYPTO_SYMQ; 1848 } 1849 return (err); 1850 } 1851 1852 static void 1853 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1854 { 1855 struct cryptop *crp = (struct cryptop *)q->q_crp; 1856 struct cryptodesc *crd; 1857 struct ubsec_dma *dmap = q->q_dma; 1858 1859 ubsecstats.hst_opackets++; 1860 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1861 1862 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1863 dmap->d_alloc.dma_map->dm_mapsize, 1864 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1865 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1866 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1867 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1868 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1869 } 1870 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1871 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1872 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1873 1874 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1875 m_freem(q->q_src_m); 1876 crp->crp_buf = (void *)q->q_dst_m; 1877 } 1878 1879 /* copy out IV for future use */ 1880 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1881 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1882 if (crd->crd_alg != CRYPTO_DES_CBC && 1883 crd->crd_alg != CRYPTO_3DES_CBC && 1884 crd->crd_alg != CRYPTO_AES_CBC) 1885 continue; 1886 if (crp->crp_flags & CRYPTO_F_IMBUF) 1887 m_copydata((struct mbuf *)crp->crp_buf, 1888 crd->crd_skip + crd->crd_len - 8, 8, 1889 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1890 else if (crp->crp_flags & CRYPTO_F_IOV) { 1891 cuio_copydata((struct uio *)crp->crp_buf, 1892 crd->crd_skip + crd->crd_len - 8, 8, 1893 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1894 } 1895 break; 1896 } 1897 } 1898 1899 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1900 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1901 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1902 continue; 1903 if (crp->crp_flags & CRYPTO_F_IMBUF) 1904 m_copyback((struct mbuf *)crp->crp_buf, 1905 crd->crd_inject, 12, 1906 (void *)dmap->d_dma->d_macbuf); 1907 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1908 bcopy((void *)dmap->d_dma->d_macbuf, 1909 crp->crp_mac, 12); 1910 break; 1911 } 1912 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1913 crypto_done(crp); 1914 } 1915 1916 static void 1917 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1918 { 1919 int i, j, dlen, slen; 1920 char *dptr, *sptr; 1921 1922 j = 0; 1923 sptr = srcm->m_data; 1924 slen = srcm->m_len; 1925 dptr = dstm->m_data; 1926 dlen = dstm->m_len; 1927 1928 while (1) { 1929 for (i = 0; i < uimin(slen, dlen); i++) { 1930 if (j < hoffset || j >= toffset) 1931 *dptr++ = *sptr++; 1932 slen--; 1933 dlen--; 1934 j++; 1935 } 1936 if (slen == 0) { 1937 srcm = srcm->m_next; 1938 if (srcm == NULL) 1939 return; 1940 sptr = srcm->m_data; 1941 slen = srcm->m_len; 1942 } 1943 if (dlen == 0) { 1944 dstm = dstm->m_next; 1945 if (dstm == NULL) 1946 return; 1947 dptr = dstm->m_data; 1948 dlen = dstm->m_len; 1949 } 1950 } 1951 } 1952 1953 /* 1954 * feed the key generator, must be called at splnet() or higher. 1955 */ 1956 static void 1957 ubsec_feed2(struct ubsec_softc *sc) 1958 { 1959 struct ubsec_q2 *q; 1960 1961 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1962 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1963 break; 1964 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1965 1966 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1967 q->q_mcr.dma_map->dm_mapsize, 1968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1969 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1970 q->q_ctx.dma_map->dm_mapsize, 1971 BUS_DMASYNC_PREWRITE); 1972 1973 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1974 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1975 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1976 --sc->sc_nqueue2; 1977 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1978 } 1979 } 1980 1981 /* 1982 * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) 1983 */ 1984 void 1985 ubsec_feed4(struct ubsec_softc *sc) 1986 { 1987 struct ubsec_q2 *q; 1988 1989 while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { 1990 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) 1991 break; 1992 q = SIMPLEQ_FIRST(&sc->sc_queue4); 1993 1994 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1995 q->q_mcr.dma_map->dm_mapsize, 1996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1997 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1998 q->q_ctx.dma_map->dm_mapsize, 1999 BUS_DMASYNC_PREWRITE); 2000 2001 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); 2002 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); 2003 --sc->sc_nqueue4; 2004 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); 2005 } 2006 } 2007 2008 /* 2009 * Callback for handling random numbers 2010 */ 2011 static void 2012 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 2013 { 2014 struct cryptkop *krp; 2015 struct ubsec_ctx_keyop *ctx; 2016 2017 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 2018 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 2019 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2020 2021 switch (q->q_type) { 2022 #ifndef UBSEC_NO_RNG 2023 case UBS_CTXOP_RNGSHA1: 2024 case UBS_CTXOP_RNGBYPASS: { 2025 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 2026 u_int32_t *p; 2027 int i; 2028 2029 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2030 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2031 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 2032 #ifndef __NetBSD__ 2033 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) 2034 add_true_randomness(letoh32(*p)); 2035 #else 2036 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 2037 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 2038 sc->sc_rng_need -= i; 2039 #endif 2040 rng->rng_used = 0; 2041 #ifdef __OpenBSD__ 2042 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 2043 #else 2044 if (sc->sc_rng_need > 0) { 2045 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2046 } 2047 #endif 2048 break; 2049 } 2050 #endif 2051 case UBS_CTXOP_MODEXP: { 2052 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2053 u_int rlen, clen; 2054 2055 krp = me->me_krp; 2056 rlen = (me->me_modbits + 7) / 8; 2057 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 2058 2059 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2060 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2061 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2062 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2063 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2064 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2065 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2066 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2067 2068 if (clen < rlen) 2069 krp->krp_status = E2BIG; 2070 else { 2071 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 2072 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 2073 (krp->krp_param[krp->krp_iparams].crp_nbits 2074 + 7) / 8); 2075 bcopy(me->me_C.dma_vaddr, 2076 krp->krp_param[krp->krp_iparams].crp_p, 2077 (me->me_modbits + 7) / 8); 2078 } else 2079 ubsec_kshift_l(me->me_shiftbits, 2080 me->me_C.dma_vaddr, me->me_normbits, 2081 krp->krp_param[krp->krp_iparams].crp_p, 2082 krp->krp_param[krp->krp_iparams].crp_nbits); 2083 } 2084 2085 crypto_kdone(krp); 2086 2087 /* bzero all potentially sensitive data */ 2088 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2089 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2090 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2091 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2092 2093 /* Can't free here, so put us on the free list. */ 2094 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 2095 break; 2096 } 2097 case UBS_CTXOP_RSAPRIV: { 2098 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2099 u_int len; 2100 2101 krp = rp->rpr_krp; 2102 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 2103 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2104 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 2105 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2106 2107 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) 2108 / 8; 2109 bcopy(rp->rpr_msgout.dma_vaddr, 2110 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 2111 2112 crypto_kdone(krp); 2113 2114 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2115 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2116 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 2117 2118 /* Can't free here, so put us on the free list. */ 2119 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 2120 break; 2121 } 2122 default: 2123 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 2124 letoh16(ctx->ctx_op)); 2125 break; 2126 } 2127 } 2128 2129 #ifndef UBSEC_NO_RNG 2130 2131 static void 2132 ubsec_rng_get(size_t bytes, void *vsc) 2133 { 2134 struct ubsec_softc *sc = vsc; 2135 2136 mutex_spin_enter(&sc->sc_mtx); 2137 sc->sc_rng_need = bytes; 2138 ubsec_rng_locked(sc); 2139 mutex_spin_exit(&sc->sc_mtx); 2140 2141 } 2142 2143 static void 2144 ubsec_rng(void *vsc) 2145 { 2146 struct ubsec_softc *sc = vsc; 2147 mutex_spin_enter(&sc->sc_mtx); 2148 ubsec_rng_locked(sc); 2149 mutex_spin_exit(&sc->sc_mtx); 2150 } 2151 2152 static void 2153 ubsec_rng_locked(void *vsc) 2154 { 2155 struct ubsec_softc *sc = vsc; 2156 struct ubsec_q2_rng *rng = &sc->sc_rng; 2157 struct ubsec_mcr *mcr; 2158 struct ubsec_ctx_rngbypass *ctx; 2159 int *nqueue; 2160 2161 /* Caller is responsible to lock and release sc_mtx. */ 2162 KASSERT(mutex_owned(&sc->sc_mtx)); 2163 2164 if (rng->rng_used) { 2165 return; 2166 } 2167 2168 if (sc->sc_rng_need < 1) { 2169 callout_stop(&sc->sc_rngto); 2170 return; 2171 } 2172 2173 if (sc->sc_flags & UBS_FLAGS_RNG4) 2174 nqueue = &sc->sc_nqueue4; 2175 else 2176 nqueue = &sc->sc_nqueue2; 2177 2178 (*nqueue)++; 2179 if (*nqueue >= UBS_MAX_NQUEUE) 2180 goto out; 2181 2182 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 2183 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 2184 2185 mcr->mcr_pkts = htole16(1); 2186 mcr->mcr_flags = 0; 2187 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 2188 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 2189 mcr->mcr_ipktbuf.pb_len = 0; 2190 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 2191 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 2192 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 2193 UBS_PKTBUF_LEN); 2194 mcr->mcr_opktbuf.pb_next = 0; 2195 2196 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 2197 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 2198 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 2199 2200 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2201 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2202 2203 if (sc->sc_flags & UBS_FLAGS_RNG4) { 2204 SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); 2205 ubsec_feed4(sc); 2206 } else { 2207 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 2208 ubsec_feed2(sc); 2209 } 2210 rng->rng_used = 1; 2211 ubsecstats.hst_rng++; 2212 2213 return; 2214 2215 out: 2216 /* 2217 * Something weird happened, generate our own call back. 2218 */ 2219 (*nqueue)--; 2220 #ifdef __OpenBSD__ 2221 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 2222 #else 2223 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2224 #endif 2225 } 2226 #endif /* UBSEC_NO_RNG */ 2227 2228 static int 2229 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 2230 struct ubsec_dma_alloc *dma,int mapflags) 2231 { 2232 int r; 2233 2234 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 2235 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 2236 goto fail_0; 2237 2238 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 2239 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 2240 goto fail_1; 2241 2242 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2243 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 2244 goto fail_2; 2245 2246 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 2247 size, NULL, BUS_DMA_NOWAIT)) != 0) 2248 goto fail_3; 2249 2250 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 2251 dma->dma_size = size; 2252 return (0); 2253 2254 fail_3: 2255 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2256 fail_2: 2257 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2258 fail_1: 2259 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2260 fail_0: 2261 dma->dma_map = NULL; 2262 return (r); 2263 } 2264 2265 static void 2266 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 2267 { 2268 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2269 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2270 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2271 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2272 } 2273 2274 /* 2275 * Resets the board. Values in the regesters are left as is 2276 * from the reset (i.e. initial values are assigned elsewhere). 2277 */ 2278 static void 2279 ubsec_reset_board(struct ubsec_softc *sc) 2280 { 2281 volatile u_int32_t ctrl; 2282 2283 ctrl = READ_REG(sc, BS_CTRL); 2284 ctrl |= BS_CTRL_RESET; 2285 WRITE_REG(sc, BS_CTRL, ctrl); 2286 2287 /* 2288 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2289 */ 2290 DELAY(10); 2291 2292 /* Enable RNG and interrupts on newer devices */ 2293 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2294 #ifndef UBSEC_NO_RNG 2295 WRITE_REG(sc, BS_CFG, BS_CFG_RNG); 2296 #endif 2297 WRITE_REG(sc, BS_INT, BS_INT_DMAINT); 2298 } 2299 } 2300 2301 /* 2302 * Init Broadcom registers 2303 */ 2304 static void 2305 ubsec_init_board(struct ubsec_softc *sc) 2306 { 2307 u_int32_t ctrl; 2308 2309 ctrl = READ_REG(sc, BS_CTRL); 2310 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2311 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2312 2313 /* 2314 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 2315 * anyone got hw docs? 2316 */ 2317 if (sc->sc_flags & UBS_FLAGS_KEY) 2318 ctrl |= BS_CTRL_MCR2INT; 2319 else 2320 ctrl &= ~BS_CTRL_MCR2INT; 2321 2322 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2323 ctrl &= ~BS_CTRL_SWNORM; 2324 2325 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2326 ctrl |= BS_CTRL_BSIZE240; 2327 ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ 2328 2329 if (sc->sc_flags & UBS_FLAGS_RNG4) 2330 ctrl |= BS_CTRL_MCR4INT; 2331 else 2332 ctrl &= ~BS_CTRL_MCR4INT; 2333 } 2334 2335 WRITE_REG(sc, BS_CTRL, ctrl); 2336 } 2337 2338 /* 2339 * Init Broadcom PCI registers 2340 */ 2341 static void 2342 ubsec_init_pciregs(struct pci_attach_args *pa) 2343 { 2344 pci_chipset_tag_t pc = pa->pa_pc; 2345 u_int32_t misc; 2346 2347 /* 2348 * This will set the cache line size to 1, this will 2349 * force the BCM58xx chip just to do burst read/writes. 2350 * Cache line read/writes are to slow 2351 */ 2352 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 2353 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 2354 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 2355 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 2356 } 2357 2358 /* 2359 * Clean up after a chip crash. 2360 * It is assumed that the caller in splnet() 2361 */ 2362 static void 2363 ubsec_cleanchip(struct ubsec_softc *sc) 2364 { 2365 struct ubsec_q *q; 2366 2367 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2368 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2369 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 2370 ubsec_free_q(sc, q); 2371 } 2372 sc->sc_nqchip = 0; 2373 } 2374 2375 /* 2376 * free a ubsec_q 2377 * It is assumed that the caller is within splnet() 2378 */ 2379 static int 2380 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2381 { 2382 struct ubsec_q *q2; 2383 struct cryptop *crp; 2384 int npkts; 2385 int i; 2386 2387 npkts = q->q_nstacked_mcrs; 2388 2389 for (i = 0; i < npkts; i++) { 2390 if(q->q_stacked_mcr[i]) { 2391 q2 = q->q_stacked_mcr[i]; 2392 2393 if ((q2->q_dst_m != NULL) 2394 && (q2->q_src_m != q2->q_dst_m)) 2395 m_freem(q2->q_dst_m); 2396 2397 crp = (struct cryptop *)q2->q_crp; 2398 2399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2400 2401 crp->crp_etype = EFAULT; 2402 crypto_done(crp); 2403 } else { 2404 break; 2405 } 2406 } 2407 2408 /* 2409 * Free header MCR 2410 */ 2411 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2412 m_freem(q->q_dst_m); 2413 2414 crp = (struct cryptop *)q->q_crp; 2415 2416 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2417 2418 crp->crp_etype = EFAULT; 2419 crypto_done(crp); 2420 return(0); 2421 } 2422 2423 /* 2424 * Routine to reset the chip and clean up. 2425 * It is assumed that the caller is in splnet() 2426 */ 2427 static void 2428 ubsec_totalreset(struct ubsec_softc *sc) 2429 { 2430 ubsec_reset_board(sc); 2431 ubsec_init_board(sc); 2432 ubsec_cleanchip(sc); 2433 } 2434 2435 static int 2436 ubsec_dmamap_aligned(bus_dmamap_t map) 2437 { 2438 int i; 2439 2440 for (i = 0; i < map->dm_nsegs; i++) { 2441 if (map->dm_segs[i].ds_addr & 3) 2442 return (0); 2443 if ((i != (map->dm_nsegs - 1)) && 2444 (map->dm_segs[i].ds_len & 3)) 2445 return (0); 2446 } 2447 return (1); 2448 } 2449 2450 #ifdef __OpenBSD__ 2451 struct ubsec_softc * 2452 ubsec_kfind(struct cryptkop *krp) 2453 { 2454 struct ubsec_softc *sc; 2455 int i; 2456 2457 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 2458 sc = ubsec_cd.cd_devs[i]; 2459 if (sc == NULL) 2460 continue; 2461 if (sc->sc_cid == krp->krp_hid) 2462 return (sc); 2463 } 2464 return (NULL); 2465 } 2466 #endif 2467 2468 static void 2469 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2470 { 2471 switch (q->q_type) { 2472 case UBS_CTXOP_MODEXP: { 2473 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2474 2475 ubsec_dma_free(sc, &me->me_q.q_mcr); 2476 ubsec_dma_free(sc, &me->me_q.q_ctx); 2477 ubsec_dma_free(sc, &me->me_M); 2478 ubsec_dma_free(sc, &me->me_E); 2479 ubsec_dma_free(sc, &me->me_C); 2480 ubsec_dma_free(sc, &me->me_epb); 2481 free(me, M_DEVBUF); 2482 break; 2483 } 2484 case UBS_CTXOP_RSAPRIV: { 2485 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2486 2487 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2488 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2489 ubsec_dma_free(sc, &rp->rpr_msgin); 2490 ubsec_dma_free(sc, &rp->rpr_msgout); 2491 free(rp, M_DEVBUF); 2492 break; 2493 } 2494 default: 2495 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2496 q->q_type); 2497 break; 2498 } 2499 } 2500 2501 static int 2502 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2503 { 2504 struct ubsec_softc *sc; 2505 int r; 2506 2507 if (krp == NULL || krp->krp_callback == NULL) 2508 return (EINVAL); 2509 #ifdef __OpenBSD__ 2510 if ((sc = ubsec_kfind(krp)) == NULL) 2511 return (EINVAL); 2512 #else 2513 sc = arg; 2514 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2515 #endif 2516 2517 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2518 struct ubsec_q2 *q; 2519 2520 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2521 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2522 ubsec_kfree(sc, q); 2523 } 2524 2525 switch (krp->krp_op) { 2526 case CRK_MOD_EXP: 2527 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2528 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2529 else 2530 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2531 break; 2532 case CRK_MOD_EXP_CRT: 2533 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2534 break; 2535 default: 2536 printf("%s: kprocess: invalid op 0x%x\n", 2537 device_xname(sc->sc_dev), krp->krp_op); 2538 krp->krp_status = EOPNOTSUPP; 2539 crypto_kdone(krp); 2540 r = 0; 2541 } 2542 return (r); 2543 } 2544 2545 /* 2546 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2547 */ 2548 static int 2549 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2550 int hint) 2551 { 2552 struct ubsec_q2_modexp *me; 2553 struct ubsec_mcr *mcr; 2554 struct ubsec_ctx_modexp *ctx; 2555 struct ubsec_pktbuf *epb; 2556 int err = 0; 2557 u_int nbits, normbits, mbits, shiftbits, ebits; 2558 2559 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2560 if (me == NULL) { 2561 err = ENOMEM; 2562 goto errout; 2563 } 2564 memset(me, 0, sizeof *me); 2565 me->me_krp = krp; 2566 me->me_q.q_type = UBS_CTXOP_MODEXP; 2567 2568 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2569 if (nbits <= 512) 2570 normbits = 512; 2571 else if (nbits <= 768) 2572 normbits = 768; 2573 else if (nbits <= 1024) 2574 normbits = 1024; 2575 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2576 normbits = 1536; 2577 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2578 normbits = 2048; 2579 else { 2580 err = E2BIG; 2581 goto errout; 2582 } 2583 2584 shiftbits = normbits - nbits; 2585 2586 me->me_modbits = nbits; 2587 me->me_shiftbits = shiftbits; 2588 me->me_normbits = normbits; 2589 2590 /* Sanity check: result bits must be >= true modulus bits. */ 2591 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2592 err = ERANGE; 2593 goto errout; 2594 } 2595 2596 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2597 &me->me_q.q_mcr, 0)) { 2598 err = ENOMEM; 2599 goto errout; 2600 } 2601 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2602 2603 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2604 &me->me_q.q_ctx, 0)) { 2605 err = ENOMEM; 2606 goto errout; 2607 } 2608 2609 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2610 if (mbits > nbits) { 2611 err = E2BIG; 2612 goto errout; 2613 } 2614 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2615 err = ENOMEM; 2616 goto errout; 2617 } 2618 ubsec_kshift_r(shiftbits, 2619 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2620 me->me_M.dma_vaddr, normbits); 2621 2622 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2623 err = ENOMEM; 2624 goto errout; 2625 } 2626 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2627 2628 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2629 if (ebits > nbits) { 2630 err = E2BIG; 2631 goto errout; 2632 } 2633 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2634 err = ENOMEM; 2635 goto errout; 2636 } 2637 ubsec_kshift_r(shiftbits, 2638 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2639 me->me_E.dma_vaddr, normbits); 2640 2641 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2642 &me->me_epb, 0)) { 2643 err = ENOMEM; 2644 goto errout; 2645 } 2646 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2647 epb->pb_addr = htole32(me->me_E.dma_paddr); 2648 epb->pb_next = 0; 2649 epb->pb_len = htole32(normbits / 8); 2650 2651 #ifdef UBSEC_DEBUG 2652 if (ubsec_debug) { 2653 printf("Epb "); 2654 ubsec_dump_pb(epb); 2655 } 2656 #endif 2657 2658 mcr->mcr_pkts = htole16(1); 2659 mcr->mcr_flags = 0; 2660 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2661 mcr->mcr_reserved = 0; 2662 mcr->mcr_pktlen = 0; 2663 2664 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2665 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2666 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2667 2668 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2669 mcr->mcr_opktbuf.pb_next = 0; 2670 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2671 2672 #ifdef DIAGNOSTIC 2673 /* Misaligned output buffer will hang the chip. */ 2674 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2675 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2676 letoh32(mcr->mcr_opktbuf.pb_addr)); 2677 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2678 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2679 letoh32(mcr->mcr_opktbuf.pb_len)); 2680 #endif 2681 2682 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2683 memset(ctx, 0, sizeof(*ctx)); 2684 ubsec_kshift_r(shiftbits, 2685 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2686 ctx->me_N, normbits); 2687 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2688 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2689 ctx->me_E_len = htole16(nbits); 2690 ctx->me_N_len = htole16(nbits); 2691 2692 #ifdef UBSEC_DEBUG 2693 if (ubsec_debug) { 2694 ubsec_dump_mcr(mcr); 2695 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2696 } 2697 #endif 2698 2699 /* 2700 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2701 * everything else. 2702 */ 2703 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2704 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2705 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2706 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2707 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2708 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2709 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2710 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2711 2712 /* Enqueue and we're done... */ 2713 mutex_spin_enter(&sc->sc_mtx); 2714 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2715 ubsec_feed2(sc); 2716 ubsecstats.hst_modexp++; 2717 mutex_spin_exit(&sc->sc_mtx); 2718 2719 return (0); 2720 2721 errout: 2722 if (me != NULL) { 2723 if (me->me_q.q_mcr.dma_map != NULL) 2724 ubsec_dma_free(sc, &me->me_q.q_mcr); 2725 if (me->me_q.q_ctx.dma_map != NULL) { 2726 memset(me->me_q.q_ctx.dma_vaddr, 0, 2727 me->me_q.q_ctx.dma_size); 2728 ubsec_dma_free(sc, &me->me_q.q_ctx); 2729 } 2730 if (me->me_M.dma_map != NULL) { 2731 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2732 ubsec_dma_free(sc, &me->me_M); 2733 } 2734 if (me->me_E.dma_map != NULL) { 2735 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2736 ubsec_dma_free(sc, &me->me_E); 2737 } 2738 if (me->me_C.dma_map != NULL) { 2739 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2740 ubsec_dma_free(sc, &me->me_C); 2741 } 2742 if (me->me_epb.dma_map != NULL) 2743 ubsec_dma_free(sc, &me->me_epb); 2744 free(me, M_DEVBUF); 2745 } 2746 krp->krp_status = err; 2747 crypto_kdone(krp); 2748 return (0); 2749 } 2750 2751 /* 2752 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2753 */ 2754 static int 2755 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2756 int hint) 2757 { 2758 struct ubsec_q2_modexp *me; 2759 struct ubsec_mcr *mcr; 2760 struct ubsec_ctx_modexp *ctx; 2761 struct ubsec_pktbuf *epb; 2762 int err = 0; 2763 u_int nbits, normbits, mbits, shiftbits, ebits; 2764 2765 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2766 if (me == NULL) { 2767 err = ENOMEM; 2768 goto errout; 2769 } 2770 memset(me, 0, sizeof *me); 2771 me->me_krp = krp; 2772 me->me_q.q_type = UBS_CTXOP_MODEXP; 2773 2774 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2775 if (nbits <= 512) 2776 normbits = 512; 2777 else if (nbits <= 768) 2778 normbits = 768; 2779 else if (nbits <= 1024) 2780 normbits = 1024; 2781 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2782 normbits = 1536; 2783 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2784 normbits = 2048; 2785 else { 2786 err = E2BIG; 2787 goto errout; 2788 } 2789 2790 shiftbits = normbits - nbits; 2791 2792 /* XXX ??? */ 2793 me->me_modbits = nbits; 2794 me->me_shiftbits = shiftbits; 2795 me->me_normbits = normbits; 2796 2797 /* Sanity check: result bits must be >= true modulus bits. */ 2798 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2799 err = ERANGE; 2800 goto errout; 2801 } 2802 2803 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2804 &me->me_q.q_mcr, 0)) { 2805 err = ENOMEM; 2806 goto errout; 2807 } 2808 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2809 2810 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2811 &me->me_q.q_ctx, 0)) { 2812 err = ENOMEM; 2813 goto errout; 2814 } 2815 2816 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2817 if (mbits > nbits) { 2818 err = E2BIG; 2819 goto errout; 2820 } 2821 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2822 err = ENOMEM; 2823 goto errout; 2824 } 2825 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2826 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2827 me->me_M.dma_vaddr, (mbits + 7) / 8); 2828 2829 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2830 err = ENOMEM; 2831 goto errout; 2832 } 2833 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2834 2835 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2836 if (ebits > nbits) { 2837 err = E2BIG; 2838 goto errout; 2839 } 2840 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2841 err = ENOMEM; 2842 goto errout; 2843 } 2844 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2845 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2846 me->me_E.dma_vaddr, (ebits + 7) / 8); 2847 2848 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2849 &me->me_epb, 0)) { 2850 err = ENOMEM; 2851 goto errout; 2852 } 2853 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2854 epb->pb_addr = htole32(me->me_E.dma_paddr); 2855 epb->pb_next = 0; 2856 epb->pb_len = htole32((ebits + 7) / 8); 2857 2858 #ifdef UBSEC_DEBUG 2859 if (ubsec_debug) { 2860 printf("Epb "); 2861 ubsec_dump_pb(epb); 2862 } 2863 #endif 2864 2865 mcr->mcr_pkts = htole16(1); 2866 mcr->mcr_flags = 0; 2867 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2868 mcr->mcr_reserved = 0; 2869 mcr->mcr_pktlen = 0; 2870 2871 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2872 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2873 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2874 2875 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2876 mcr->mcr_opktbuf.pb_next = 0; 2877 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2878 2879 #ifdef DIAGNOSTIC 2880 /* Misaligned output buffer will hang the chip. */ 2881 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2882 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2883 letoh32(mcr->mcr_opktbuf.pb_addr)); 2884 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2885 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2886 letoh32(mcr->mcr_opktbuf.pb_len)); 2887 #endif 2888 2889 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2890 memset(ctx, 0, sizeof(*ctx)); 2891 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2892 (nbits + 7) / 8); 2893 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2894 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2895 ctx->me_E_len = htole16(ebits); 2896 ctx->me_N_len = htole16(nbits); 2897 2898 #ifdef UBSEC_DEBUG 2899 if (ubsec_debug) { 2900 ubsec_dump_mcr(mcr); 2901 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2902 } 2903 #endif 2904 2905 /* 2906 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2907 * everything else. 2908 */ 2909 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2910 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2911 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2912 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2913 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2914 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2915 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2916 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2917 2918 /* Enqueue and we're done... */ 2919 mutex_spin_enter(&sc->sc_mtx); 2920 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2921 ubsec_feed2(sc); 2922 mutex_spin_exit(&sc->sc_mtx); 2923 2924 return (0); 2925 2926 errout: 2927 if (me != NULL) { 2928 if (me->me_q.q_mcr.dma_map != NULL) 2929 ubsec_dma_free(sc, &me->me_q.q_mcr); 2930 if (me->me_q.q_ctx.dma_map != NULL) { 2931 memset(me->me_q.q_ctx.dma_vaddr, 0, 2932 me->me_q.q_ctx.dma_size); 2933 ubsec_dma_free(sc, &me->me_q.q_ctx); 2934 } 2935 if (me->me_M.dma_map != NULL) { 2936 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2937 ubsec_dma_free(sc, &me->me_M); 2938 } 2939 if (me->me_E.dma_map != NULL) { 2940 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2941 ubsec_dma_free(sc, &me->me_E); 2942 } 2943 if (me->me_C.dma_map != NULL) { 2944 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2945 ubsec_dma_free(sc, &me->me_C); 2946 } 2947 if (me->me_epb.dma_map != NULL) 2948 ubsec_dma_free(sc, &me->me_epb); 2949 free(me, M_DEVBUF); 2950 } 2951 krp->krp_status = err; 2952 crypto_kdone(krp); 2953 return (0); 2954 } 2955 2956 static int 2957 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2958 int hint) 2959 { 2960 struct ubsec_q2_rsapriv *rp = NULL; 2961 struct ubsec_mcr *mcr; 2962 struct ubsec_ctx_rsapriv *ctx; 2963 int err = 0; 2964 u_int padlen, msglen; 2965 2966 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2967 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2968 if (msglen > padlen) 2969 padlen = msglen; 2970 2971 if (padlen <= 256) 2972 padlen = 256; 2973 else if (padlen <= 384) 2974 padlen = 384; 2975 else if (padlen <= 512) 2976 padlen = 512; 2977 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2978 padlen = 768; 2979 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2980 padlen = 1024; 2981 else { 2982 err = E2BIG; 2983 goto errout; 2984 } 2985 2986 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2987 err = E2BIG; 2988 goto errout; 2989 } 2990 2991 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2992 err = E2BIG; 2993 goto errout; 2994 } 2995 2996 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2997 err = E2BIG; 2998 goto errout; 2999 } 3000 3001 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 3002 if (rp == NULL) 3003 return (ENOMEM); 3004 rp->rpr_krp = krp; 3005 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 3006 3007 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 3008 &rp->rpr_q.q_mcr, 0)) { 3009 err = ENOMEM; 3010 goto errout; 3011 } 3012 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 3013 3014 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 3015 &rp->rpr_q.q_ctx, 0)) { 3016 err = ENOMEM; 3017 goto errout; 3018 } 3019 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 3020 memset(ctx, 0, sizeof *ctx); 3021 3022 /* Copy in p */ 3023 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 3024 &ctx->rpr_buf[0 * (padlen / 8)], 3025 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 3026 3027 /* Copy in q */ 3028 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 3029 &ctx->rpr_buf[1 * (padlen / 8)], 3030 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 3031 3032 /* Copy in dp */ 3033 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 3034 &ctx->rpr_buf[2 * (padlen / 8)], 3035 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 3036 3037 /* Copy in dq */ 3038 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 3039 &ctx->rpr_buf[3 * (padlen / 8)], 3040 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 3041 3042 /* Copy in pinv */ 3043 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 3044 &ctx->rpr_buf[4 * (padlen / 8)], 3045 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 3046 3047 msglen = padlen * 2; 3048 3049 /* Copy in input message (aligned buffer/length). */ 3050 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 3051 /* Is this likely? */ 3052 err = E2BIG; 3053 goto errout; 3054 } 3055 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 3056 err = ENOMEM; 3057 goto errout; 3058 } 3059 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 3060 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 3061 rp->rpr_msgin.dma_vaddr, 3062 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 3063 3064 /* Prepare space for output message (aligned buffer/length). */ 3065 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 3066 /* Is this likely? */ 3067 err = E2BIG; 3068 goto errout; 3069 } 3070 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 3071 err = ENOMEM; 3072 goto errout; 3073 } 3074 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 3075 3076 mcr->mcr_pkts = htole16(1); 3077 mcr->mcr_flags = 0; 3078 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 3079 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 3080 mcr->mcr_ipktbuf.pb_next = 0; 3081 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 3082 mcr->mcr_reserved = 0; 3083 mcr->mcr_pktlen = htole16(msglen); 3084 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 3085 mcr->mcr_opktbuf.pb_next = 0; 3086 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 3087 3088 #ifdef DIAGNOSTIC 3089 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 3090 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 3091 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 3092 (u_long) rp->rpr_msgin.dma_size); 3093 } 3094 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 3095 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 3096 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 3097 (u_long) rp->rpr_msgout.dma_size); 3098 } 3099 #endif 3100 3101 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 3102 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 3103 ctx->rpr_q_len = htole16(padlen); 3104 ctx->rpr_p_len = htole16(padlen); 3105 3106 /* 3107 * ubsec_feed2 will sync mcr and ctx, we just need to sync 3108 * everything else. 3109 */ 3110 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 3111 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3112 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 3113 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 3114 3115 /* Enqueue and we're done... */ 3116 mutex_spin_enter(&sc->sc_mtx); 3117 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 3118 ubsec_feed2(sc); 3119 ubsecstats.hst_modexpcrt++; 3120 mutex_spin_exit(&sc->sc_mtx); 3121 return (0); 3122 3123 errout: 3124 if (rp != NULL) { 3125 if (rp->rpr_q.q_mcr.dma_map != NULL) 3126 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 3127 if (rp->rpr_msgin.dma_map != NULL) { 3128 memset(rp->rpr_msgin.dma_vaddr, 0, 3129 rp->rpr_msgin.dma_size); 3130 ubsec_dma_free(sc, &rp->rpr_msgin); 3131 } 3132 if (rp->rpr_msgout.dma_map != NULL) { 3133 memset(rp->rpr_msgout.dma_vaddr, 0, 3134 rp->rpr_msgout.dma_size); 3135 ubsec_dma_free(sc, &rp->rpr_msgout); 3136 } 3137 free(rp, M_DEVBUF); 3138 } 3139 krp->krp_status = err; 3140 crypto_kdone(krp); 3141 return (0); 3142 } 3143 3144 #ifdef UBSEC_DEBUG 3145 static void 3146 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 3147 { 3148 printf("addr 0x%x (0x%x) next 0x%x\n", 3149 pb->pb_addr, pb->pb_len, pb->pb_next); 3150 } 3151 3152 static void 3153 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 3154 { 3155 printf("CTX (0x%x):\n", c->ctx_len); 3156 switch (letoh16(c->ctx_op)) { 3157 case UBS_CTXOP_RNGBYPASS: 3158 case UBS_CTXOP_RNGSHA1: 3159 break; 3160 case UBS_CTXOP_MODEXP: 3161 { 3162 struct ubsec_ctx_modexp *cx = (void *)c; 3163 int i, len; 3164 3165 printf(" Elen %u, Nlen %u\n", 3166 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 3167 len = (cx->me_N_len + 7)/8; 3168 for (i = 0; i < len; i++) 3169 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 3170 printf("\n"); 3171 break; 3172 } 3173 default: 3174 printf("unknown context: %x\n", c->ctx_op); 3175 } 3176 printf("END CTX\n"); 3177 } 3178 3179 static void 3180 ubsec_dump_mcr(struct ubsec_mcr *mcr) 3181 { 3182 volatile struct ubsec_mcr_add *ma; 3183 int i; 3184 3185 printf("MCR:\n"); 3186 printf(" pkts: %u, flags 0x%x\n", 3187 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 3188 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 3189 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 3190 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 3191 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 3192 letoh16(ma->mcr_reserved)); 3193 printf(" %d: ipkt ", i); 3194 ubsec_dump_pb(&ma->mcr_ipktbuf); 3195 printf(" %d: opkt ", i); 3196 ubsec_dump_pb(&ma->mcr_opktbuf); 3197 ma++; 3198 } 3199 printf("END MCR\n"); 3200 } 3201 #endif /* UBSEC_DEBUG */ 3202 3203 /* 3204 * Return the number of significant bits of a big number. 3205 */ 3206 static int 3207 ubsec_ksigbits(struct crparam *cr) 3208 { 3209 u_int plen = (cr->crp_nbits + 7) / 8; 3210 int i, sig = plen * 8; 3211 u_int8_t c, *p = cr->crp_p; 3212 3213 for (i = plen - 1; i >= 0; i--) { 3214 c = p[i]; 3215 if (c != 0) { 3216 while ((c & 0x80) == 0) { 3217 sig--; 3218 c <<= 1; 3219 } 3220 break; 3221 } 3222 sig -= 8; 3223 } 3224 return (sig); 3225 } 3226 3227 static void 3228 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 3229 u_int8_t *dst, u_int dstbits) 3230 { 3231 u_int slen, dlen; 3232 int i, si, di, n; 3233 3234 slen = (srcbits + 7) / 8; 3235 dlen = (dstbits + 7) / 8; 3236 3237 for (i = 0; i < slen; i++) 3238 dst[i] = src[i]; 3239 for (i = 0; i < dlen - slen; i++) 3240 dst[slen + i] = 0; 3241 3242 n = shiftbits / 8; 3243 if (n != 0) { 3244 si = dlen - n - 1; 3245 di = dlen - 1; 3246 while (si >= 0) 3247 dst[di--] = dst[si--]; 3248 while (di >= 0) 3249 dst[di--] = 0; 3250 } 3251 3252 n = shiftbits % 8; 3253 if (n != 0) { 3254 for (i = dlen - 1; i > 0; i--) 3255 dst[i] = (dst[i] << n) | 3256 (dst[i - 1] >> (8 - n)); 3257 dst[0] = dst[0] << n; 3258 } 3259 } 3260 3261 static void 3262 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 3263 u_int8_t *dst, u_int dstbits) 3264 { 3265 int slen, dlen, i, n; 3266 3267 slen = (srcbits + 7) / 8; 3268 dlen = (dstbits + 7) / 8; 3269 3270 n = shiftbits / 8; 3271 for (i = 0; i < slen; i++) 3272 dst[i] = src[i + n]; 3273 for (i = 0; i < dlen - slen; i++) 3274 dst[slen + i] = 0; 3275 3276 n = shiftbits % 8; 3277 if (n != 0) { 3278 for (i = 0; i < (dlen - 1); i++) 3279 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 3280 dst[dlen - 1] = dst[dlen - 1] >> n; 3281 } 3282 } 3283