1 /* $NetBSD: ubsec.c,v 1.52 2020/06/14 23:22:09 riastradh Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.143 2009/03/27 13:31:30 reyk Exp$ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.52 2020/06/14 23:22:09 riastradh Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, 58xx hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/mbuf.h> 54 #include <sys/device.h> 55 #include <sys/module.h> 56 #include <sys/queue.h> 57 #include <sys/sysctl.h> 58 59 #include <opencrypto/cryptodev.h> 60 #include <opencrypto/xform.h> 61 #include <sys/cprng.h> 62 #include <sys/md5.h> 63 #include <sys/rndsource.h> 64 #include <sys/sha1.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/pci/ubsecreg.h> 71 #include <dev/pci/ubsecvar.h> 72 73 #define UBSEC_NO_RNG /* hangs on attach */ 74 #define letoh16 htole16 75 #define letoh32 htole32 76 77 /* 78 * Prototypes and count for the pci_device structure 79 */ 80 static int ubsec_probe(device_t, cfdata_t, void *); 81 static void ubsec_attach(device_t, device_t, void *); 82 static int ubsec_detach(device_t, int); 83 static void ubsec_reset_board(struct ubsec_softc *); 84 static void ubsec_init_board(struct ubsec_softc *); 85 static void ubsec_init_pciregs(struct pci_attach_args *pa); 86 static void ubsec_cleanchip(struct ubsec_softc *); 87 static void ubsec_totalreset(struct ubsec_softc *); 88 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 89 90 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 91 ubsec_detach, NULL); 92 extern struct cfdriver ubsec_cd; 93 94 /* patchable */ 95 #ifdef UBSEC_DEBUG 96 extern int ubsec_debug; 97 int ubsec_debug=1; 98 #endif 99 100 static int ubsec_intr(void *); 101 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 102 static int ubsec_freesession(void*, u_int64_t); 103 static int ubsec_process(void*, struct cryptop *, int hint); 104 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 105 static void ubsec_feed(struct ubsec_softc *); 106 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 107 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 108 static void ubsec_feed2(struct ubsec_softc *); 109 static void ubsec_feed4(struct ubsec_softc *); 110 #ifndef UBSEC_NO_RNG 111 static void ubsec_rng(void *); 112 static void ubsec_rng_locked(void *); 113 static void ubsec_rng_get(size_t, void *); 114 #endif /* UBSEC_NO_RNG */ 115 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 116 struct ubsec_dma_alloc *, int); 117 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 118 static int ubsec_dmamap_aligned(bus_dmamap_t); 119 120 static int ubsec_kprocess(void*, struct cryptkop *, int); 121 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 122 struct cryptkop *, int); 123 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 124 struct cryptkop *, int); 125 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 126 struct cryptkop *, int); 127 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 128 static int ubsec_ksigbits(struct crparam *); 129 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 130 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 131 132 #ifdef UBSEC_DEBUG 133 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 134 static void ubsec_dump_mcr(struct ubsec_mcr *); 135 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 136 #endif 137 138 #define READ_REG(sc,r) \ 139 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 140 141 #define WRITE_REG(sc,reg,val) \ 142 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 143 144 #define SWAP32(x) (x) = htole32(ntohl((x))) 145 #ifndef HTOLE32 146 #define HTOLE32(x) (x) = htole32(x) 147 #endif 148 149 struct ubsec_stats ubsecstats; 150 151 /* 152 * ubsec_maxbatch controls the number of crypto ops to voluntarily 153 * collect into one submission to the hardware. This batching happens 154 * when ops are dispatched from the crypto subsystem with a hint that 155 * more are to follow immediately. These ops must also not be marked 156 * with a ``no delay'' flag. 157 */ 158 static int ubsec_maxbatch = 1; 159 160 /* 161 * ubsec_maxaggr controls the number of crypto ops to submit to the 162 * hardware as a unit. This aggregation reduces the number of interrupts 163 * to the host at the expense of increased latency (for all but the last 164 * operation). For network traffic setting this to one yields the highest 165 * performance but at the expense of more interrupt processing. 166 */ 167 static int ubsec_maxaggr = 1; 168 169 static const struct ubsec_product { 170 pci_vendor_id_t ubsec_vendor; 171 pci_product_id_t ubsec_product; 172 int ubsec_flags; 173 int ubsec_statmask; 174 int ubsec_maxaggr; 175 const char *ubsec_name; 176 } ubsec_products[] = { 177 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 178 0, 179 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 180 UBS_MIN_AGGR, 181 "Bluesteel 5501" 182 }, 183 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 184 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 185 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 186 UBS_MIN_AGGR, 187 "Bluesteel 5601" 188 }, 189 190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 191 0, 192 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 193 UBS_MIN_AGGR, 194 "Broadcom BCM5801" 195 }, 196 197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 198 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 199 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 200 UBS_MIN_AGGR, 201 "Broadcom BCM5802" 202 }, 203 204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 205 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 206 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 207 UBS_MIN_AGGR, 208 "Broadcom BCM5805" 209 }, 210 211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 212 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 213 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 214 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 215 UBS_MIN_AGGR, 216 "Broadcom BCM5820" 217 }, 218 219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 220 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 221 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 222 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 223 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 224 UBS_MIN_AGGR, 225 "Broadcom BCM5821" 226 }, 227 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 228 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 229 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 230 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 231 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 232 UBS_MIN_AGGR, 233 "Sun Crypto Accelerator 1000" 234 }, 235 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 236 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 237 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 238 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 239 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 240 UBS_MIN_AGGR, 241 "Broadcom BCM5821 (Sun)" 242 }, 243 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 245 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 246 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 247 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 248 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 249 UBS_MIN_AGGR, 250 "Broadcom BCM5822" 251 }, 252 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 254 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 255 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 256 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 257 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 258 UBS_MIN_AGGR, 259 "Broadcom BCM5823" 260 }, 261 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, 263 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 264 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 265 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 266 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 267 UBS_MIN_AGGR, 268 "Broadcom BCM5825" 269 }, 270 271 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, 272 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 273 UBS_FLAGS_LONGCTX | 274 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 275 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 276 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 277 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 278 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 279 UBS_MAX_AGGR, 280 "Broadcom BCM5860" 281 }, 282 283 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, 284 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 285 UBS_FLAGS_LONGCTX | 286 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 287 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 288 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 289 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 290 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 291 UBS_MAX_AGGR, 292 "Broadcom BCM5861" 293 }, 294 295 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, 296 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 297 UBS_FLAGS_LONGCTX | 298 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 299 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 300 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 301 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 302 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 303 UBS_MAX_AGGR, 304 "Broadcom BCM5862" 305 }, 306 307 { 0, 0, 308 0, 309 0, 310 0, 311 NULL 312 } 313 }; 314 315 static const struct ubsec_product * 316 ubsec_lookup(const struct pci_attach_args *pa) 317 { 318 const struct ubsec_product *up; 319 320 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 321 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 322 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 323 return (up); 324 } 325 return (NULL); 326 } 327 328 static int 329 ubsec_probe(device_t parent, cfdata_t match, void *aux) 330 { 331 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 332 333 if (ubsec_lookup(pa) != NULL) 334 return (1); 335 336 return (0); 337 } 338 339 static void 340 ubsec_attach(device_t parent, device_t self, void *aux) 341 { 342 struct ubsec_softc *sc = device_private(self); 343 struct pci_attach_args *pa = aux; 344 const struct ubsec_product *up; 345 pci_chipset_tag_t pc = pa->pa_pc; 346 pci_intr_handle_t ih; 347 const char *intrstr = NULL; 348 pcireg_t memtype; 349 struct ubsec_dma *dmap; 350 u_int32_t cmd, i; 351 char intrbuf[PCI_INTRSTR_LEN]; 352 353 sc->sc_dev = self; 354 sc->sc_pct = pc; 355 356 up = ubsec_lookup(pa); 357 if (up == NULL) { 358 printf("\n"); 359 panic("ubsec_attach: impossible"); 360 } 361 362 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 363 364 SIMPLEQ_INIT(&sc->sc_queue); 365 SIMPLEQ_INIT(&sc->sc_qchip); 366 SIMPLEQ_INIT(&sc->sc_queue2); 367 SIMPLEQ_INIT(&sc->sc_qchip2); 368 SIMPLEQ_INIT(&sc->sc_queue4); 369 SIMPLEQ_INIT(&sc->sc_qchip4); 370 SIMPLEQ_INIT(&sc->sc_q2free); 371 372 sc->sc_flags = up->ubsec_flags; 373 sc->sc_statmask = up->ubsec_statmask; 374 sc->sc_maxaggr = up->ubsec_maxaggr; 375 376 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 377 cmd |= PCI_COMMAND_MASTER_ENABLE; 378 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 379 380 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); 381 if (pci_mapreg_map(pa, BS_BAR, memtype, 0, 382 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { 383 aprint_error_dev(self, "can't find mem space"); 384 return; 385 } 386 387 sc->sc_dmat = pa->pa_dmat; 388 389 if (pci_intr_map(pa, &ih)) { 390 aprint_error_dev(self, "couldn't map interrupt\n"); 391 return; 392 } 393 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 394 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ubsec_intr, sc, 395 device_xname(self)); 396 if (sc->sc_ih == NULL) { 397 aprint_error_dev(self, "couldn't establish interrupt"); 398 if (intrstr != NULL) 399 aprint_error(" at %s", intrstr); 400 aprint_error("\n"); 401 return; 402 } 403 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 404 405 sc->sc_cid = crypto_get_driverid(0); 406 if (sc->sc_cid < 0) { 407 aprint_error_dev(self, "couldn't get crypto driver id\n"); 408 pci_intr_disestablish(pc, sc->sc_ih); 409 return; 410 } 411 412 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 413 414 SIMPLEQ_INIT(&sc->sc_freequeue); 415 dmap = sc->sc_dmaa; 416 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 417 struct ubsec_q *q; 418 419 q = malloc(sizeof(struct ubsec_q), M_DEVBUF, M_ZERO|M_WAITOK); 420 421 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 422 &dmap->d_alloc, 0)) { 423 aprint_error_dev(self, "can't allocate dma buffers\n"); 424 free(q, M_DEVBUF); 425 break; 426 } 427 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 428 429 q->q_dma = dmap; 430 sc->sc_queuea[i] = q; 431 432 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 433 } 434 435 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 436 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 437 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 438 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 439 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 440 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 441 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 442 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 443 if (sc->sc_flags & UBS_FLAGS_AES) { 444 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 445 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 446 } 447 448 /* 449 * Reset Broadcom chip 450 */ 451 ubsec_reset_board(sc); 452 453 /* 454 * Init Broadcom specific PCI settings 455 */ 456 ubsec_init_pciregs(pa); 457 458 /* 459 * Init Broadcom chip 460 */ 461 ubsec_init_board(sc); 462 463 #ifndef UBSEC_NO_RNG 464 if (sc->sc_flags & UBS_FLAGS_RNG) { 465 if (sc->sc_flags & UBS_FLAGS_RNG4) 466 sc->sc_statmask |= BS_STAT_MCR4_DONE; 467 else 468 sc->sc_statmask |= BS_STAT_MCR2_DONE; 469 470 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 471 &sc->sc_rng.rng_q.q_mcr, 0)) 472 goto skip_rng; 473 474 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 475 &sc->sc_rng.rng_q.q_ctx, 0)) { 476 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 477 goto skip_rng; 478 } 479 480 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 481 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 482 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 483 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 484 goto skip_rng; 485 } 486 if (hz >= 100) 487 sc->sc_rnghz = hz / 100; 488 else 489 sc->sc_rnghz = 1; 490 callout_init(&sc->sc_rngto, 0); 491 callout_setfunc(&sc->sc_rngto, ubsec_rng, sc); 492 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 493 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 494 RND_TYPE_RNG, 495 RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 496 497 skip_rng: 498 if (sc->sc_rnghz) 499 aprint_normal_dev(self, 500 "random number generator enabled\n"); 501 else 502 aprint_error_dev(self, 503 "WARNING: random number generator disabled\n"); 504 } 505 #endif /* UBSEC_NO_RNG */ 506 507 if (sc->sc_flags & UBS_FLAGS_KEY) { 508 sc->sc_statmask |= BS_STAT_MCR2_DONE; 509 510 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 511 ubsec_kprocess, sc); 512 #if 0 513 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 514 ubsec_kprocess, sc); 515 #endif 516 } 517 } 518 519 static int 520 ubsec_detach(device_t self, int flags) 521 { 522 struct ubsec_softc *sc = device_private(self); 523 struct ubsec_q *q, *qtmp; 524 volatile u_int32_t ctrl; 525 526 /* disable interrupts */ 527 /* XXX wait/abort current ops? where is DMAERR enabled? */ 528 ctrl = READ_REG(sc, BS_CTRL); 529 530 ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR); 531 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 532 ctrl &= ~BS_CTRL_MCR4INT; 533 534 WRITE_REG(sc, BS_CTRL, ctrl); 535 536 #ifndef UBSEC_NO_RNG 537 if (sc->sc_flags & UBS_FLAGS_RNG) { 538 callout_halt(&sc->sc_rngto, NULL); 539 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 540 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 541 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 542 rnd_detach_source(&sc->sc_rnd_source); 543 } 544 #endif /* UBSEC_NO_RNG */ 545 546 crypto_unregister_all(sc->sc_cid); 547 548 mutex_spin_enter(&sc->sc_mtx); 549 550 ubsec_totalreset(sc); /* XXX leaves the chip running */ 551 552 SIMPLEQ_FOREACH_SAFE(q, &sc->sc_freequeue, q_next, qtmp) { 553 ubsec_dma_free(sc, &q->q_dma->d_alloc); 554 if (q->q_src_map != NULL) 555 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 556 if (q->q_cached_dst_map != NULL) 557 bus_dmamap_destroy(sc->sc_dmat, q->q_cached_dst_map); 558 free(q, M_DEVBUF); 559 } 560 561 mutex_spin_exit(&sc->sc_mtx); 562 563 if (sc->sc_ih != NULL) { 564 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 565 sc->sc_ih = NULL; 566 } 567 568 if (sc->sc_memsize != 0) { 569 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_memsize); 570 sc->sc_memsize = 0; 571 } 572 573 return 0; 574 } 575 576 MODULE(MODULE_CLASS_DRIVER, ubsec, "pci,opencrypto"); 577 578 #ifdef _MODULE 579 #include "ioconf.c" 580 #endif 581 582 static int 583 ubsec_modcmd(modcmd_t cmd, void *data) 584 { 585 int error = 0; 586 587 switch (cmd) { 588 case MODULE_CMD_INIT: 589 #ifdef _MODULE 590 error = config_init_component(cfdriver_ioconf_ubsec, 591 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 592 #endif 593 return error; 594 case MODULE_CMD_FINI: 595 #ifdef _MODULE 596 error = config_fini_component(cfdriver_ioconf_ubsec, 597 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 598 #endif 599 return error; 600 default: 601 return ENOTTY; 602 } 603 } 604 605 SYSCTL_SETUP(ubsec_sysctl_init, "ubsec sysctl") 606 { 607 const struct sysctlnode *node = NULL; 608 609 sysctl_createv(clog, 0, NULL, &node, 610 CTLFLAG_PERMANENT, 611 CTLTYPE_NODE, "ubsec", 612 SYSCTL_DESCR("ubsec opetions"), 613 NULL, 0, NULL, 0, 614 CTL_HW, CTL_CREATE, CTL_EOL); 615 sysctl_createv(clog, 0, &node, NULL, 616 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 617 CTLTYPE_INT, "maxbatch", 618 SYSCTL_DESCR("max ops to batch w/o interrupt"), 619 NULL, 0, &ubsec_maxbatch, 0, 620 CTL_CREATE, CTL_EOL); 621 sysctl_createv(clog, 0, &node, NULL, 622 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 623 CTLTYPE_INT, "maxaggr", 624 SYSCTL_DESCR("max ops to aggregate under one interrupt"), 625 NULL, 0, &ubsec_maxaggr, 0, 626 CTL_CREATE, CTL_EOL); 627 628 return; 629 } 630 631 /* 632 * UBSEC Interrupt routine 633 */ 634 static int 635 ubsec_intr(void *arg) 636 { 637 struct ubsec_softc *sc = arg; 638 volatile u_int32_t stat; 639 struct ubsec_q *q; 640 struct ubsec_dma *dmap; 641 int flags; 642 int npkts = 0, i; 643 644 mutex_spin_enter(&sc->sc_mtx); 645 stat = READ_REG(sc, BS_STAT); 646 stat &= sc->sc_statmask; 647 if (stat == 0) { 648 mutex_spin_exit(&sc->sc_mtx); 649 return (0); 650 } 651 652 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 653 654 /* 655 * Check to see if we have any packets waiting for us 656 */ 657 if ((stat & BS_STAT_MCR1_DONE)) { 658 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 659 q = SIMPLEQ_FIRST(&sc->sc_qchip); 660 dmap = q->q_dma; 661 662 if ((dmap->d_dma->d_mcr.mcr_flags 663 & htole16(UBS_MCR_DONE)) == 0) 664 break; 665 666 q = SIMPLEQ_FIRST(&sc->sc_qchip); 667 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 668 669 npkts = q->q_nstacked_mcrs; 670 sc->sc_nqchip -= 1+npkts; 671 /* 672 * search for further sc_qchip ubsec_q's that share 673 * the same MCR, and complete them too, they must be 674 * at the top. 675 */ 676 for (i = 0; i < npkts; i++) { 677 if(q->q_stacked_mcr[i]) 678 ubsec_callback(sc, q->q_stacked_mcr[i]); 679 else 680 break; 681 } 682 ubsec_callback(sc, q); 683 } 684 685 /* 686 * Don't send any more packet to chip if there has been 687 * a DMAERR. 688 */ 689 if (!(stat & BS_STAT_DMAERR)) 690 ubsec_feed(sc); 691 } 692 693 /* 694 * Check to see if we have any key setups/rng's waiting for us 695 */ 696 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 697 (stat & BS_STAT_MCR2_DONE)) { 698 struct ubsec_q2 *q2; 699 struct ubsec_mcr *mcr; 700 701 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 702 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 703 704 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 705 0, q2->q_mcr.dma_map->dm_mapsize, 706 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 707 708 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 709 710 /* A bug in new devices requires to swap this field */ 711 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 712 flags = htole16(mcr->mcr_flags); 713 else 714 flags = mcr->mcr_flags; 715 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 716 bus_dmamap_sync(sc->sc_dmat, 717 q2->q_mcr.dma_map, 0, 718 q2->q_mcr.dma_map->dm_mapsize, 719 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 720 break; 721 } 722 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 723 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 724 ubsec_callback2(sc, q2); 725 /* 726 * Don't send any more packet to chip if there has been 727 * a DMAERR. 728 */ 729 if (!(stat & BS_STAT_DMAERR)) 730 ubsec_feed2(sc); 731 } 732 } 733 if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { 734 struct ubsec_q2 *q2; 735 struct ubsec_mcr *mcr; 736 737 while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { 738 q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); 739 740 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 741 0, q2->q_mcr.dma_map->dm_mapsize, 742 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 743 744 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 745 746 /* A bug in new devices requires to swap this field */ 747 flags = htole16(mcr->mcr_flags); 748 749 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 750 bus_dmamap_sync(sc->sc_dmat, 751 q2->q_mcr.dma_map, 0, 752 q2->q_mcr.dma_map->dm_mapsize, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 break; 755 } 756 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); 757 ubsec_callback2(sc, q2); 758 /* 759 * Don't send any more packet to chip if there has been 760 * a DMAERR. 761 */ 762 if (!(stat & BS_STAT_DMAERR)) 763 ubsec_feed4(sc); 764 } 765 } 766 767 /* 768 * Check to see if we got any DMA Error 769 */ 770 if (stat & BS_STAT_DMAERR) { 771 #ifdef UBSEC_DEBUG 772 if (ubsec_debug) { 773 volatile u_int32_t a = READ_REG(sc, BS_ERR); 774 775 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 776 (a & BS_ERR_READ) ? "read" : "write", 777 a & BS_ERR_ADDR); 778 } 779 #endif /* UBSEC_DEBUG */ 780 ubsecstats.hst_dmaerr++; 781 ubsec_totalreset(sc); 782 ubsec_feed(sc); 783 } 784 785 if (sc->sc_needwakeup) { /* XXX check high watermark */ 786 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 787 #ifdef UBSEC_DEBUG 788 if (ubsec_debug) 789 printf("%s: wakeup crypto (%x)\n", 790 device_xname(sc->sc_dev), sc->sc_needwakeup); 791 #endif /* UBSEC_DEBUG */ 792 sc->sc_needwakeup &= ~wkeup; 793 crypto_unblock(sc->sc_cid, wkeup); 794 } 795 mutex_spin_exit(&sc->sc_mtx); 796 return (1); 797 } 798 799 /* 800 * ubsec_feed() - aggregate and post requests to chip 801 * OpenBSD comments: 802 * It is assumed that the caller set splnet() 803 */ 804 static void 805 ubsec_feed(struct ubsec_softc *sc) 806 { 807 struct ubsec_q *q, *q2; 808 int npkts, i; 809 void *v; 810 u_int32_t stat; 811 #ifdef UBSEC_DEBUG 812 static int max; 813 #endif /* UBSEC_DEBUG */ 814 815 npkts = sc->sc_nqueue; 816 if (npkts > ubsecstats.hst_maxqueue) 817 ubsecstats.hst_maxqueue = npkts; 818 if (npkts < 2) 819 goto feed1; 820 821 /* 822 * Decide how many ops to combine in a single MCR. We cannot 823 * aggregate more than UBS_MAX_AGGR because this is the number 824 * of slots defined in the data structure. Otherwise we clamp 825 * based on the tunable parameter ubsec_maxaggr. Note that 826 * aggregation can happen in two ways: either by batching ops 827 * from above or because the h/w backs up and throttles us. 828 * Aggregating ops reduces the number of interrupts to the host 829 * but also (potentially) increases the latency for processing 830 * completed ops as we only get an interrupt when all aggregated 831 * ops have completed. 832 */ 833 if (npkts > sc->sc_maxaggr) 834 npkts = sc->sc_maxaggr; 835 if (npkts > ubsec_maxaggr) 836 npkts = ubsec_maxaggr; 837 if (npkts > ubsecstats.hst_maxbatch) 838 ubsecstats.hst_maxbatch = npkts; 839 if (npkts < 2) 840 goto feed1; 841 ubsecstats.hst_totbatch += npkts-1; 842 843 if ((stat = READ_REG(sc, BS_STAT)) 844 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 845 if (stat & BS_STAT_DMAERR) { 846 ubsec_totalreset(sc); 847 ubsecstats.hst_dmaerr++; 848 } else { 849 ubsecstats.hst_mcr1full++; 850 } 851 return; 852 } 853 854 #ifdef UBSEC_DEBUG 855 if (ubsec_debug) 856 printf("merging %d records\n", npkts); 857 /* XXX temporary aggregation statistics reporting code */ 858 if (max < npkts) { 859 max = npkts; 860 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), 861 max); 862 } 863 #endif /* UBSEC_DEBUG */ 864 865 q = SIMPLEQ_FIRST(&sc->sc_queue); 866 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 867 --sc->sc_nqueue; 868 869 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 870 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 871 if (q->q_dst_map != NULL) 872 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 873 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 874 875 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 876 877 for (i = 0; i < q->q_nstacked_mcrs; i++) { 878 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 879 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 880 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 881 if (q2->q_dst_map != NULL) 882 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 883 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 884 q2= SIMPLEQ_FIRST(&sc->sc_queue); 885 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 886 --sc->sc_nqueue; 887 888 v = ((void *)&q2->q_dma->d_dma->d_mcr); 889 v = (char*)v + (sizeof(struct ubsec_mcr) - 890 sizeof(struct ubsec_mcr_add)); 891 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, 892 sizeof(struct ubsec_mcr_add)); 893 q->q_stacked_mcr[i] = q2; 894 } 895 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 896 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 897 sc->sc_nqchip += npkts; 898 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 899 ubsecstats.hst_maxqchip = sc->sc_nqchip; 900 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 901 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 902 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 903 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 904 offsetof(struct ubsec_dmachunk, d_mcr)); 905 return; 906 907 feed1: 908 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 909 if ((stat = READ_REG(sc, BS_STAT)) 910 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 911 if (stat & BS_STAT_DMAERR) { 912 ubsec_totalreset(sc); 913 ubsecstats.hst_dmaerr++; 914 } else { 915 ubsecstats.hst_mcr1full++; 916 } 917 break; 918 } 919 920 q = SIMPLEQ_FIRST(&sc->sc_queue); 921 922 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 923 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 924 if (q->q_dst_map != NULL) 925 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 926 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 927 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 928 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 930 931 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 932 offsetof(struct ubsec_dmachunk, d_mcr)); 933 #ifdef UBSEC_DEBUG 934 if (ubsec_debug) 935 printf("feed: q->chip %p %08x stat %08x\n", 936 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 937 stat); 938 #endif /* UBSEC_DEBUG */ 939 q = SIMPLEQ_FIRST(&sc->sc_queue); 940 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 941 --sc->sc_nqueue; 942 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 943 sc->sc_nqchip++; 944 } 945 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 946 ubsecstats.hst_maxqchip = sc->sc_nqchip; 947 } 948 949 /* 950 * Allocate a new 'session' and return an encoded session id. 'sidp' 951 * contains our registration id, and should contain an encoded session 952 * id on successful allocation. 953 */ 954 static int 955 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 956 { 957 struct cryptoini *c, *encini = NULL, *macini = NULL; 958 struct ubsec_softc *sc; 959 struct ubsec_session *ses = NULL; 960 MD5_CTX md5ctx; 961 SHA1_CTX sha1ctx; 962 int i, sesn; 963 964 sc = arg; 965 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 966 967 if (sidp == NULL || cri == NULL || sc == NULL) 968 return (EINVAL); 969 970 for (c = cri; c != NULL; c = c->cri_next) { 971 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 972 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 973 if (macini) 974 return (EINVAL); 975 macini = c; 976 } else if (c->cri_alg == CRYPTO_DES_CBC || 977 c->cri_alg == CRYPTO_3DES_CBC || 978 c->cri_alg == CRYPTO_AES_CBC) { 979 if (encini) 980 return (EINVAL); 981 encini = c; 982 } else 983 return (EINVAL); 984 } 985 if (encini == NULL && macini == NULL) 986 return (EINVAL); 987 988 if (encini && encini->cri_alg == CRYPTO_AES_CBC) { 989 switch (encini->cri_klen) { 990 case 128: 991 case 192: 992 case 256: 993 break; 994 default: 995 return (EINVAL); 996 } 997 } 998 999 if (sc->sc_sessions == NULL) { 1000 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 1001 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1002 if (ses == NULL) 1003 return (ENOMEM); 1004 sesn = 0; 1005 sc->sc_nsessions = 1; 1006 } else { 1007 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 1008 if (sc->sc_sessions[sesn].ses_used == 0) { 1009 ses = &sc->sc_sessions[sesn]; 1010 break; 1011 } 1012 } 1013 1014 if (ses == NULL) { 1015 sesn = sc->sc_nsessions; 1016 ses = (struct ubsec_session *)malloc((sesn + 1) * 1017 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1018 if (ses == NULL) 1019 return (ENOMEM); 1020 memcpy(ses, sc->sc_sessions, sesn * 1021 sizeof(struct ubsec_session)); 1022 memset(sc->sc_sessions, 0, sesn * 1023 sizeof(struct ubsec_session)); 1024 free(sc->sc_sessions, M_DEVBUF); 1025 sc->sc_sessions = ses; 1026 ses = &sc->sc_sessions[sesn]; 1027 sc->sc_nsessions++; 1028 } 1029 } 1030 1031 memset(ses, 0, sizeof(struct ubsec_session)); 1032 ses->ses_used = 1; 1033 if (encini) { 1034 /* Go ahead and compute key in ubsec's byte order */ 1035 if (encini->cri_alg == CRYPTO_AES_CBC) { 1036 memcpy(ses->ses_key, encini->cri_key, 1037 encini->cri_klen / 8); 1038 } 1039 if (encini->cri_alg == CRYPTO_DES_CBC) { 1040 memcpy(&ses->ses_key[0], encini->cri_key, 8); 1041 memcpy(&ses->ses_key[2], encini->cri_key, 8); 1042 memcpy(&ses->ses_key[4], encini->cri_key, 8); 1043 } else 1044 memcpy(ses->ses_key, encini->cri_key, 24); 1045 1046 SWAP32(ses->ses_key[0]); 1047 SWAP32(ses->ses_key[1]); 1048 SWAP32(ses->ses_key[2]); 1049 SWAP32(ses->ses_key[3]); 1050 SWAP32(ses->ses_key[4]); 1051 SWAP32(ses->ses_key[5]); 1052 } 1053 1054 if (macini) { 1055 for (i = 0; i < macini->cri_klen / 8; i++) 1056 macini->cri_key[i] ^= HMAC_IPAD_VAL; 1057 1058 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1059 MD5Init(&md5ctx); 1060 MD5Update(&md5ctx, macini->cri_key, 1061 macini->cri_klen / 8); 1062 MD5Update(&md5ctx, hmac_ipad_buffer, 1063 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1064 memcpy(ses->ses_hminner, md5ctx.state, 1065 sizeof(md5ctx.state)); 1066 } else { 1067 SHA1Init(&sha1ctx); 1068 SHA1Update(&sha1ctx, macini->cri_key, 1069 macini->cri_klen / 8); 1070 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1071 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1072 memcpy(ses->ses_hminner, sha1ctx.state, 1073 sizeof(sha1ctx.state)); 1074 } 1075 1076 for (i = 0; i < macini->cri_klen / 8; i++) 1077 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1078 1079 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1080 MD5Init(&md5ctx); 1081 MD5Update(&md5ctx, macini->cri_key, 1082 macini->cri_klen / 8); 1083 MD5Update(&md5ctx, hmac_opad_buffer, 1084 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1085 memcpy(ses->ses_hmouter, md5ctx.state, 1086 sizeof(md5ctx.state)); 1087 } else { 1088 SHA1Init(&sha1ctx); 1089 SHA1Update(&sha1ctx, macini->cri_key, 1090 macini->cri_klen / 8); 1091 SHA1Update(&sha1ctx, hmac_opad_buffer, 1092 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1093 memcpy(ses->ses_hmouter, sha1ctx.state, 1094 sizeof(sha1ctx.state)); 1095 } 1096 1097 for (i = 0; i < macini->cri_klen / 8; i++) 1098 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1099 } 1100 1101 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 1102 return (0); 1103 } 1104 1105 /* 1106 * Deallocate a session. 1107 */ 1108 static int 1109 ubsec_freesession(void *arg, u_int64_t tid) 1110 { 1111 struct ubsec_softc *sc; 1112 int session; 1113 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1114 1115 sc = arg; 1116 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 1117 1118 session = UBSEC_SESSION(sid); 1119 if (session >= sc->sc_nsessions) 1120 return (EINVAL); 1121 1122 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 1123 return (0); 1124 } 1125 1126 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 1127 static void 1128 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1129 int error) 1130 { 1131 struct ubsec_operand *op = arg; 1132 1133 KASSERT(nsegs <= UBS_MAX_SCATTER 1134 /*, ("Too many DMA segments returned when mapping operand")*/); 1135 #ifdef UBSEC_DEBUG 1136 if (ubsec_debug) 1137 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1138 (u_int) mapsize, nsegs); 1139 #endif 1140 op->mapsize = mapsize; 1141 op->nsegs = nsegs; 1142 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 1143 } 1144 #endif 1145 1146 static int 1147 ubsec_process(void *arg, struct cryptop *crp, int hint) 1148 { 1149 struct ubsec_q *q = NULL; 1150 int err = 0, i, j, nicealign; 1151 struct ubsec_softc *sc; 1152 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1153 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1154 int sskip, dskip, stheend, dtheend; 1155 int16_t coffset; 1156 struct ubsec_session *ses, key; 1157 struct ubsec_dma *dmap = NULL; 1158 u_int16_t flags = 0; 1159 int ivlen = 0, keylen = 0; 1160 1161 sc = arg; 1162 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 1163 1164 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1165 ubsecstats.hst_invalid++; 1166 return (EINVAL); 1167 } 1168 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1169 ubsecstats.hst_badsession++; 1170 return (EINVAL); 1171 } 1172 1173 mutex_spin_enter(&sc->sc_mtx); 1174 1175 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1176 ubsecstats.hst_queuefull++; 1177 sc->sc_needwakeup |= CRYPTO_SYMQ; 1178 mutex_spin_exit(&sc->sc_mtx); 1179 return(ERESTART); 1180 } 1181 1182 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1183 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 1184 mutex_spin_exit(&sc->sc_mtx); 1185 1186 dmap = q->q_dma; /* Save dma pointer */ 1187 /* don't lose the cached dmamaps q_src_map and q_cached_dst_map */ 1188 memset(q, 0, offsetof(struct ubsec_q, q_src_map)); 1189 memset(&key, 0, sizeof(key)); 1190 1191 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1192 q->q_dma = dmap; 1193 ses = &sc->sc_sessions[q->q_sesn]; 1194 1195 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1196 q->q_src_m = (struct mbuf *)crp->crp_buf; 1197 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1198 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1199 q->q_src_io = (struct uio *)crp->crp_buf; 1200 q->q_dst_io = (struct uio *)crp->crp_buf; 1201 } else { 1202 ubsecstats.hst_badflags++; 1203 err = EINVAL; 1204 goto errout; /* XXX we don't handle contiguous blocks! */ 1205 } 1206 1207 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 1208 1209 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1210 dmap->d_dma->d_mcr.mcr_flags = 0; 1211 q->q_crp = crp; 1212 1213 crd1 = crp->crp_desc; 1214 if (crd1 == NULL) { 1215 ubsecstats.hst_nodesc++; 1216 err = EINVAL; 1217 goto errout; 1218 } 1219 crd2 = crd1->crd_next; 1220 1221 if (crd2 == NULL) { 1222 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1223 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1224 maccrd = crd1; 1225 enccrd = NULL; 1226 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1227 crd1->crd_alg == CRYPTO_3DES_CBC || 1228 crd1->crd_alg == CRYPTO_AES_CBC) { 1229 maccrd = NULL; 1230 enccrd = crd1; 1231 } else { 1232 ubsecstats.hst_badalg++; 1233 err = EINVAL; 1234 goto errout; 1235 } 1236 } else { 1237 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1238 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1239 (crd2->crd_alg == CRYPTO_DES_CBC || 1240 crd2->crd_alg == CRYPTO_3DES_CBC || 1241 crd2->crd_alg == CRYPTO_AES_CBC) && 1242 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1243 maccrd = crd1; 1244 enccrd = crd2; 1245 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1246 crd1->crd_alg == CRYPTO_3DES_CBC || 1247 crd1->crd_alg == CRYPTO_AES_CBC) && 1248 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1249 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1250 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1251 enccrd = crd1; 1252 maccrd = crd2; 1253 } else { 1254 /* 1255 * We cannot order the ubsec as requested 1256 */ 1257 ubsecstats.hst_badalg++; 1258 err = EINVAL; 1259 goto errout; 1260 } 1261 } 1262 1263 if (enccrd) { 1264 if (enccrd->crd_alg == CRYPTO_AES_CBC) { 1265 if ((sc->sc_flags & UBS_FLAGS_AES) == 0) { 1266 /* 1267 * We cannot order the ubsec as requested 1268 */ 1269 ubsecstats.hst_badalg++; 1270 err = EINVAL; 1271 goto errout; 1272 } 1273 flags |= htole16(UBS_PKTCTX_ENC_AES); 1274 switch (enccrd->crd_klen) { 1275 case 128: 1276 case 192: 1277 case 256: 1278 keylen = enccrd->crd_klen / 8; 1279 break; 1280 default: 1281 err = EINVAL; 1282 goto errout; 1283 } 1284 ivlen = 16; 1285 } else { 1286 flags |= htole16(UBS_PKTCTX_ENC_3DES); 1287 ivlen = 8; 1288 keylen = 24; 1289 } 1290 1291 encoffset = enccrd->crd_skip; 1292 1293 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1294 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1295 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1296 else 1297 cprng_fast(key.ses_iv, ivlen); 1298 1299 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1300 if (crp->crp_flags & CRYPTO_F_IMBUF) 1301 m_copyback(q->q_src_m, 1302 enccrd->crd_inject, 1303 ivlen, (void *)key.ses_iv); 1304 else if (crp->crp_flags & CRYPTO_F_IOV) 1305 cuio_copyback(q->q_src_io, 1306 enccrd->crd_inject, 1307 ivlen, (void *)key.ses_iv); 1308 } 1309 } else { 1310 flags |= htole16(UBS_PKTCTX_INBOUND); 1311 1312 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1313 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1314 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1315 m_copydata(q->q_src_m, enccrd->crd_inject, 1316 ivlen, (void *)key.ses_iv); 1317 else if (crp->crp_flags & CRYPTO_F_IOV) 1318 cuio_copydata(q->q_src_io, 1319 enccrd->crd_inject, 8, 1320 (void *)key.ses_iv); 1321 } 1322 1323 for (i = 0; i < (keylen / 4); i++) 1324 key.ses_key[i] = ses->ses_key[i]; 1325 for (i = 0; i < (ivlen / 4); i++) 1326 SWAP32(key.ses_iv[i]); 1327 } 1328 1329 if (maccrd) { 1330 macoffset = maccrd->crd_skip; 1331 1332 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1333 flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1334 else 1335 flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1336 1337 for (i = 0; i < 5; i++) { 1338 key.ses_hminner[i] = ses->ses_hminner[i]; 1339 key.ses_hmouter[i] = ses->ses_hmouter[i]; 1340 1341 HTOLE32(key.ses_hminner[i]); 1342 HTOLE32(key.ses_hmouter[i]); 1343 } 1344 } 1345 1346 if (enccrd && maccrd) { 1347 /* 1348 * ubsec cannot handle packets where the end of encryption 1349 * and authentication are not the same, or where the 1350 * encrypted part begins before the authenticated part. 1351 */ 1352 if ((encoffset + enccrd->crd_len) != 1353 (macoffset + maccrd->crd_len)) { 1354 ubsecstats.hst_lenmismatch++; 1355 err = EINVAL; 1356 goto errout; 1357 } 1358 if (enccrd->crd_skip < maccrd->crd_skip) { 1359 ubsecstats.hst_skipmismatch++; 1360 err = EINVAL; 1361 goto errout; 1362 } 1363 sskip = maccrd->crd_skip; 1364 cpskip = dskip = enccrd->crd_skip; 1365 stheend = maccrd->crd_len; 1366 dtheend = enccrd->crd_len; 1367 coffset = enccrd->crd_skip - maccrd->crd_skip; 1368 cpoffset = cpskip + dtheend; 1369 #ifdef UBSEC_DEBUG 1370 if (ubsec_debug) { 1371 printf("mac: skip %d, len %d, inject %d\n", 1372 maccrd->crd_skip, maccrd->crd_len, 1373 maccrd->crd_inject); 1374 printf("enc: skip %d, len %d, inject %d\n", 1375 enccrd->crd_skip, enccrd->crd_len, 1376 enccrd->crd_inject); 1377 printf("src: skip %d, len %d\n", sskip, stheend); 1378 printf("dst: skip %d, len %d\n", dskip, dtheend); 1379 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1380 coffset, stheend, cpskip, cpoffset); 1381 } 1382 #endif 1383 } else { 1384 cpskip = dskip = sskip = macoffset + encoffset; 1385 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1386 cpoffset = cpskip + dtheend; 1387 coffset = 0; 1388 } 1389 1390 if (q->q_src_map == NULL) { 1391 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1392 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1393 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1394 err = ENOMEM; 1395 goto errout; 1396 } 1397 } 1398 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1399 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1400 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1401 ubsecstats.hst_noload++; 1402 err = ENOMEM; 1403 goto errout; 1404 } 1405 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1406 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1407 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1408 ubsecstats.hst_noload++; 1409 err = ENOMEM; 1410 goto errout; 1411 } 1412 } 1413 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1414 1415 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1416 1417 #ifdef UBSEC_DEBUG 1418 if (ubsec_debug) 1419 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1420 #endif 1421 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1422 struct ubsec_pktbuf *pb; 1423 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1424 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1425 1426 if (sskip >= packl) { 1427 sskip -= packl; 1428 continue; 1429 } 1430 1431 packl -= sskip; 1432 packp += sskip; 1433 sskip = 0; 1434 1435 if (packl > 0xfffc) { 1436 err = EIO; 1437 goto errout; 1438 } 1439 1440 if (j == 0) 1441 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1442 else 1443 pb = &dmap->d_dma->d_sbuf[j - 1]; 1444 1445 pb->pb_addr = htole32(packp); 1446 1447 if (stheend) { 1448 if (packl > stheend) { 1449 pb->pb_len = htole32(stheend); 1450 stheend = 0; 1451 } else { 1452 pb->pb_len = htole32(packl); 1453 stheend -= packl; 1454 } 1455 } else 1456 pb->pb_len = htole32(packl); 1457 1458 if ((i + 1) == q->q_src_map->dm_nsegs) 1459 pb->pb_next = 0; 1460 else 1461 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1462 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1463 j++; 1464 } 1465 1466 if (enccrd == NULL && maccrd != NULL) { 1467 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1468 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1469 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1470 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1471 #ifdef UBSEC_DEBUG 1472 if (ubsec_debug) 1473 printf("opkt: %x %x %x\n", 1474 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1475 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1476 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1477 1478 #endif 1479 } else { 1480 if (crp->crp_flags & CRYPTO_F_IOV) { 1481 if (!nicealign) { 1482 ubsecstats.hst_iovmisaligned++; 1483 err = EINVAL; 1484 goto errout; 1485 } 1486 if (q->q_dst_map == NULL) { 1487 if (q->q_cached_dst_map == NULL) { 1488 /* 1489 * XXX: ``what the heck's that'' 1490 * 0xfff0? 1491 */ 1492 if (bus_dmamap_create(sc->sc_dmat, 1493 0xfff0, UBS_MAX_SCATTER, 0xfff0, 0, 1494 BUS_DMA_NOWAIT, 1495 &q->q_cached_dst_map) != 0) { 1496 ubsecstats.hst_nomap++; 1497 err = ENOMEM; 1498 goto errout; 1499 } 1500 } 1501 q->q_dst_map = q->q_cached_dst_map; 1502 } 1503 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1504 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1505 ubsecstats.hst_noload++; 1506 err = ENOMEM; 1507 goto errout; 1508 } 1509 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1510 if (nicealign) { 1511 q->q_dst_m = q->q_src_m; 1512 q->q_dst_map = q->q_src_map; 1513 } else { 1514 int totlen, len; 1515 struct mbuf *m, *top, **mp; 1516 1517 ubsecstats.hst_unaligned++; 1518 totlen = q->q_src_map->dm_mapsize; 1519 if (q->q_src_m->m_flags & M_PKTHDR) { 1520 len = MHLEN; 1521 MGETHDR(m, M_DONTWAIT, MT_DATA); 1522 /*XXX FIXME: m_dup_pkthdr */ 1523 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1524 m_free(m); 1525 m = NULL; 1526 } 1527 } else { 1528 len = MLEN; 1529 MGET(m, M_DONTWAIT, MT_DATA); 1530 } 1531 if (m == NULL) { 1532 ubsecstats.hst_nombuf++; 1533 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1534 goto errout; 1535 } 1536 if (len == MHLEN) 1537 /*XXX was M_DUP_PKTHDR*/ 1538 m_copy_pkthdr(m, q->q_src_m); 1539 if (totlen >= MINCLSIZE) { 1540 MCLGET(m, M_DONTWAIT); 1541 if ((m->m_flags & M_EXT) == 0) { 1542 m_free(m); 1543 ubsecstats.hst_nomcl++; 1544 err = sc->sc_nqueue 1545 ? ERESTART : ENOMEM; 1546 goto errout; 1547 } 1548 len = MCLBYTES; 1549 } 1550 m->m_len = len; 1551 top = NULL; 1552 mp = ⊤ 1553 1554 while (totlen > 0) { 1555 if (top) { 1556 MGET(m, M_DONTWAIT, MT_DATA); 1557 if (m == NULL) { 1558 m_freem(top); 1559 ubsecstats.hst_nombuf++; 1560 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1561 goto errout; 1562 } 1563 len = MLEN; 1564 } 1565 if (top && totlen >= MINCLSIZE) { 1566 MCLGET(m, M_DONTWAIT); 1567 if ((m->m_flags & M_EXT) == 0) { 1568 *mp = m; 1569 m_freem(top); 1570 ubsecstats.hst_nomcl++; 1571 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1572 goto errout; 1573 } 1574 len = MCLBYTES; 1575 } 1576 m->m_len = len = uimin(totlen, len); 1577 totlen -= len; 1578 *mp = m; 1579 mp = &m->m_next; 1580 } 1581 q->q_dst_m = top; 1582 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1583 cpskip, cpoffset); 1584 if (q->q_dst_map == NULL) { 1585 if (q->q_cached_dst_map == NULL) { 1586 /* XXX again, what the heck is that 0xfff0? */ 1587 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1588 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1589 &q->q_cached_dst_map) != 0) { 1590 ubsecstats.hst_nomap++; 1591 err = ENOMEM; 1592 goto errout; 1593 } 1594 } 1595 q->q_dst_map = q->q_cached_dst_map; 1596 } 1597 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1598 q->q_dst_map, q->q_dst_m, 1599 BUS_DMA_NOWAIT) != 0) { 1600 ubsecstats.hst_noload++; 1601 err = ENOMEM; 1602 goto errout; 1603 } 1604 } 1605 } else { 1606 ubsecstats.hst_badflags++; 1607 err = EINVAL; 1608 goto errout; 1609 } 1610 1611 #ifdef UBSEC_DEBUG 1612 if (ubsec_debug) 1613 printf("dst skip: %d\n", dskip); 1614 #endif 1615 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1616 struct ubsec_pktbuf *pb; 1617 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1618 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1619 1620 if (dskip >= packl) { 1621 dskip -= packl; 1622 continue; 1623 } 1624 1625 packl -= dskip; 1626 packp += dskip; 1627 dskip = 0; 1628 1629 if (packl > 0xfffc) { 1630 err = EIO; 1631 goto errout; 1632 } 1633 1634 if (j == 0) 1635 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1636 else 1637 pb = &dmap->d_dma->d_dbuf[j - 1]; 1638 1639 pb->pb_addr = htole32(packp); 1640 1641 if (dtheend) { 1642 if (packl > dtheend) { 1643 pb->pb_len = htole32(dtheend); 1644 dtheend = 0; 1645 } else { 1646 pb->pb_len = htole32(packl); 1647 dtheend -= packl; 1648 } 1649 } else 1650 pb->pb_len = htole32(packl); 1651 1652 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1653 if (maccrd) 1654 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1655 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1656 else 1657 pb->pb_next = 0; 1658 } else 1659 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1660 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1661 j++; 1662 } 1663 } 1664 1665 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1666 offsetof(struct ubsec_dmachunk, d_ctx)); 1667 1668 if (enccrd && enccrd->crd_alg == CRYPTO_AES_CBC) { 1669 struct ubsec_pktctx_aes128 *aes128; 1670 struct ubsec_pktctx_aes192 *aes192; 1671 struct ubsec_pktctx_aes256 *aes256; 1672 struct ubsec_pktctx_hdr *ph; 1673 u_int8_t *ctx; 1674 1675 ctx = (u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1676 offsetof(struct ubsec_dmachunk, d_ctx); 1677 1678 ph = (struct ubsec_pktctx_hdr *)ctx; 1679 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); 1680 ph->ph_flags = flags; 1681 ph->ph_offset = htole16(coffset >> 2); 1682 1683 switch (enccrd->crd_klen) { 1684 case 128: 1685 aes128 = (struct ubsec_pktctx_aes128 *)ctx; 1686 ph->ph_len = htole16(sizeof(*aes128)); 1687 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_128); 1688 for (i = 0; i < 4; i++) 1689 aes128->pc_aeskey[i] = key.ses_key[i]; 1690 for (i = 0; i < 5; i++) 1691 aes128->pc_hminner[i] = key.ses_hminner[i]; 1692 for (i = 0; i < 5; i++) 1693 aes128->pc_hmouter[i] = key.ses_hmouter[i]; 1694 for (i = 0; i < 4; i++) 1695 aes128->pc_iv[i] = key.ses_iv[i]; 1696 break; 1697 case 192: 1698 aes192 = (struct ubsec_pktctx_aes192 *)ctx; 1699 ph->ph_len = htole16(sizeof(*aes192)); 1700 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_192); 1701 for (i = 0; i < 6; i++) 1702 aes192->pc_aeskey[i] = key.ses_key[i]; 1703 for (i = 0; i < 5; i++) 1704 aes192->pc_hminner[i] = key.ses_hminner[i]; 1705 for (i = 0; i < 5; i++) 1706 aes192->pc_hmouter[i] = key.ses_hmouter[i]; 1707 for (i = 0; i < 4; i++) 1708 aes192->pc_iv[i] = key.ses_iv[i]; 1709 break; 1710 case 256: 1711 aes256 = (struct ubsec_pktctx_aes256 *)ctx; 1712 ph->ph_len = htole16(sizeof(*aes256)); 1713 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_256); 1714 for (i = 0; i < 8; i++) 1715 aes256->pc_aeskey[i] = key.ses_key[i]; 1716 for (i = 0; i < 5; i++) 1717 aes256->pc_hminner[i] = key.ses_hminner[i]; 1718 for (i = 0; i < 5; i++) 1719 aes256->pc_hmouter[i] = key.ses_hmouter[i]; 1720 for (i = 0; i < 4; i++) 1721 aes256->pc_iv[i] = key.ses_iv[i]; 1722 break; 1723 } 1724 } else if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1725 struct ubsec_pktctx_3des *ctx; 1726 struct ubsec_pktctx_hdr *ph; 1727 1728 ctx = (struct ubsec_pktctx_3des *) 1729 ((u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1730 offsetof(struct ubsec_dmachunk, d_ctx)); 1731 1732 ph = (struct ubsec_pktctx_hdr *)ctx; 1733 ph->ph_len = htole16(sizeof(*ctx)); 1734 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_3DES); 1735 ph->ph_flags = flags; 1736 ph->ph_offset = htole16(coffset >> 2); 1737 1738 for (i = 0; i < 6; i++) 1739 ctx->pc_deskey[i] = key.ses_key[i]; 1740 for (i = 0; i < 5; i++) 1741 ctx->pc_hminner[i] = key.ses_hminner[i]; 1742 for (i = 0; i < 5; i++) 1743 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1744 for (i = 0; i < 2; i++) 1745 ctx->pc_iv[i] = key.ses_iv[i]; 1746 } else { 1747 struct ubsec_pktctx *ctx = (struct ubsec_pktctx *) 1748 ((u_int8_t *)dmap->d_alloc.dma_vaddr + 1749 offsetof(struct ubsec_dmachunk, d_ctx)); 1750 1751 ctx->pc_flags = flags; 1752 ctx->pc_offset = htole16(coffset >> 2); 1753 for (i = 0; i < 6; i++) 1754 ctx->pc_deskey[i] = key.ses_key[i]; 1755 for (i = 0; i < 5; i++) 1756 ctx->pc_hminner[i] = key.ses_hminner[i]; 1757 for (i = 0; i < 5; i++) 1758 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1759 for (i = 0; i < 2; i++) 1760 ctx->pc_iv[i] = key.ses_iv[i]; 1761 } 1762 1763 mutex_spin_enter(&sc->sc_mtx); 1764 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1765 sc->sc_nqueue++; 1766 ubsecstats.hst_ipackets++; 1767 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1768 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1769 ubsec_feed(sc); 1770 mutex_spin_exit(&sc->sc_mtx); 1771 return (0); 1772 1773 errout: 1774 if (q != NULL) { 1775 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1776 m_freem(q->q_dst_m); 1777 1778 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1779 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1780 } 1781 if (q->q_src_map != NULL) { 1782 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1783 } 1784 1785 mutex_spin_enter(&sc->sc_mtx); 1786 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1787 mutex_spin_exit(&sc->sc_mtx); 1788 } 1789 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1790 if (err == EINVAL) 1791 ubsecstats.hst_invalid++; 1792 else 1793 ubsecstats.hst_nomem++; 1794 #endif 1795 if (err != ERESTART) { 1796 crp->crp_etype = err; 1797 crypto_done(crp); 1798 } else { 1799 sc->sc_needwakeup |= CRYPTO_SYMQ; 1800 } 1801 return (err); 1802 } 1803 1804 static void 1805 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1806 { 1807 struct cryptop *crp = (struct cryptop *)q->q_crp; 1808 struct cryptodesc *crd; 1809 struct ubsec_dma *dmap = q->q_dma; 1810 1811 ubsecstats.hst_opackets++; 1812 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1813 1814 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1815 dmap->d_alloc.dma_map->dm_mapsize, 1816 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1817 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1818 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1819 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1820 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1821 } 1822 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1823 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1824 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1825 1826 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1827 m_freem(q->q_src_m); 1828 crp->crp_buf = (void *)q->q_dst_m; 1829 } 1830 1831 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1832 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1833 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1834 continue; 1835 if (crp->crp_flags & CRYPTO_F_IMBUF) 1836 m_copyback((struct mbuf *)crp->crp_buf, 1837 crd->crd_inject, 12, 1838 (void *)dmap->d_dma->d_macbuf); 1839 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1840 bcopy((void *)dmap->d_dma->d_macbuf, 1841 crp->crp_mac, 12); 1842 break; 1843 } 1844 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1845 crypto_done(crp); 1846 } 1847 1848 static void 1849 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1850 { 1851 int i, j, dlen, slen; 1852 char *dptr, *sptr; 1853 1854 j = 0; 1855 sptr = srcm->m_data; 1856 slen = srcm->m_len; 1857 dptr = dstm->m_data; 1858 dlen = dstm->m_len; 1859 1860 while (1) { 1861 for (i = 0; i < uimin(slen, dlen); i++) { 1862 if (j < hoffset || j >= toffset) 1863 *dptr++ = *sptr++; 1864 slen--; 1865 dlen--; 1866 j++; 1867 } 1868 if (slen == 0) { 1869 srcm = srcm->m_next; 1870 if (srcm == NULL) 1871 return; 1872 sptr = srcm->m_data; 1873 slen = srcm->m_len; 1874 } 1875 if (dlen == 0) { 1876 dstm = dstm->m_next; 1877 if (dstm == NULL) 1878 return; 1879 dptr = dstm->m_data; 1880 dlen = dstm->m_len; 1881 } 1882 } 1883 } 1884 1885 /* 1886 * feed the key generator, must be called at splnet() or higher. 1887 */ 1888 static void 1889 ubsec_feed2(struct ubsec_softc *sc) 1890 { 1891 struct ubsec_q2 *q; 1892 1893 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1894 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1895 break; 1896 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1897 1898 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1899 q->q_mcr.dma_map->dm_mapsize, 1900 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1901 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1902 q->q_ctx.dma_map->dm_mapsize, 1903 BUS_DMASYNC_PREWRITE); 1904 1905 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1906 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1907 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1908 --sc->sc_nqueue2; 1909 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1910 } 1911 } 1912 1913 /* 1914 * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) 1915 */ 1916 void 1917 ubsec_feed4(struct ubsec_softc *sc) 1918 { 1919 struct ubsec_q2 *q; 1920 1921 while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { 1922 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) 1923 break; 1924 q = SIMPLEQ_FIRST(&sc->sc_queue4); 1925 1926 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1927 q->q_mcr.dma_map->dm_mapsize, 1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1929 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1930 q->q_ctx.dma_map->dm_mapsize, 1931 BUS_DMASYNC_PREWRITE); 1932 1933 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); 1934 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); 1935 --sc->sc_nqueue4; 1936 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); 1937 } 1938 } 1939 1940 /* 1941 * Callback for handling random numbers 1942 */ 1943 static void 1944 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1945 { 1946 struct cryptkop *krp; 1947 struct ubsec_ctx_keyop *ctx; 1948 1949 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1950 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1951 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1952 1953 switch (q->q_type) { 1954 #ifndef UBSEC_NO_RNG 1955 case UBS_CTXOP_RNGSHA1: 1956 case UBS_CTXOP_RNGBYPASS: { 1957 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1958 u_int32_t *p; 1959 int i; 1960 1961 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1962 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1963 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 1964 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 1965 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 1966 sc->sc_rng_need -= i; 1967 rng->rng_used = 0; 1968 if (sc->sc_rng_need > 0) { 1969 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 1970 } 1971 break; 1972 } 1973 #endif 1974 case UBS_CTXOP_MODEXP: { 1975 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1976 u_int rlen, clen; 1977 1978 krp = me->me_krp; 1979 rlen = (me->me_modbits + 7) / 8; 1980 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1981 1982 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 1983 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1984 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 1985 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1986 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 1987 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1988 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 1989 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1990 1991 if (clen < rlen) 1992 krp->krp_status = E2BIG; 1993 else { 1994 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1995 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 1996 (krp->krp_param[krp->krp_iparams].crp_nbits 1997 + 7) / 8); 1998 bcopy(me->me_C.dma_vaddr, 1999 krp->krp_param[krp->krp_iparams].crp_p, 2000 (me->me_modbits + 7) / 8); 2001 } else 2002 ubsec_kshift_l(me->me_shiftbits, 2003 me->me_C.dma_vaddr, me->me_normbits, 2004 krp->krp_param[krp->krp_iparams].crp_p, 2005 krp->krp_param[krp->krp_iparams].crp_nbits); 2006 } 2007 2008 crypto_kdone(krp); 2009 2010 /* bzero all potentially sensitive data */ 2011 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2012 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2013 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2014 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2015 2016 /* Can't free here, so put us on the free list. */ 2017 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 2018 break; 2019 } 2020 case UBS_CTXOP_RSAPRIV: { 2021 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2022 u_int len; 2023 2024 krp = rp->rpr_krp; 2025 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 2026 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2027 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 2028 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2029 2030 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) 2031 / 8; 2032 bcopy(rp->rpr_msgout.dma_vaddr, 2033 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 2034 2035 crypto_kdone(krp); 2036 2037 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2038 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2039 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 2040 2041 /* Can't free here, so put us on the free list. */ 2042 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 2043 break; 2044 } 2045 default: 2046 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 2047 letoh16(ctx->ctx_op)); 2048 break; 2049 } 2050 } 2051 2052 #ifndef UBSEC_NO_RNG 2053 2054 static void 2055 ubsec_rng_get(size_t bytes, void *vsc) 2056 { 2057 struct ubsec_softc *sc = vsc; 2058 2059 mutex_spin_enter(&sc->sc_mtx); 2060 sc->sc_rng_need = bytes; 2061 ubsec_rng_locked(sc); 2062 mutex_spin_exit(&sc->sc_mtx); 2063 2064 } 2065 2066 static void 2067 ubsec_rng(void *vsc) 2068 { 2069 struct ubsec_softc *sc = vsc; 2070 mutex_spin_enter(&sc->sc_mtx); 2071 ubsec_rng_locked(sc); 2072 mutex_spin_exit(&sc->sc_mtx); 2073 } 2074 2075 static void 2076 ubsec_rng_locked(void *vsc) 2077 { 2078 struct ubsec_softc *sc = vsc; 2079 struct ubsec_q2_rng *rng = &sc->sc_rng; 2080 struct ubsec_mcr *mcr; 2081 struct ubsec_ctx_rngbypass *ctx; 2082 int *nqueue; 2083 2084 /* Caller is responsible to lock and release sc_mtx. */ 2085 KASSERT(mutex_owned(&sc->sc_mtx)); 2086 2087 if (rng->rng_used) { 2088 return; 2089 } 2090 2091 if (sc->sc_rng_need < 1) { 2092 callout_stop(&sc->sc_rngto); 2093 return; 2094 } 2095 2096 if (sc->sc_flags & UBS_FLAGS_RNG4) 2097 nqueue = &sc->sc_nqueue4; 2098 else 2099 nqueue = &sc->sc_nqueue2; 2100 2101 (*nqueue)++; 2102 if (*nqueue >= UBS_MAX_NQUEUE) 2103 goto out; 2104 2105 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 2106 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 2107 2108 mcr->mcr_pkts = htole16(1); 2109 mcr->mcr_flags = 0; 2110 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 2111 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 2112 mcr->mcr_ipktbuf.pb_len = 0; 2113 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 2114 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 2115 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 2116 UBS_PKTBUF_LEN); 2117 mcr->mcr_opktbuf.pb_next = 0; 2118 2119 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 2120 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 2121 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 2122 2123 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2124 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2125 2126 if (sc->sc_flags & UBS_FLAGS_RNG4) { 2127 SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); 2128 ubsec_feed4(sc); 2129 } else { 2130 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 2131 ubsec_feed2(sc); 2132 } 2133 rng->rng_used = 1; 2134 ubsecstats.hst_rng++; 2135 2136 return; 2137 2138 out: 2139 /* 2140 * Something weird happened, generate our own call back. 2141 */ 2142 (*nqueue)--; 2143 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2144 } 2145 #endif /* UBSEC_NO_RNG */ 2146 2147 static int 2148 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 2149 struct ubsec_dma_alloc *dma,int mapflags) 2150 { 2151 int r; 2152 2153 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 2154 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 2155 goto fail_0; 2156 2157 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 2158 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 2159 goto fail_1; 2160 2161 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2162 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 2163 goto fail_2; 2164 2165 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 2166 size, NULL, BUS_DMA_NOWAIT)) != 0) 2167 goto fail_3; 2168 2169 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 2170 dma->dma_size = size; 2171 return (0); 2172 2173 fail_3: 2174 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2175 fail_2: 2176 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2177 fail_1: 2178 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2179 fail_0: 2180 dma->dma_map = NULL; 2181 return (r); 2182 } 2183 2184 static void 2185 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 2186 { 2187 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2188 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2189 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2190 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2191 } 2192 2193 /* 2194 * Resets the board. Values in the regesters are left as is 2195 * from the reset (i.e. initial values are assigned elsewhere). 2196 */ 2197 static void 2198 ubsec_reset_board(struct ubsec_softc *sc) 2199 { 2200 volatile u_int32_t ctrl; 2201 2202 ctrl = READ_REG(sc, BS_CTRL); 2203 ctrl |= BS_CTRL_RESET; 2204 WRITE_REG(sc, BS_CTRL, ctrl); 2205 2206 /* 2207 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2208 */ 2209 DELAY(10); 2210 2211 /* Enable RNG and interrupts on newer devices */ 2212 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2213 #ifndef UBSEC_NO_RNG 2214 WRITE_REG(sc, BS_CFG, BS_CFG_RNG); 2215 #endif 2216 WRITE_REG(sc, BS_INT, BS_INT_DMAINT); 2217 } 2218 } 2219 2220 /* 2221 * Init Broadcom registers 2222 */ 2223 static void 2224 ubsec_init_board(struct ubsec_softc *sc) 2225 { 2226 u_int32_t ctrl; 2227 2228 ctrl = READ_REG(sc, BS_CTRL); 2229 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2230 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2231 2232 /* 2233 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 2234 * anyone got hw docs? 2235 */ 2236 if (sc->sc_flags & UBS_FLAGS_KEY) 2237 ctrl |= BS_CTRL_MCR2INT; 2238 else 2239 ctrl &= ~BS_CTRL_MCR2INT; 2240 2241 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2242 ctrl &= ~BS_CTRL_SWNORM; 2243 2244 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2245 ctrl |= BS_CTRL_BSIZE240; 2246 ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ 2247 2248 if (sc->sc_flags & UBS_FLAGS_RNG4) 2249 ctrl |= BS_CTRL_MCR4INT; 2250 else 2251 ctrl &= ~BS_CTRL_MCR4INT; 2252 } 2253 2254 WRITE_REG(sc, BS_CTRL, ctrl); 2255 } 2256 2257 /* 2258 * Init Broadcom PCI registers 2259 */ 2260 static void 2261 ubsec_init_pciregs(struct pci_attach_args *pa) 2262 { 2263 pci_chipset_tag_t pc = pa->pa_pc; 2264 u_int32_t misc; 2265 2266 /* 2267 * This will set the cache line size to 1, this will 2268 * force the BCM58xx chip just to do burst read/writes. 2269 * Cache line read/writes are to slow 2270 */ 2271 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 2272 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 2273 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 2274 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 2275 } 2276 2277 /* 2278 * Clean up after a chip crash. 2279 * It is assumed that the caller in splnet() 2280 */ 2281 static void 2282 ubsec_cleanchip(struct ubsec_softc *sc) 2283 { 2284 struct ubsec_q *q; 2285 2286 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2287 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2288 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 2289 ubsec_free_q(sc, q); 2290 } 2291 sc->sc_nqchip = 0; 2292 } 2293 2294 /* 2295 * free a ubsec_q 2296 * It is assumed that the caller is within splnet() 2297 */ 2298 static int 2299 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2300 { 2301 struct ubsec_q *q2; 2302 struct cryptop *crp; 2303 int npkts; 2304 int i; 2305 2306 npkts = q->q_nstacked_mcrs; 2307 2308 for (i = 0; i < npkts; i++) { 2309 if(q->q_stacked_mcr[i]) { 2310 q2 = q->q_stacked_mcr[i]; 2311 2312 if ((q2->q_dst_m != NULL) 2313 && (q2->q_src_m != q2->q_dst_m)) 2314 m_freem(q2->q_dst_m); 2315 2316 crp = (struct cryptop *)q2->q_crp; 2317 2318 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2319 2320 crp->crp_etype = EFAULT; 2321 crypto_done(crp); 2322 } else { 2323 break; 2324 } 2325 } 2326 2327 /* 2328 * Free header MCR 2329 */ 2330 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2331 m_freem(q->q_dst_m); 2332 2333 crp = (struct cryptop *)q->q_crp; 2334 2335 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2336 2337 crp->crp_etype = EFAULT; 2338 crypto_done(crp); 2339 return(0); 2340 } 2341 2342 /* 2343 * Routine to reset the chip and clean up. 2344 * It is assumed that the caller is in splnet() 2345 */ 2346 static void 2347 ubsec_totalreset(struct ubsec_softc *sc) 2348 { 2349 ubsec_reset_board(sc); 2350 ubsec_init_board(sc); 2351 ubsec_cleanchip(sc); 2352 } 2353 2354 static int 2355 ubsec_dmamap_aligned(bus_dmamap_t map) 2356 { 2357 int i; 2358 2359 for (i = 0; i < map->dm_nsegs; i++) { 2360 if (map->dm_segs[i].ds_addr & 3) 2361 return (0); 2362 if ((i != (map->dm_nsegs - 1)) && 2363 (map->dm_segs[i].ds_len & 3)) 2364 return (0); 2365 } 2366 return (1); 2367 } 2368 2369 static void 2370 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2371 { 2372 switch (q->q_type) { 2373 case UBS_CTXOP_MODEXP: { 2374 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2375 2376 ubsec_dma_free(sc, &me->me_q.q_mcr); 2377 ubsec_dma_free(sc, &me->me_q.q_ctx); 2378 ubsec_dma_free(sc, &me->me_M); 2379 ubsec_dma_free(sc, &me->me_E); 2380 ubsec_dma_free(sc, &me->me_C); 2381 ubsec_dma_free(sc, &me->me_epb); 2382 free(me, M_DEVBUF); 2383 break; 2384 } 2385 case UBS_CTXOP_RSAPRIV: { 2386 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2387 2388 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2389 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2390 ubsec_dma_free(sc, &rp->rpr_msgin); 2391 ubsec_dma_free(sc, &rp->rpr_msgout); 2392 free(rp, M_DEVBUF); 2393 break; 2394 } 2395 default: 2396 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2397 q->q_type); 2398 break; 2399 } 2400 } 2401 2402 static int 2403 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2404 { 2405 struct ubsec_softc *sc; 2406 int r; 2407 2408 if (krp == NULL || krp->krp_callback == NULL) 2409 return (EINVAL); 2410 sc = arg; 2411 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2412 2413 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2414 struct ubsec_q2 *q; 2415 2416 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2417 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2418 ubsec_kfree(sc, q); 2419 } 2420 2421 switch (krp->krp_op) { 2422 case CRK_MOD_EXP: 2423 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2424 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2425 else 2426 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2427 break; 2428 case CRK_MOD_EXP_CRT: 2429 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2430 break; 2431 default: 2432 printf("%s: kprocess: invalid op 0x%x\n", 2433 device_xname(sc->sc_dev), krp->krp_op); 2434 krp->krp_status = EOPNOTSUPP; 2435 crypto_kdone(krp); 2436 r = 0; 2437 } 2438 return (r); 2439 } 2440 2441 /* 2442 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2443 */ 2444 static int 2445 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2446 int hint) 2447 { 2448 struct ubsec_q2_modexp *me; 2449 struct ubsec_mcr *mcr; 2450 struct ubsec_ctx_modexp *ctx; 2451 struct ubsec_pktbuf *epb; 2452 int err = 0; 2453 u_int nbits, normbits, mbits, shiftbits, ebits; 2454 2455 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2456 if (me == NULL) { 2457 err = ENOMEM; 2458 goto errout; 2459 } 2460 memset(me, 0, sizeof *me); 2461 me->me_krp = krp; 2462 me->me_q.q_type = UBS_CTXOP_MODEXP; 2463 2464 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2465 if (nbits <= 512) 2466 normbits = 512; 2467 else if (nbits <= 768) 2468 normbits = 768; 2469 else if (nbits <= 1024) 2470 normbits = 1024; 2471 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2472 normbits = 1536; 2473 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2474 normbits = 2048; 2475 else { 2476 err = E2BIG; 2477 goto errout; 2478 } 2479 2480 shiftbits = normbits - nbits; 2481 2482 me->me_modbits = nbits; 2483 me->me_shiftbits = shiftbits; 2484 me->me_normbits = normbits; 2485 2486 /* Sanity check: result bits must be >= true modulus bits. */ 2487 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2488 err = ERANGE; 2489 goto errout; 2490 } 2491 2492 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2493 &me->me_q.q_mcr, 0)) { 2494 err = ENOMEM; 2495 goto errout; 2496 } 2497 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2498 2499 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2500 &me->me_q.q_ctx, 0)) { 2501 err = ENOMEM; 2502 goto errout; 2503 } 2504 2505 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2506 if (mbits > nbits) { 2507 err = E2BIG; 2508 goto errout; 2509 } 2510 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2511 err = ENOMEM; 2512 goto errout; 2513 } 2514 ubsec_kshift_r(shiftbits, 2515 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2516 me->me_M.dma_vaddr, normbits); 2517 2518 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2519 err = ENOMEM; 2520 goto errout; 2521 } 2522 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2523 2524 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2525 if (ebits > nbits) { 2526 err = E2BIG; 2527 goto errout; 2528 } 2529 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2530 err = ENOMEM; 2531 goto errout; 2532 } 2533 ubsec_kshift_r(shiftbits, 2534 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2535 me->me_E.dma_vaddr, normbits); 2536 2537 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2538 &me->me_epb, 0)) { 2539 err = ENOMEM; 2540 goto errout; 2541 } 2542 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2543 epb->pb_addr = htole32(me->me_E.dma_paddr); 2544 epb->pb_next = 0; 2545 epb->pb_len = htole32(normbits / 8); 2546 2547 #ifdef UBSEC_DEBUG 2548 if (ubsec_debug) { 2549 printf("Epb "); 2550 ubsec_dump_pb(epb); 2551 } 2552 #endif 2553 2554 mcr->mcr_pkts = htole16(1); 2555 mcr->mcr_flags = 0; 2556 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2557 mcr->mcr_reserved = 0; 2558 mcr->mcr_pktlen = 0; 2559 2560 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2561 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2562 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2563 2564 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2565 mcr->mcr_opktbuf.pb_next = 0; 2566 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2567 2568 #ifdef DIAGNOSTIC 2569 /* Misaligned output buffer will hang the chip. */ 2570 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2571 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2572 letoh32(mcr->mcr_opktbuf.pb_addr)); 2573 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2574 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2575 letoh32(mcr->mcr_opktbuf.pb_len)); 2576 #endif 2577 2578 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2579 memset(ctx, 0, sizeof(*ctx)); 2580 ubsec_kshift_r(shiftbits, 2581 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2582 ctx->me_N, normbits); 2583 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2584 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2585 ctx->me_E_len = htole16(nbits); 2586 ctx->me_N_len = htole16(nbits); 2587 2588 #ifdef UBSEC_DEBUG 2589 if (ubsec_debug) { 2590 ubsec_dump_mcr(mcr); 2591 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2592 } 2593 #endif 2594 2595 /* 2596 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2597 * everything else. 2598 */ 2599 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2600 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2601 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2602 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2603 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2604 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2605 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2606 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2607 2608 /* Enqueue and we're done... */ 2609 mutex_spin_enter(&sc->sc_mtx); 2610 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2611 ubsec_feed2(sc); 2612 ubsecstats.hst_modexp++; 2613 mutex_spin_exit(&sc->sc_mtx); 2614 2615 return (0); 2616 2617 errout: 2618 if (me != NULL) { 2619 if (me->me_q.q_mcr.dma_map != NULL) 2620 ubsec_dma_free(sc, &me->me_q.q_mcr); 2621 if (me->me_q.q_ctx.dma_map != NULL) { 2622 memset(me->me_q.q_ctx.dma_vaddr, 0, 2623 me->me_q.q_ctx.dma_size); 2624 ubsec_dma_free(sc, &me->me_q.q_ctx); 2625 } 2626 if (me->me_M.dma_map != NULL) { 2627 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2628 ubsec_dma_free(sc, &me->me_M); 2629 } 2630 if (me->me_E.dma_map != NULL) { 2631 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2632 ubsec_dma_free(sc, &me->me_E); 2633 } 2634 if (me->me_C.dma_map != NULL) { 2635 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2636 ubsec_dma_free(sc, &me->me_C); 2637 } 2638 if (me->me_epb.dma_map != NULL) 2639 ubsec_dma_free(sc, &me->me_epb); 2640 free(me, M_DEVBUF); 2641 } 2642 krp->krp_status = err; 2643 crypto_kdone(krp); 2644 return (0); 2645 } 2646 2647 /* 2648 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2649 */ 2650 static int 2651 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2652 int hint) 2653 { 2654 struct ubsec_q2_modexp *me; 2655 struct ubsec_mcr *mcr; 2656 struct ubsec_ctx_modexp *ctx; 2657 struct ubsec_pktbuf *epb; 2658 int err = 0; 2659 u_int nbits, normbits, mbits, shiftbits, ebits; 2660 2661 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2662 if (me == NULL) { 2663 err = ENOMEM; 2664 goto errout; 2665 } 2666 memset(me, 0, sizeof *me); 2667 me->me_krp = krp; 2668 me->me_q.q_type = UBS_CTXOP_MODEXP; 2669 2670 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2671 if (nbits <= 512) 2672 normbits = 512; 2673 else if (nbits <= 768) 2674 normbits = 768; 2675 else if (nbits <= 1024) 2676 normbits = 1024; 2677 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2678 normbits = 1536; 2679 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2680 normbits = 2048; 2681 else { 2682 err = E2BIG; 2683 goto errout; 2684 } 2685 2686 shiftbits = normbits - nbits; 2687 2688 /* XXX ??? */ 2689 me->me_modbits = nbits; 2690 me->me_shiftbits = shiftbits; 2691 me->me_normbits = normbits; 2692 2693 /* Sanity check: result bits must be >= true modulus bits. */ 2694 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2695 err = ERANGE; 2696 goto errout; 2697 } 2698 2699 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2700 &me->me_q.q_mcr, 0)) { 2701 err = ENOMEM; 2702 goto errout; 2703 } 2704 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2705 2706 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2707 &me->me_q.q_ctx, 0)) { 2708 err = ENOMEM; 2709 goto errout; 2710 } 2711 2712 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2713 if (mbits > nbits) { 2714 err = E2BIG; 2715 goto errout; 2716 } 2717 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2718 err = ENOMEM; 2719 goto errout; 2720 } 2721 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2722 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2723 me->me_M.dma_vaddr, (mbits + 7) / 8); 2724 2725 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2726 err = ENOMEM; 2727 goto errout; 2728 } 2729 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2730 2731 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2732 if (ebits > nbits) { 2733 err = E2BIG; 2734 goto errout; 2735 } 2736 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2737 err = ENOMEM; 2738 goto errout; 2739 } 2740 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2741 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2742 me->me_E.dma_vaddr, (ebits + 7) / 8); 2743 2744 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2745 &me->me_epb, 0)) { 2746 err = ENOMEM; 2747 goto errout; 2748 } 2749 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2750 epb->pb_addr = htole32(me->me_E.dma_paddr); 2751 epb->pb_next = 0; 2752 epb->pb_len = htole32((ebits + 7) / 8); 2753 2754 #ifdef UBSEC_DEBUG 2755 if (ubsec_debug) { 2756 printf("Epb "); 2757 ubsec_dump_pb(epb); 2758 } 2759 #endif 2760 2761 mcr->mcr_pkts = htole16(1); 2762 mcr->mcr_flags = 0; 2763 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2764 mcr->mcr_reserved = 0; 2765 mcr->mcr_pktlen = 0; 2766 2767 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2768 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2769 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2770 2771 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2772 mcr->mcr_opktbuf.pb_next = 0; 2773 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2774 2775 #ifdef DIAGNOSTIC 2776 /* Misaligned output buffer will hang the chip. */ 2777 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2778 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2779 letoh32(mcr->mcr_opktbuf.pb_addr)); 2780 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2781 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2782 letoh32(mcr->mcr_opktbuf.pb_len)); 2783 #endif 2784 2785 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2786 memset(ctx, 0, sizeof(*ctx)); 2787 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2788 (nbits + 7) / 8); 2789 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2790 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2791 ctx->me_E_len = htole16(ebits); 2792 ctx->me_N_len = htole16(nbits); 2793 2794 #ifdef UBSEC_DEBUG 2795 if (ubsec_debug) { 2796 ubsec_dump_mcr(mcr); 2797 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2798 } 2799 #endif 2800 2801 /* 2802 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2803 * everything else. 2804 */ 2805 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2806 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2807 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2808 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2809 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2810 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2811 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2812 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2813 2814 /* Enqueue and we're done... */ 2815 mutex_spin_enter(&sc->sc_mtx); 2816 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2817 ubsec_feed2(sc); 2818 mutex_spin_exit(&sc->sc_mtx); 2819 2820 return (0); 2821 2822 errout: 2823 if (me != NULL) { 2824 if (me->me_q.q_mcr.dma_map != NULL) 2825 ubsec_dma_free(sc, &me->me_q.q_mcr); 2826 if (me->me_q.q_ctx.dma_map != NULL) { 2827 memset(me->me_q.q_ctx.dma_vaddr, 0, 2828 me->me_q.q_ctx.dma_size); 2829 ubsec_dma_free(sc, &me->me_q.q_ctx); 2830 } 2831 if (me->me_M.dma_map != NULL) { 2832 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2833 ubsec_dma_free(sc, &me->me_M); 2834 } 2835 if (me->me_E.dma_map != NULL) { 2836 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2837 ubsec_dma_free(sc, &me->me_E); 2838 } 2839 if (me->me_C.dma_map != NULL) { 2840 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2841 ubsec_dma_free(sc, &me->me_C); 2842 } 2843 if (me->me_epb.dma_map != NULL) 2844 ubsec_dma_free(sc, &me->me_epb); 2845 free(me, M_DEVBUF); 2846 } 2847 krp->krp_status = err; 2848 crypto_kdone(krp); 2849 return (0); 2850 } 2851 2852 static int 2853 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2854 int hint) 2855 { 2856 struct ubsec_q2_rsapriv *rp = NULL; 2857 struct ubsec_mcr *mcr; 2858 struct ubsec_ctx_rsapriv *ctx; 2859 int err = 0; 2860 u_int padlen, msglen; 2861 2862 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2863 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2864 if (msglen > padlen) 2865 padlen = msglen; 2866 2867 if (padlen <= 256) 2868 padlen = 256; 2869 else if (padlen <= 384) 2870 padlen = 384; 2871 else if (padlen <= 512) 2872 padlen = 512; 2873 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2874 padlen = 768; 2875 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2876 padlen = 1024; 2877 else { 2878 err = E2BIG; 2879 goto errout; 2880 } 2881 2882 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2883 err = E2BIG; 2884 goto errout; 2885 } 2886 2887 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2888 err = E2BIG; 2889 goto errout; 2890 } 2891 2892 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2893 err = E2BIG; 2894 goto errout; 2895 } 2896 2897 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 2898 if (rp == NULL) 2899 return (ENOMEM); 2900 rp->rpr_krp = krp; 2901 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2902 2903 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2904 &rp->rpr_q.q_mcr, 0)) { 2905 err = ENOMEM; 2906 goto errout; 2907 } 2908 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2909 2910 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2911 &rp->rpr_q.q_ctx, 0)) { 2912 err = ENOMEM; 2913 goto errout; 2914 } 2915 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2916 memset(ctx, 0, sizeof *ctx); 2917 2918 /* Copy in p */ 2919 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2920 &ctx->rpr_buf[0 * (padlen / 8)], 2921 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2922 2923 /* Copy in q */ 2924 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2925 &ctx->rpr_buf[1 * (padlen / 8)], 2926 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2927 2928 /* Copy in dp */ 2929 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2930 &ctx->rpr_buf[2 * (padlen / 8)], 2931 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2932 2933 /* Copy in dq */ 2934 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2935 &ctx->rpr_buf[3 * (padlen / 8)], 2936 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2937 2938 /* Copy in pinv */ 2939 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2940 &ctx->rpr_buf[4 * (padlen / 8)], 2941 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2942 2943 msglen = padlen * 2; 2944 2945 /* Copy in input message (aligned buffer/length). */ 2946 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2947 /* Is this likely? */ 2948 err = E2BIG; 2949 goto errout; 2950 } 2951 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2952 err = ENOMEM; 2953 goto errout; 2954 } 2955 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 2956 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2957 rp->rpr_msgin.dma_vaddr, 2958 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2959 2960 /* Prepare space for output message (aligned buffer/length). */ 2961 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2962 /* Is this likely? */ 2963 err = E2BIG; 2964 goto errout; 2965 } 2966 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2967 err = ENOMEM; 2968 goto errout; 2969 } 2970 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 2971 2972 mcr->mcr_pkts = htole16(1); 2973 mcr->mcr_flags = 0; 2974 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2975 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2976 mcr->mcr_ipktbuf.pb_next = 0; 2977 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2978 mcr->mcr_reserved = 0; 2979 mcr->mcr_pktlen = htole16(msglen); 2980 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2981 mcr->mcr_opktbuf.pb_next = 0; 2982 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2983 2984 #ifdef DIAGNOSTIC 2985 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2986 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 2987 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 2988 (u_long) rp->rpr_msgin.dma_size); 2989 } 2990 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2991 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 2992 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 2993 (u_long) rp->rpr_msgout.dma_size); 2994 } 2995 #endif 2996 2997 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2998 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2999 ctx->rpr_q_len = htole16(padlen); 3000 ctx->rpr_p_len = htole16(padlen); 3001 3002 /* 3003 * ubsec_feed2 will sync mcr and ctx, we just need to sync 3004 * everything else. 3005 */ 3006 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 3007 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3008 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 3009 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 3010 3011 /* Enqueue and we're done... */ 3012 mutex_spin_enter(&sc->sc_mtx); 3013 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 3014 ubsec_feed2(sc); 3015 ubsecstats.hst_modexpcrt++; 3016 mutex_spin_exit(&sc->sc_mtx); 3017 return (0); 3018 3019 errout: 3020 if (rp != NULL) { 3021 if (rp->rpr_q.q_mcr.dma_map != NULL) 3022 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 3023 if (rp->rpr_msgin.dma_map != NULL) { 3024 memset(rp->rpr_msgin.dma_vaddr, 0, 3025 rp->rpr_msgin.dma_size); 3026 ubsec_dma_free(sc, &rp->rpr_msgin); 3027 } 3028 if (rp->rpr_msgout.dma_map != NULL) { 3029 memset(rp->rpr_msgout.dma_vaddr, 0, 3030 rp->rpr_msgout.dma_size); 3031 ubsec_dma_free(sc, &rp->rpr_msgout); 3032 } 3033 free(rp, M_DEVBUF); 3034 } 3035 krp->krp_status = err; 3036 crypto_kdone(krp); 3037 return (0); 3038 } 3039 3040 #ifdef UBSEC_DEBUG 3041 static void 3042 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 3043 { 3044 printf("addr 0x%x (0x%x) next 0x%x\n", 3045 pb->pb_addr, pb->pb_len, pb->pb_next); 3046 } 3047 3048 static void 3049 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 3050 { 3051 printf("CTX (0x%x):\n", c->ctx_len); 3052 switch (letoh16(c->ctx_op)) { 3053 case UBS_CTXOP_RNGBYPASS: 3054 case UBS_CTXOP_RNGSHA1: 3055 break; 3056 case UBS_CTXOP_MODEXP: 3057 { 3058 struct ubsec_ctx_modexp *cx = (void *)c; 3059 int i, len; 3060 3061 printf(" Elen %u, Nlen %u\n", 3062 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 3063 len = (cx->me_N_len + 7)/8; 3064 for (i = 0; i < len; i++) 3065 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 3066 printf("\n"); 3067 break; 3068 } 3069 default: 3070 printf("unknown context: %x\n", c->ctx_op); 3071 } 3072 printf("END CTX\n"); 3073 } 3074 3075 static void 3076 ubsec_dump_mcr(struct ubsec_mcr *mcr) 3077 { 3078 volatile struct ubsec_mcr_add *ma; 3079 int i; 3080 3081 printf("MCR:\n"); 3082 printf(" pkts: %u, flags 0x%x\n", 3083 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 3084 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 3085 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 3086 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 3087 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 3088 letoh16(ma->mcr_reserved)); 3089 printf(" %d: ipkt ", i); 3090 ubsec_dump_pb(&ma->mcr_ipktbuf); 3091 printf(" %d: opkt ", i); 3092 ubsec_dump_pb(&ma->mcr_opktbuf); 3093 ma++; 3094 } 3095 printf("END MCR\n"); 3096 } 3097 #endif /* UBSEC_DEBUG */ 3098 3099 /* 3100 * Return the number of significant bits of a big number. 3101 */ 3102 static int 3103 ubsec_ksigbits(struct crparam *cr) 3104 { 3105 u_int plen = (cr->crp_nbits + 7) / 8; 3106 int i, sig = plen * 8; 3107 u_int8_t c, *p = cr->crp_p; 3108 3109 for (i = plen - 1; i >= 0; i--) { 3110 c = p[i]; 3111 if (c != 0) { 3112 while ((c & 0x80) == 0) { 3113 sig--; 3114 c <<= 1; 3115 } 3116 break; 3117 } 3118 sig -= 8; 3119 } 3120 return (sig); 3121 } 3122 3123 static void 3124 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 3125 u_int8_t *dst, u_int dstbits) 3126 { 3127 u_int slen, dlen; 3128 int i, si, di, n; 3129 3130 slen = (srcbits + 7) / 8; 3131 dlen = (dstbits + 7) / 8; 3132 3133 for (i = 0; i < slen; i++) 3134 dst[i] = src[i]; 3135 for (i = 0; i < dlen - slen; i++) 3136 dst[slen + i] = 0; 3137 3138 n = shiftbits / 8; 3139 if (n != 0) { 3140 si = dlen - n - 1; 3141 di = dlen - 1; 3142 while (si >= 0) 3143 dst[di--] = dst[si--]; 3144 while (di >= 0) 3145 dst[di--] = 0; 3146 } 3147 3148 n = shiftbits % 8; 3149 if (n != 0) { 3150 for (i = dlen - 1; i > 0; i--) 3151 dst[i] = (dst[i] << n) | 3152 (dst[i - 1] >> (8 - n)); 3153 dst[0] = dst[0] << n; 3154 } 3155 } 3156 3157 static void 3158 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 3159 u_int8_t *dst, u_int dstbits) 3160 { 3161 int slen, dlen, i, n; 3162 3163 slen = (srcbits + 7) / 8; 3164 dlen = (dstbits + 7) / 8; 3165 3166 n = shiftbits / 8; 3167 for (i = 0; i < slen; i++) 3168 dst[i] = src[i + n]; 3169 for (i = 0; i < dlen - slen; i++) 3170 dst[slen + i] = 0; 3171 3172 n = shiftbits % 8; 3173 if (n != 0) { 3174 for (i = 0; i < (dlen - 1); i++) 3175 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 3176 dst[dlen - 1] = dst[dlen - 1] >> n; 3177 } 3178 } 3179