1 /* $NetBSD: twereg.h,v 1.12 2005/12/11 12:22:51 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twereg.h,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 #ifndef _PCI_TWEREG_H_ 69 #define _PCI_TWEREG_H_ 70 71 /* Board registers. */ 72 #define TWE_REG_CTL 0x00 73 #define TWE_REG_STS 0x04 74 #define TWE_REG_CMD_QUEUE 0x08 75 #define TWE_REG_RESP_QUEUE 0x0c 76 77 /* Control register bit definitions. */ 78 #define TWE_CTL_CLEAR_HOST_INTR 0x00080000 79 #define TWE_CTL_CLEAR_ATTN_INTR 0x00040000 80 #define TWE_CTL_MASK_CMD_INTR 0x00020000 81 #define TWE_CTL_MASK_RESP_INTR 0x00010000 82 #define TWE_CTL_UNMASK_CMD_INTR 0x00008000 83 #define TWE_CTL_UNMASK_RESP_INTR 0x00004000 84 #define TWE_CTL_CLEAR_ERROR_STS 0x00000200 85 #define TWE_CTL_ISSUE_SOFT_RESET 0x00000100 86 #define TWE_CTL_ENABLE_INTRS 0x00000080 87 #define TWE_CTL_DISABLE_INTRS 0x00000040 88 #define TWE_CTL_ISSUE_HOST_INTR 0x00000020 89 #define TWE_CTL_CLEAR_PARITY_ERROR 0x00800000 90 #define TWE_CTL_CLEAR_PCI_ABORT 0x00100000 91 92 /* Status register bit definitions. */ 93 #define TWE_STS_MAJOR_VERSION_MASK 0xf0000000 94 #define TWE_STS_MINOR_VERSION_MASK 0x0f000000 95 #define TWE_STS_PCI_PARITY_ERROR 0x00800000 96 #define TWE_STS_QUEUE_ERROR 0x00400000 97 #define TWE_STS_MICROCONTROLLER_ERROR 0x00200000 98 #define TWE_STS_PCI_ABORT 0x00100000 99 #define TWE_STS_HOST_INTR 0x00080000 100 #define TWE_STS_ATTN_INTR 0x00040000 101 #define TWE_STS_CMD_INTR 0x00020000 102 #define TWE_STS_RESP_INTR 0x00010000 103 #define TWE_STS_CMD_QUEUE_FULL 0x00008000 104 #define TWE_STS_RESP_QUEUE_EMPTY 0x00004000 105 #define TWE_STS_MICROCONTROLLER_READY 0x00002000 106 #define TWE_STS_CMD_QUEUE_EMPTY 0x00001000 107 108 #define TWE_STS_ALL_INTRS 0x000f0000 109 #define TWE_STS_CLEARABLE_BITS 0x00d00000 110 #define TWE_STS_EXPECTED_BITS 0x00002000 111 #define TWE_STS_UNEXPECTED_BITS 0x00f80000 112 113 /* Command packet opcodes. */ 114 #define TWE_OP_NOP 0x00 115 #define TWE_OP_INIT_CONNECTION 0x01 116 #define TWE_OP_READ 0x02 117 #define TWE_OP_WRITE 0x03 118 #define TWE_OP_READVERIFY 0x04 119 #define TWE_OP_VERIFY 0x05 120 #define TWE_OP_PROBE 0x06 121 #define TWE_OP_PROBEUNIT 0x07 122 #define TWE_OP_ZEROUNIT 0x08 123 #define TWE_OP_REPLACEUNIT 0x09 124 #define TWE_OP_HOTSWAP 0x0a 125 #define TWE_OP_SETATAFEATURE 0x0c 126 #define TWE_OP_FLUSH 0x0e 127 #define TWE_OP_ABORT 0x0f 128 #define TWE_OP_CHECKSTATUS 0x10 129 #define TWE_OP_ATA_PASSTHROUGH 0x11 130 #define TWE_OP_GET_PARAM 0x12 131 #define TWE_OP_SET_PARAM 0x13 132 #define TWE_OP_CREATEUNIT 0x14 133 #define TWE_OP_DELETEUNIT 0x15 134 #define TWE_OP_REBUILDUNIT 0x17 135 #define TWE_OP_SECTOR_INFO 0x1a 136 #define TWE_OP_AEN_LISTEN 0x1c 137 #define TWE_OP_CMD_PACKET 0x1d 138 #define TWE_OP_CMD_WITH_DATA 0x1f 139 140 /* Response queue entries. Masking and shifting yields request ID. */ 141 #define TWE_RESP_MASK 0x00000ff0 142 #define TWE_RESP_SHIFT 4 143 144 /* Miscellenous constants. */ 145 #define TWE_ALIGNMENT 512 146 #define TWE_MAX_UNITS 16 147 #define TWE_INIT_CMD_PACKET_SIZE 0x3 148 #define TWE_SG_SIZE 62 149 #define TWE_MAX_CMDS 255 150 #define TWE_Q_START 0 151 #define TWE_UNIT_INFORMATION_TABLE_BASE 0x300 152 #define TWE_IOCTL 0x80 153 #define TWE_SECTOR_SIZE 512 154 155 /* Scatter/gather block. */ 156 struct twe_sgb { 157 u_int32_t tsg_address; 158 u_int32_t tsg_length; 159 } __attribute__ ((packed)); 160 161 /* 162 * Command block. This is 512 (really 508) bytes in size, and must be 163 * aligned on a 512 byte boundary. 164 */ 165 struct twe_cmd { 166 u_int8_t tc_opcode; /* high 3 bits is S/G list offset */ 167 u_int8_t tc_size; 168 u_int8_t tc_cmdid; 169 u_int8_t tc_unit; /* high nybble is host ID */ 170 u_int8_t tc_status; 171 u_int8_t tc_flags; 172 u_int16_t tc_count; /* block & param count, msg credits */ 173 union { 174 struct { 175 u_int32_t lba; 176 struct twe_sgb sgl[TWE_SG_SIZE]; 177 } io __attribute__ ((packed)); 178 struct { 179 struct twe_sgb sgl[TWE_SG_SIZE]; 180 } param __attribute__ ((packed)); 181 struct { 182 u_int32_t response_queue_pointer; 183 } init_connection __attribute__ ((packed)); 184 } tc_args __attribute__ ((packed)); 185 int32_t tc_pad; 186 } __attribute__ ((packed)); 187 188 /* Get/set parameter block. */ 189 struct twe_param { 190 u_int16_t tp_table_id; 191 u_int8_t tp_param_id; 192 u_int8_t tp_param_size; 193 u_int8_t tp_data[1]; 194 } __attribute__ ((packed)); 195 196 /* 197 * From 3ware's documentation: 198 * 199 * All parameters maintained by the controller are grouped into related 200 * tables. Tables are are accessed indirectly via get and set parameter 201 * commands. To access a specific parameter in a table, the table ID and 202 * parameter index are used to uniquely identify a parameter. Table 203 * 0xffff is the directory table and provides a list of the table IDs and 204 * sizes of all other tables. Index zero in each table specifies the 205 * entire table, and index one specifies the size of the table. An entire 206 * table can be read or set by using index zero. 207 */ 208 209 #define TWE_PARAM_PARAM_ALL 0 210 #define TWE_PARAM_PARAM_SIZE 1 211 212 #define TWE_PARAM_DIRECTORY 0xffff /* size is 4 * number of tables */ 213 #define TWE_PARAM_DIRECTORY_TABLES 2 /* 16 bits * number of tables */ 214 #define TWE_PARAM_DIRECTORY_SIZES 3 /* 16 bits * number of tables */ 215 216 #define TWE_PARAM_DRIVESUMMARY 0x0002 217 #define TWE_PARAM_DRIVESUMMARY_Num 2 /* number of physical drives [2] */ 218 #define TWE_PARAM_DRIVESUMMARY_Status 3 /* array giving drive status per aport */ 219 #define TWE_PARAM_DRIVESTATUS_Missing 0x00 220 #define TWE_PARAM_DRIVESTATUS_NotSupp 0xfe 221 #define TWE_PARAM_DRIVESTATUS_Present 0xff 222 223 #define TWE_PARAM_UNITSUMMARY 0x0003 224 #define TWE_PARAM_UNITSUMMARY_Num 2 /* number of logical units [2] */ 225 #define TWE_PARAM_UNITSUMMARY_Status 3 /* array giving unit status [16] */ 226 #define TWE_PARAM_UNITSTATUS_Online (1<<0) 227 #define TWE_PARAM_UNITSTATUS_Complete (1<<1) 228 #define TWE_PARAM_UNITSTATUS_MASK 0xfc 229 #define TWE_PARAM_UNITSTATUS_Normal 0xfc 230 #define TWE_PARAM_UNITSTATUS_Initialising 0xf4 /* cannot be incomplete */ 231 #define TWE_PARAM_UNITSTATUS_Degraded 0xec 232 #define TWE_PARAM_UNITSTATUS_Rebuilding 0xdc /* cannot be incomplete */ 233 #define TWE_PARAM_UNITSTATUS_Verifying 0xcc /* cannot be incomplete */ 234 #define TWE_PARAM_UNITSTATUS_Corrupt 0xbc /* cannot be complete */ 235 #define TWE_PARAM_UNITSTATUS_Missing 0x00 /* cannot be complete or online */ 236 237 #define TWE_PARAM_DRIVEINFO 0x0200 /* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */ 238 #define TWE_PARAM_DRIVEINFO_Size 2 /* size in blocks [4] */ 239 #define TWE_PARAM_DRIVEINFO_Model 3 /* drive model string [40] */ 240 #define TWE_PARAM_DRIVEINFO_Serial 4 /* drive serial number [20] */ 241 #define TWE_PARAM_DRIVEINFO_PhysCylNum 5 /* physical geometry [2] */ 242 #define TWE_PARAM_DRIVEINFO_PhysHeadNum 6 /* [2] */ 243 #define TWE_PARAM_DRIVEINFO_PhysSectorNum 7 /* [2] */ 244 #define TWE_PARAM_DRIVEINFO_LogCylNum 8 /* logical geometry [2] */ 245 #define TWE_PARAM_DRIVEINFO_LogHeadNum 9 /* [2] */ 246 #define TWE_PARAM_DRIVEINFO_LogSectorNum 10 /* [2] */ 247 #define TWE_PARAM_DRIVEINFO_UnitNum 11 /* unit number this drive is associated with or 0xff [1] */ 248 #define TWE_PARAM_DRIVEINFO_DriveFlags 12 /* N/A [1] */ 249 250 #define TWE_PARAM_APORTTIMEOUT 0x02c0 /* add (aport_number * 3) to parameter index */ 251 #define TWE_PARAM_APORTTIMEOUT_READ 2 /* read timeouts last 24hrs [2] */ 252 #define TWE_PARAM_APORTTIMEOUT_WRITE 3 /* write timeouts last 24hrs [2] */ 253 #define TWE_PARAM_APORTTIMEOUT_DEGRADE 4 /* degrade threshold [2] */ 254 255 #define TWE_PARAM_UNITINFO 0x0300 /* add unit number 0x00-0x0f */ 256 #define TWE_PARAM_UNITINFO_Number 2 /* unit number [1] */ 257 #define TWE_PARAM_UNITINFO_Status 3 /* unit status [1] */ 258 #define TWE_PARAM_UNITINFO_Capacity 4 /* unit capacity in blocks [4] */ 259 #define TWE_PARAM_UNITINFO_DescriptorSize 5 /* unit descriptor size + 3 bytes [2] */ 260 #define TWE_PARAM_UNITINFO_Descriptor 6 /* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */ 261 #define TWE_PARAM_UNITINFO_Flags 7 /* unit flags [1] */ 262 #define TWE_PARAM_UNITFLAGS_WCE (1<<0) 263 264 #define TWE_PARAM_AEN 0x0401 265 #define TWE_PARAM_AEN_UnitCode 2 /* (unit number << 8) | AEN code [2] */ 266 #define TWE_AEN_QUEUE_EMPTY 0x00 267 #define TWE_AEN_SOFT_RESET 0x01 268 #define TWE_AEN_DEGRADED_MIRROR 0x02 /* reports unit */ 269 #define TWE_AEN_CONTROLLER_ERROR 0x03 270 #define TWE_AEN_REBUILD_FAIL 0x04 /* reports unit */ 271 #define TWE_AEN_REBUILD_DONE 0x05 /* reports unit */ 272 #define TWE_AEN_INCOMP_UNIT 0x06 /* reports unit */ 273 #define TWE_AEN_INIT_DONE 0x07 /* reports unit */ 274 #define TWE_AEN_UNCLEAN_SHUTDOWN 0x08 /* reports unit */ 275 #define TWE_AEN_APORT_TIMEOUT 0x09 /* reports unit, rate limited to 1 per 2^16 errors */ 276 #define TWE_AEN_DRIVE_ERROR 0x0a /* reports unit */ 277 #define TWE_AEN_REBUILD_STARTED 0x0b /* reports unit */ 278 #define TWE_AEN_QUEUE_FULL 0xff 279 #define TWE_AEN_TABLE_UNDEFINED 0x15 280 #define TWE_AEN_CODE(x) ((x) & 0xff) 281 #define TWE_AEN_UNIT(x) ((x) >> 8) 282 283 #define TWE_PARAM_VERSION 0x0402 284 #define TWE_PARAM_VERSION_Mon 2 /* monitor version [16] */ 285 #define TWE_PARAM_VERSION_FW 3 /* firmware version [16] */ 286 #define TWE_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 287 #define TWE_PARAM_VERSION_PCB 5 /* PCB version [8] */ 288 #define TWE_PARAM_VERSION_ATA 6 /* A-chip version [8] */ 289 #define TWE_PARAM_VERSION_PCI 7 /* P-chip version [8] */ 290 #define TWE_PARAM_VERSION_CtrlModel 8 /* N/A */ 291 #define TWE_PARAM_VERSION_CtrlSerial 9 /* N/A */ 292 #define TWE_PARAM_VERSION_SBufSize 10 /* N/A */ 293 #define TWE_PARAM_VERSION_CompCode 11 /* compatibility code [4] */ 294 295 #define TWE_PARAM_CONTROLLER 0x0403 296 #define TWE_PARAM_CONTROLLER_DCBSectors 2 /* # sectors reserved for DCB per drive [2] */ 297 #define TWE_PARAM_CONTROLLER_PortCount 3 /* number of drive ports [1] */ 298 299 #define TWE_PARAM_FEATURES 0x404 300 #define TWE_PARAM_FEATURES_DriverShutdown 2 /* set to 1 if driver supports shutdown notification [1] */ 301 302 #define TWE_PARAM_PROC 0x406 303 #define TWE_PARAM_PROC_PERCENT 2 /* Per-sub-unit % complete of init/verify/rebuild or 0xff [16] */ 304 305 struct twe_unit_descriptor { 306 u_int8_t num_subunits; /* must be zero */ 307 u_int8_t configuration; 308 #define TWE_UD_CONFIG_CBOD 0x0c /* JBOD with DCB, used for mirrors */ 309 #define TWE_UD_CONFIG_SPARE 0x0d /* same as CBOD, but firmware will use as spare */ 310 #define TWE_UD_CONFIG_SUBUNIT 0x0e /* drive is a subunit in an array */ 311 #define TWE_UD_CONFIG_JBOD 0x0f /* plain drive */ 312 u_int8_t phys_drv_num; /* may be 0xff if port can't be determined at runtime */ 313 u_int8_t log_drv_num; /* must be zero for configuration == 0x0f */ 314 u_int32_t start_lba; 315 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */ 316 } __attribute__ ((packed)); 317 318 struct twe_mirror_descriptor { 319 u_int8_t flag; /* must be 0xff */ 320 u_int8_t res1; 321 u_int8_t mirunit_status[4]; /* bitmap of functional subunits in each mirror */ 322 u_int8_t res2[6]; 323 } __attribute__ ((packed)); 324 325 struct twe_array_descriptor { 326 u_int8_t num_subunits; /* number of subunits, or number of mirror units in RAID10 */ 327 u_int8_t configuration; 328 #define TWE_AD_CONFIG_RAID0 0x00 329 #define TWE_AD_CONFIG_RAID1 0x01 330 #define TWE_AD_CONFIG_TwinStor 0x02 331 #define TWE_AD_CONFIG_RAID5 0x05 332 #define TWE_AD_CONFIG_RAID10 0x06 333 u_int8_t stripe_size; 334 #define TWE_AD_STRIPE_4k 0x03 335 #define TWE_AD_STRIPE_8k 0x04 336 #define TWE_AD_STRIPE_16k 0x05 337 #define TWE_AD_STRIPE_32k 0x06 338 #define TWE_AD_STRIPE_64k 0x07 339 #define TWE_AD_STRIPE_128k 0x08 340 #define TWE_AD_STRIPE_256k 0x09 341 #define TWE_AD_STRIPE_512k 0x0a 342 #define TWE_AD_STRIPE_1024k 0x0b 343 u_int8_t log_drv_status; /* bitmap of functional subunits, or mirror units in RAID10 */ 344 u_int32_t start_lba; 345 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */ 346 struct twe_unit_descriptor subunit[1]; 347 } __attribute__ ((packed)); 348 349 #endif /* !_PCI_TWEREG_H_ */ 350