1 /* $NetBSD: trm.c,v 1.4 2001/11/13 07:48:49 lukem Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2001 Rui-Xiang Guo 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from 34 * dc395x_trm.c 35 * 36 * Written for NetBSD 1.4.x by 37 * Erich Chen (erich@tekram.com.tw) 38 * 39 * Provided by 40 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.4 2001/11/13 07:48:49 lukem Exp $"); 45 46 /* #define TRM_DEBUG */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/malloc.h> 51 #include <sys/buf.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <dev/scsipi/scsi_all.h> 61 #include <dev/scsipi/scsi_message.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/pci/pcidevs.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/trmreg.h> 69 70 /* 71 * feature of chip set MAX value 72 */ 73 #define TRM_MAX_TARGETS 16 74 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 75 #define TRM_MAX_SRB 32 76 77 /* 78 * Segment Entry 79 */ 80 struct trm_sg_entry { 81 u_int32_t address; 82 u_int32_t length; 83 }; 84 85 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 86 87 /* 88 ********************************************************************** 89 * The SEEPROM structure for TRM_S1040 90 ********************************************************************** 91 */ 92 struct nvram_target { 93 u_int8_t config0; /* Target configuration byte 0 */ 94 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 95 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 96 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 97 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 98 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 99 #define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC) Parity check enable */ 100 u_int8_t period; /* Target period */ 101 u_int8_t config2; /* Target configuration byte 2 */ 102 u_int8_t config3; /* Target configuration byte 3 */ 103 }; 104 105 struct trm_nvram { 106 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 107 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 108 u_int8_t subclass; /* 4 Sub Class */ 109 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 110 u_int8_t device_id[2]; /* 7,8 Device ID */ 111 u_int8_t reserved0; /* 9 Reserved */ 112 struct nvram_target target[TRM_MAX_TARGETS]; 113 /* 10,11,12,13 114 * 14,15,16,17 115 * .... 116 * 70,71,72,73 */ 117 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 118 u_int8_t channel_cfg; /* 75 Channel configuration */ 119 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 120 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 121 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 122 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 123 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 124 u_int8_t delay_time; /* 76 Power on delay time */ 125 u_int8_t max_tag; /* 77 Maximum tags */ 126 u_int8_t reserved1; /* 78 */ 127 u_int8_t boot_target; /* 79 */ 128 u_int8_t boot_lun; /* 80 */ 129 u_int8_t reserved2; /* 81 */ 130 u_int8_t reserved3[44]; /* 82,..125 */ 131 u_int8_t checksum0; /* 126 */ 132 u_int8_t checksum1; /* 127 */ 133 #define TRM_NVRAM_CKSUM 0x1234 134 }; 135 136 /* Nvram Initiater bits definition */ 137 #define MORE2_DRV 0x00000001 138 #define GREATER_1G 0x00000002 139 #define RST_SCSI_BUS 0x00000004 140 #define ACTIVE_NEGATION 0x00000008 141 #define NO_SEEK 0x00000010 142 #define LUN_CHECK 0x00000020 143 144 #define trm_wait_30us() DELAY(30) 145 146 /* 147 *----------------------------------------------------------------------- 148 * SCSI Request Block 149 *----------------------------------------------------------------------- 150 */ 151 struct trm_srb { 152 struct trm_srb *next; 153 struct trm_dcb *dcb; 154 155 struct trm_sg_entry *sgentry; 156 struct trm_sg_entry tempsg; /* Temp sgentry when Request Sense */ 157 /* 158 * the scsipi_xfer for this cmd 159 */ 160 struct scsipi_xfer *xs; 161 bus_dmamap_t dmap; 162 bus_size_t sgoffset; /* Xfer buf offset */ 163 164 u_int32_t buflen; /* Total xfer length */ 165 u_int32_t templen; /* Temp buflen when Request Sense */ 166 u_int32_t sgaddr; /* SGList physical starting address */ 167 168 u_int state; /* SRB State */ 169 #define SRB_FREE 0x0000 170 #define SRB_WAIT 0x0001 171 #define SRB_READY 0x0002 172 #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */ 173 #define SRB_MSGIN 0x0008 174 #define SRB_EXTEND_MSGIN 0x0010 175 #define SRB_COMMAND 0x0020 176 #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */ 177 #define SRB_DISCONNECT 0x0080 178 #define SRB_DATA_XFER 0x0100 179 #define SRB_XFERPAD 0x0200 180 #define SRB_STATUS 0x0400 181 #define SRB_COMPLETED 0x0800 182 #define SRB_ABORT_SENT 0x1000 183 #define SRB_DO_SYNC_NEGO 0x2000 184 #define SRB_DO_WIDE_NEGO 0x4000 185 #define SRB_UNEXPECT_RESEL 0x8000 186 u_int8_t *msg; 187 188 int sgcnt; 189 int sgindex; 190 191 int phase; /* SCSI phase */ 192 int hastat; /* Host Adapter Status */ 193 #define H_STATUS_GOOD 0x00 194 #define H_SEL_TIMEOUT 0x11 195 #define H_OVER_UNDER_RUN 0x12 196 #define H_UNEXP_BUS_FREE 0x13 197 #define H_TARGET_PHASE_F 0x14 198 #define H_INVALID_CCB_OP 0x16 199 #define H_LINK_CCB_BAD 0x17 200 #define H_BAD_TARGET_DIR 0x18 201 #define H_DUPLICATE_CCB 0x19 202 #define H_BAD_CCB_OR_SG 0x1A 203 #define H_ABORT 0xFF 204 int tastat; /* Target SCSI Status Byte */ 205 int flag; /* SRBFlag */ 206 #define DATAOUT 0x0080 207 #define DATAIN 0x0040 208 #define RESIDUAL_VALID 0x0020 209 #define ENABLE_TIMER 0x0010 210 #define RESET_DEV0 0x0004 211 #define ABORT_DEV 0x0002 212 #define AUTO_REQSENSE 0x0001 213 int srbstat; /* SRB Status */ 214 #define SRB_OK 0x01 215 #define ABORTION 0x02 216 #define OVER_RUN 0x04 217 #define UNDER_RUN 0x08 218 #define PARITY_ERROR 0x10 219 #define SRB_ERROR 0x20 220 int tagnum; /* Tag number */ 221 int retry; /* Retry Count */ 222 int msgcnt; 223 224 int cmdlen; /* SCSI command length */ 225 u_int8_t cmd[12]; /* SCSI command */ 226 u_int8_t tempcmd[6]; /* Temp cmd when Request Sense */ 227 228 u_int8_t msgin[6]; 229 u_int8_t msgout[6]; 230 }; 231 232 /* 233 *----------------------------------------------------------------------- 234 * Device Control Block 235 *----------------------------------------------------------------------- 236 */ 237 struct trm_dcb { 238 struct trm_dcb *next; 239 240 struct trm_srb *waitsrb; 241 struct trm_srb *last_waitsrb; 242 243 struct trm_srb *gosrb; 244 struct trm_srb *last_gosrb; 245 246 struct trm_srb *actsrb; 247 248 int gosrb_cnt; 249 u_int maxcmd; /* Max command */ 250 251 int id; /* SCSI Target ID (SCSI Only) */ 252 int lun; /* SCSI Log. Unit (SCSI Only) */ 253 254 u_int8_t tagmask; /* Tag mask */ 255 256 u_int8_t tacfg; /* Target Config */ 257 u_int8_t idmsg; /* Identify Msg */ 258 u_int8_t period; /* Max Period for nego. */ 259 260 u_int8_t synctl; /* Sync control for reg. */ 261 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 262 u_int8_t mode; /* Sync mode ? (1 sync):(0 async) */ 263 #define SYNC_NEGO_ENABLE 0x01 264 #define SYNC_NEGO_DONE 0x02 265 #define WIDE_NEGO_ENABLE 0x04 266 #define WIDE_NEGO_DONE 0x08 267 #define EN_TAG_QUEUING 0x10 268 #define EN_ATN_STOP 0x20 269 #define SYNC_NEGO_OFFSET 15 270 u_int8_t flag; 271 #define ABORT_DEV_ 0x01 272 #define SHOW_MESSAGE_ 0x02 273 u_int8_t type; /* Device Type */ 274 }; 275 276 /* 277 *----------------------------------------------------------------------- 278 * Adapter Control Block 279 *----------------------------------------------------------------------- 280 */ 281 struct trm_softc { 282 struct device sc_dev; 283 284 bus_space_tag_t sc_iot; 285 bus_space_handle_t sc_ioh; 286 bus_dma_tag_t sc_dmat; 287 bus_dmamap_t sc_dmamap; /* Map the control structures */ 288 289 struct trm_dcb *sc_linkdcb; 290 struct trm_dcb *sc_roundcb; 291 292 struct trm_dcb *sc_actdcb; 293 struct trm_dcb *sc_dcb[TRM_MAX_TARGETS][8]; 294 295 struct trm_srb *sc_freesrb; 296 struct trm_srb *sc_srb; /* SRB array */ 297 struct trm_srb sc_tempsrb; 298 299 struct trm_sg_entry *sc_sglist; 300 301 int maxid; 302 int maxtag; /* Max Tag number */ 303 /* 304 * Link to the generic SCSI driver 305 */ 306 struct scsipi_channel sc_channel; 307 struct scsipi_adapter sc_adapter; 308 309 int sc_id; /* Adapter SCSI Target ID */ 310 311 int devcnt; /* Device Count */ 312 313 int devflag[TRM_MAX_TARGETS][8]; /* flag of initDCB for device */ 314 315 int devscan[TRM_MAX_TARGETS][8]; 316 int devscan_end; 317 int cur_offset; /* Current Sync offset */ 318 319 struct trm_nvram sc_eeprom; 320 int sc_config; 321 #define HCC_WIDE_CARD 0x20 322 #define HCC_SCSI_RESET 0x10 323 #define HCC_PARITY 0x08 324 #define HCC_AUTOTERM 0x04 325 #define HCC_LOW8TERM 0x02 326 #define HCC_UP8TERM 0x01 327 int sc_flag; 328 #define RESET_DEV 0x01 329 #define RESET_DETECT 0x02 330 #define RESET_DONE 0x04 331 }; 332 333 /* 334 * SCSI Status codes not defined in scsi_all.h 335 */ 336 #define SCSI_COND_MET 0x04 /* Condition Met */ 337 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 338 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpect Bus Free */ 339 #define SCSI_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */ 340 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Time out */ 341 342 static void trm_rewait_srb(struct trm_dcb *, struct trm_srb *); 343 static void trm_wait_srb(struct trm_softc *); 344 static void trm_reset_device(struct trm_softc *); 345 static void trm_recover_srb(struct trm_softc *); 346 static int trm_start_scsi(struct trm_softc *, struct trm_dcb *, 347 struct trm_srb *); 348 static int trm_intr(void *); 349 350 static void trm_dataout_phase0(struct trm_softc *, struct trm_srb *, int *); 351 static void trm_datain_phase0(struct trm_softc *, struct trm_srb *, int *); 352 static void trm_command_phase0(struct trm_softc *, struct trm_srb *, int *); 353 static void trm_status_phase0(struct trm_softc *, struct trm_srb *, int *); 354 static void trm_msgout_phase0(struct trm_softc *, struct trm_srb *, int *); 355 static void trm_msgin_phase0(struct trm_softc *, struct trm_srb *, int *); 356 static void trm_dataout_phase1(struct trm_softc *, struct trm_srb *, int *); 357 static void trm_datain_phase1(struct trm_softc *, struct trm_srb *, int *); 358 static void trm_command_phase1(struct trm_softc *, struct trm_srb *, int *); 359 static void trm_status_phase1(struct trm_softc *, struct trm_srb *, int *); 360 static void trm_msgout_phase1(struct trm_softc *, struct trm_srb *, int *); 361 static void trm_msgin_phase1(struct trm_softc *, struct trm_srb *, int *); 362 static void trm_nop0(struct trm_softc *, struct trm_srb *, int *); 363 static void trm_nop1(struct trm_softc *, struct trm_srb *, int *); 364 365 static void trm_set_xfer_rate(struct trm_softc *, struct trm_srb *, 366 struct trm_dcb *); 367 static void trm_dataio_xfer(struct trm_softc *, struct trm_srb *, int); 368 static void trm_disconnect(struct trm_softc *); 369 static void trm_reselect(struct trm_softc *); 370 static void trm_srb_done(struct trm_softc *, struct trm_dcb *, 371 struct trm_srb *); 372 static void trm_doing_srb_done(struct trm_softc *); 373 static void trm_scsi_reset_detect(struct trm_softc *); 374 static void trm_reset_scsi_bus(struct trm_softc *); 375 static void trm_request_sense(struct trm_softc *, struct trm_dcb *, 376 struct trm_srb *); 377 static void trm_msgout_abort(struct trm_softc *, struct trm_srb *); 378 static void trm_timeout(void *); 379 static void trm_reset(struct trm_softc *); 380 static void trm_send_srb(struct scsipi_xfer *, struct trm_softc *, 381 struct trm_srb *); 382 static int trm_init(struct trm_softc *); 383 static void trm_init_adapter(struct trm_softc *); 384 static void trm_init_dcb(struct trm_softc *, struct trm_dcb *, 385 struct scsipi_xfer *); 386 static void trm_link_srb(struct trm_softc *); 387 static void trm_init_sc(struct trm_softc *); 388 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 389 static void trm_release_srb(struct trm_softc *, struct trm_dcb *, 390 struct trm_srb *); 391 void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *); 392 393 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 394 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 395 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 396 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 397 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 398 399 static int trm_probe(struct device *, struct cfdata *, void *); 400 static void trm_attach(struct device *, struct device *, void *); 401 402 struct cfattach trm_ca = { 403 sizeof(struct trm_softc), trm_probe, trm_attach 404 }; 405 406 407 /* 408 * state_v = (void *) trm_scsi_phase0[phase] 409 */ 410 static void *trm_scsi_phase0[] = { 411 trm_dataout_phase0, /* phase:0 */ 412 trm_datain_phase0, /* phase:1 */ 413 trm_command_phase0, /* phase:2 */ 414 trm_status_phase0, /* phase:3 */ 415 trm_nop0, /* phase:4 */ 416 trm_nop1, /* phase:5 */ 417 trm_msgout_phase0, /* phase:6 */ 418 trm_msgin_phase0, /* phase:7 */ 419 }; 420 421 /* 422 * state_v = (void *) trm_scsi_phase1[phase] 423 */ 424 static void *trm_scsi_phase1[] = { 425 trm_dataout_phase1, /* phase:0 */ 426 trm_datain_phase1, /* phase:1 */ 427 trm_command_phase1, /* phase:2 */ 428 trm_status_phase1, /* phase:3 */ 429 trm_nop0, /* phase:4 */ 430 trm_nop1, /* phase:5 */ 431 trm_msgout_phase1, /* phase:6 */ 432 trm_msgin_phase1, /* phase:7 */ 433 }; 434 435 /* real period: */ 436 static const u_int8_t trm_clock_period[] = { 437 13, /* 52 ns 20.0 MB/sec */ 438 18, /* 72 ns 13.3 MB/sec */ 439 25, /* 100 ns 10.0 MB/sec */ 440 31, /* 124 ns 8.0 MB/sec */ 441 37, /* 148 ns 6.6 MB/sec */ 442 43, /* 172 ns 5.7 MB/sec */ 443 50, /* 200 ns 5.0 MB/sec */ 444 62 /* 248 ns 4.0 MB/sec */ 445 }; 446 447 /* 448 * Q back to pending Q 449 */ 450 static void 451 trm_rewait_srb(dcb, srb) 452 struct trm_dcb *dcb; 453 struct trm_srb *srb; 454 { 455 struct trm_srb *psrb1; 456 int s; 457 458 s = splbio(); 459 460 dcb->gosrb_cnt--; 461 psrb1 = dcb->gosrb; 462 if (srb == psrb1) 463 dcb->gosrb = psrb1->next; 464 else { 465 while (srb != psrb1->next) 466 psrb1 = psrb1->next; 467 468 psrb1->next = srb->next; 469 if (srb == dcb->last_gosrb) 470 dcb->last_gosrb = psrb1; 471 } 472 if (dcb->waitsrb) { 473 srb->next = dcb->waitsrb; 474 dcb->waitsrb = srb; 475 } else { 476 srb->next = NULL; 477 dcb->waitsrb = srb; 478 dcb->last_waitsrb = srb; 479 } 480 dcb->tagmask &= ~(1 << srb->tagnum); /* Free TAG number */ 481 482 splx(s); 483 } 484 485 static void 486 trm_wait_srb(sc) 487 struct trm_softc *sc; 488 { 489 struct trm_dcb *ptr, *ptr1; 490 struct trm_srb *srb; 491 int s; 492 493 s = splbio(); 494 495 if (sc->sc_actdcb == NULL && 496 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) == 0) { 497 ptr = sc->sc_roundcb; 498 if (ptr == NULL) { 499 ptr = sc->sc_linkdcb; 500 sc->sc_roundcb = ptr; 501 } 502 for (ptr1 = ptr; ptr1 != NULL;) { 503 sc->sc_roundcb = ptr1->next; 504 if (ptr1->maxcmd <= ptr1->gosrb_cnt || 505 (srb = ptr1->waitsrb) == NULL) { 506 if (sc->sc_roundcb == ptr) 507 break; 508 ptr1 = ptr1->next; 509 } else { 510 if (trm_start_scsi(sc, ptr1, srb) == 0) { 511 /* 512 * If trm_start_scsi return 0 : 513 * current interrupt status is 514 * interrupt enable. It's said that 515 * SCSI processor is unoccupied 516 */ 517 ptr1->gosrb_cnt++; 518 if (ptr1->last_waitsrb == srb) { 519 ptr1->waitsrb = NULL; 520 ptr1->last_waitsrb = NULL; 521 } else 522 ptr1->waitsrb = srb->next; 523 524 srb->next = NULL; 525 if (ptr1->gosrb != NULL) 526 ptr1->last_gosrb->next = srb; 527 else 528 ptr1->gosrb = srb; 529 530 ptr1->last_gosrb = srb; 531 } 532 break; 533 } 534 } 535 } 536 splx(s); 537 } 538 539 static void 540 trm_send_srb(xs, sc, srb) 541 struct scsipi_xfer *xs; 542 struct trm_softc *sc; 543 struct trm_srb *srb; 544 { 545 struct trm_dcb *dcb; 546 int s; 547 548 #ifdef TRM_DEBUG 549 printf("trm_send_srb..........\n"); 550 #endif 551 s = splbio(); 552 553 /* 554 * now get the DCB from upper layer( OS ) 555 */ 556 dcb = srb->dcb; 557 558 if (dcb->maxcmd <= dcb->gosrb_cnt || 559 sc->sc_actdcb != NULL || 560 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV))) { 561 if (dcb->waitsrb != NULL) { 562 dcb->last_waitsrb->next = srb; 563 dcb->last_waitsrb = srb; 564 srb->next = NULL; 565 } else { 566 dcb->waitsrb = srb; 567 dcb->last_waitsrb = srb; 568 } 569 splx(s); 570 return; 571 } 572 if (dcb->waitsrb != NULL) { 573 dcb->last_waitsrb->next = srb; 574 dcb->last_waitsrb = srb; 575 srb->next = NULL; 576 /* srb = GetWaitingSRB(dcb); */ 577 srb = dcb->waitsrb; 578 dcb->waitsrb = srb->next; 579 srb->next = NULL; 580 } 581 if (trm_start_scsi(sc, dcb, srb) == 0) { 582 /* 583 * If trm_start_scsi return 0: current interrupt status 584 * is interrupt enable. It's said that SCSI processor is 585 * unoccupied. 586 */ 587 dcb->gosrb_cnt++; /* stack waiting SRB */ 588 if (dcb->gosrb != NULL) { 589 dcb->last_gosrb->next = srb; 590 dcb->last_gosrb = srb; 591 } else { 592 dcb->gosrb = srb; 593 dcb->last_gosrb = srb; 594 } 595 } else { 596 /* 597 * If trm_start_scsi return 1: current interrupt status 598 * is interrupt disreenable. It's said that SCSI processor 599 * has more one SRB need to do we need reQ back SRB. 600 */ 601 if (dcb->waitsrb != NULL) { 602 srb->next = dcb->waitsrb; 603 dcb->waitsrb = srb; 604 } else { 605 srb->next = NULL; 606 dcb->waitsrb = srb; 607 dcb->last_waitsrb = srb; 608 } 609 } 610 611 splx(s); 612 } 613 614 /* 615 * Called by GENERIC SCSI driver 616 * enqueues a SCSI command 617 */ 618 void 619 trm_scsipi_request(chan, req, arg) 620 struct scsipi_channel *chan; 621 scsipi_adapter_req_t req; 622 void *arg; 623 { 624 bus_space_tag_t iot; 625 bus_space_handle_t ioh; 626 struct trm_softc *sc; 627 struct trm_dcb *dcb = NULL; 628 struct trm_srb *srb; 629 struct scsipi_xfer *xs; 630 int error, i, id, lun, s; 631 632 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 633 iot = sc->sc_iot; 634 ioh = sc->sc_ioh; 635 636 switch (req) { 637 case ADAPTER_REQ_RUN_XFER: 638 xs = arg; 639 id = xs->xs_periph->periph_target; 640 lun = xs->xs_periph->periph_lun; 641 #ifdef TRM_DEBUG 642 printf("trm_scsipi_request.....\n"); 643 printf("%s: id= %d lun= %d\n", sc->sc_dev.dv_xname, id, lun); 644 printf("sc->devscan[id][lun]= %d\n", sc->devscan[id][lun]); 645 #endif 646 if ((id > sc->maxid) || (lun > 7)) { 647 xs->error = XS_DRIVER_STUFFUP; 648 return; 649 } 650 dcb = sc->sc_dcb[id][lun]; 651 if (sc->devscan[id][lun] != 0 && sc->devflag[id][lun] == 0) { 652 /* 653 * Scan SCSI BUS => trm_init_dcb 654 */ 655 if (sc->devcnt < TRM_MAX_TARGETS) { 656 #ifdef TRM_DEBUG 657 printf("trm_init_dcb: dcb=%8x, ", (int) dcb); 658 printf("ID=%2x, LUN=%2x\n", id, lun); 659 #endif 660 sc->devflag[id][lun] = 1; 661 trm_init_dcb(sc, dcb, xs); 662 } else { 663 printf("%s: ", sc->sc_dev.dv_xname); 664 printf("sc->devcnt >= TRM_MAX_TARGETS\n"); 665 xs->error = XS_DRIVER_STUFFUP; 666 return; 667 } 668 } 669 670 if (xs->xs_control & XS_CTL_RESET) { 671 trm_reset(sc); 672 xs->error = XS_NOERROR | XS_RESET; 673 return; 674 } 675 if (xs->xs_status & XS_STS_DONE) { 676 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 677 xs->xs_status &= ~XS_STS_DONE; 678 } 679 xs->error = 0; 680 xs->status = 0; 681 xs->resid = 0; 682 683 s = splbio(); 684 685 /* Get SRB */ 686 srb = sc->sc_freesrb; 687 if (srb != NULL) { 688 sc->sc_freesrb = srb->next; 689 srb->next = NULL; 690 #ifdef TRM_DEBUG 691 printf("srb = %8p sc->sc_freesrb= %8p\n", 692 srb, sc->sc_freesrb); 693 #endif 694 } else { 695 xs->error = XS_RESOURCE_SHORTAGE; 696 scsipi_done(xs); 697 splx(s); 698 return; 699 } 700 /* 701 * XXX BuildSRB(srb ,dcb); XXX 702 */ 703 srb->dcb = dcb; 704 srb->xs = xs; 705 srb->cmdlen = xs->cmdlen; 706 /* 707 * Move layer of CAM command block to layer of SCSI 708 * Request Block for SCSI processor command doing. 709 */ 710 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 711 if (xs->datalen > 0) { 712 #ifdef TRM_DEBUG 713 printf("xs->datalen...\n"); 714 printf("sc->sc_dmat=%x\n", (int) sc->sc_dmat); 715 printf("srb->dmap=%x\n", (int) srb->dmap); 716 printf("xs->data=%x\n", (int) xs->data); 717 printf("xs->datalen=%x\n", (int) xs->datalen); 718 #endif 719 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 720 xs->data, xs->datalen, NULL, 721 (xs->xs_control & XS_CTL_NOSLEEP) ? 722 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) != 0) { 723 printf("%s: DMA transfer map unable to load, " 724 "error = %d\n", sc->sc_dev.dv_xname, error); 725 xs->error = XS_DRIVER_STUFFUP; 726 /* 727 * free SRB 728 */ 729 srb->next = sc->sc_freesrb; 730 sc->sc_freesrb = srb; 731 splx(s); 732 return; 733 } 734 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 735 srb->dmap->dm_mapsize, 736 (xs->xs_control & XS_CTL_DATA_IN) ? 737 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 738 739 /* Set up the scatter gather list */ 740 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 741 srb->sgentry[i].address = 742 htole32(srb->dmap->dm_segs[i].ds_addr); 743 srb->sgentry[i].length = 744 htole32(srb->dmap->dm_segs[i].ds_len); 745 } 746 srb->buflen = xs->datalen; 747 srb->sgcnt = srb->dmap->dm_nsegs; 748 } else { 749 srb->sgentry[0].address = 0; 750 srb->sgentry[0].length = 0; 751 srb->buflen = 0; 752 srb->sgcnt = 0; 753 } 754 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 755 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 756 757 if (dcb->type != T_SEQUENTIAL) 758 srb->retry = 1; 759 else 760 srb->retry = 0; 761 762 srb->sgindex = 0; 763 srb->hastat = 0; 764 srb->tastat = 0; 765 srb->msgcnt = 0; 766 srb->srbstat = 0; 767 srb->flag = 0; 768 srb->state = 0; 769 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 770 771 trm_send_srb(xs, sc, srb); 772 splx(s); 773 774 if ((xs->xs_control & XS_CTL_POLL) == 0) { 775 int timeout = xs->timeout; 776 timeout = (timeout > 100000) ? 777 timeout / 1000 * hz : timeout * hz / 1000; 778 callout_reset(&xs->xs_callout, timeout, 779 trm_timeout, srb); 780 } else { 781 s = splbio(); 782 do { 783 while (--xs->timeout) { 784 DELAY(1000); 785 if (bus_space_read_2(iot, ioh, 786 TRM_SCSI_STATUS) & SCSIINTERRUPT) 787 break; 788 } 789 if (xs->timeout == 0) { 790 trm_timeout(srb); 791 break; 792 } else 793 trm_intr(sc); 794 } while ((xs->xs_status & XS_STS_DONE) == 0); 795 splx(s); 796 } 797 return; 798 799 case ADAPTER_REQ_GROW_RESOURCES: 800 /* XXX Not supported. */ 801 return; 802 803 case ADAPTER_REQ_SET_XFER_MODE: 804 /* XXX XXX XXX */ 805 return; 806 } 807 } 808 809 static void 810 trm_reset_device(sc) 811 struct trm_softc *sc; 812 { 813 struct trm_dcb *dcb, *pdcb; 814 struct trm_nvram *eeprom; 815 int index; 816 817 dcb = sc->sc_linkdcb; 818 if (dcb == NULL) 819 return; 820 821 pdcb = dcb; 822 do { 823 dcb->mode &= ~(SYNC_NEGO_DONE | WIDE_NEGO_DONE); 824 dcb->synctl = 0; 825 dcb->offset = 0; 826 eeprom = &sc->sc_eeprom; 827 dcb->tacfg = eeprom->target[dcb->id].config0; 828 index = eeprom->target[dcb->id].period & 0x07; 829 dcb->period = trm_clock_period[index]; 830 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && 831 (sc->sc_config & HCC_WIDE_CARD)) 832 dcb->mode |= WIDE_NEGO_ENABLE; 833 834 dcb = dcb->next; 835 } 836 while (pdcb != dcb); 837 } 838 839 static void 840 trm_recover_srb(sc) 841 struct trm_softc *sc; 842 { 843 struct trm_dcb *dcb, *pdcb; 844 struct trm_srb *psrb, *psrb2; 845 int i; 846 847 dcb = sc->sc_linkdcb; 848 if (dcb == NULL) 849 return; 850 851 pdcb = dcb; 852 do { 853 psrb = pdcb->gosrb; 854 for (i = 0; i < pdcb->gosrb_cnt; i++) { 855 psrb2 = psrb; 856 psrb = psrb->next; 857 if (pdcb->waitsrb) { 858 psrb2->next = pdcb->waitsrb; 859 pdcb->waitsrb = psrb2; 860 } else { 861 pdcb->waitsrb = psrb2; 862 pdcb->last_waitsrb = psrb2; 863 psrb2->next = NULL; 864 } 865 } 866 pdcb->gosrb_cnt = 0; 867 pdcb->gosrb = NULL; 868 pdcb->tagmask = 0; 869 pdcb = pdcb->next; 870 } 871 while (pdcb != dcb); 872 } 873 874 /* 875 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 876 */ 877 static void 878 trm_reset(sc) 879 struct trm_softc *sc; 880 { 881 bus_space_tag_t iot = sc->sc_iot; 882 bus_space_handle_t ioh = sc->sc_ioh; 883 int s; 884 885 #ifdef TRM_DEBUG 886 printf("%s: SCSI RESET.........", sc->sc_dev.dv_xname); 887 #endif 888 s = splbio(); 889 890 /* disable SCSI and DMA interrupt */ 891 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 892 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 893 894 trm_reset_scsi_bus(sc); 895 DELAY(500000); 896 897 /* Enable SCSI interrupt */ 898 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 899 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 900 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 901 902 /* Enable DMA interrupt */ 903 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 904 905 /* Clear DMA FIFO */ 906 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 907 908 /* Clear SCSI FIFO */ 909 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 910 911 trm_reset_device(sc); 912 trm_doing_srb_done(sc); 913 sc->sc_actdcb = NULL; 914 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 915 trm_wait_srb(sc); 916 917 splx(s); 918 } 919 920 static void 921 trm_timeout(arg) 922 void *arg; 923 { 924 struct trm_srb *srb = (struct trm_srb *)arg; 925 struct scsipi_xfer *xs = srb->xs; 926 struct scsipi_periph *periph = xs->xs_periph; 927 struct trm_softc *sc; 928 int s; 929 930 if (xs == NULL) 931 printf("trm_timeout called with xs == NULL\n"); 932 933 else { 934 scsipi_printaddr(xs->xs_periph); 935 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 936 } 937 938 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 939 940 s = splbio(); 941 trm_reset_scsi_bus(sc); 942 callout_stop(&xs->xs_callout); 943 splx(s); 944 } 945 946 static int 947 trm_start_scsi(sc, dcb, srb) 948 struct trm_softc *sc; 949 struct trm_dcb *dcb; 950 struct trm_srb *srb; 951 { 952 bus_space_tag_t iot = sc->sc_iot; 953 bus_space_handle_t ioh = sc->sc_ioh; 954 int tagnum; 955 u_int32_t tagmask; 956 u_int8_t scsicmd, idmsg; 957 958 srb->tagnum = 31; 959 960 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 961 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, dcb->id); 962 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 963 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 964 srb->phase = PH_BUS_FREE; /* initial phase */ 965 /* Flush FIFO */ 966 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 967 968 idmsg = dcb->idmsg; 969 970 if ((srb->cmd[0] == INQUIRY) || 971 (srb->cmd[0] == REQUEST_SENSE) || 972 (srb->flag & AUTO_REQSENSE)) { 973 if (((dcb->mode & WIDE_NEGO_ENABLE) && 974 (dcb->mode & WIDE_NEGO_DONE) == 0) || 975 ((dcb->mode & SYNC_NEGO_ENABLE) && 976 (dcb->mode & SYNC_NEGO_DONE) == 0)) { 977 if ((dcb->idmsg & 7) == 0 || srb->cmd[0] != INQUIRY) { 978 scsicmd = SCMD_SEL_ATNSTOP; 979 srb->state = SRB_MSGOUT; 980 goto polling; 981 } 982 } 983 /* Send identify message */ 984 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 985 idmsg & ~MSG_IDENTIFY_DISCFLAG); 986 scsicmd = SCMD_SEL_ATN; 987 srb->state = SRB_START_; 988 } else { /* not inquiry,request sense,auto request sense */ 989 /* Send identify message */ 990 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, idmsg); 991 DELAY(30); 992 scsicmd = SCMD_SEL_ATN; 993 srb->state = SRB_START_; 994 if (dcb->mode & EN_TAG_QUEUING) { 995 /* Send Tag message, get tag id */ 996 tagmask = 1; 997 tagnum = 0; 998 while (tagmask & dcb->tagmask) { 999 tagmask = tagmask << 1; 1000 tagnum++; 1001 } 1002 /* Send Tag id */ 1003 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1004 MSG_SIMPLE_Q_TAG); 1005 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, tagnum); 1006 1007 dcb->tagmask |= tagmask; 1008 srb->tagnum = tagnum; 1009 1010 scsicmd = SCMD_SEL_ATN3; 1011 srb->state = SRB_START_; 1012 } 1013 } 1014 polling: 1015 /* 1016 * Send CDB ..command block... 1017 */ 1018 if (srb->flag & AUTO_REQSENSE) { 1019 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, REQUEST_SENSE); 1020 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1021 dcb->idmsg << SCSI_CMD_LUN_SHIFT); 1022 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1023 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1024 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1025 sizeof(struct scsipi_sense_data)); 1026 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1027 } else 1028 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1029 srb->cmd, srb->cmdlen); 1030 1031 if (bus_space_read_2(iot, ioh, TRM_SCSI_STATUS) & SCSIINTERRUPT) { 1032 /* 1033 * If trm_start_scsi return 1: current interrupt status 1034 * is interrupt disreenable. It's said that SCSI processor 1035 * has more one SRB need to do, SCSI processor has been 1036 * occupied by one SRB. 1037 */ 1038 srb->state = SRB_READY; 1039 dcb->tagmask &= ~(1 << srb->tagnum); 1040 return (1); 1041 } else { 1042 /* 1043 * If trm_start_scsi return 0: current interrupt status 1044 * is interrupt enable. It's said that SCSI processor is 1045 * unoccupied. 1046 */ 1047 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1048 sc->sc_actdcb = dcb; 1049 dcb->actsrb = srb; 1050 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1051 DO_DATALATCH | DO_HWRESELECT); 1052 /* it's important for atn stop */ 1053 /* 1054 * SCSI command 1055 */ 1056 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1057 return (0); 1058 } 1059 } 1060 1061 /* 1062 * Catch an interrupt from the adapter 1063 * Process pending device interrupts. 1064 */ 1065 static int 1066 trm_intr(vsc) 1067 void *vsc; 1068 { 1069 bus_space_tag_t iot; 1070 bus_space_handle_t ioh; 1071 struct trm_softc *sc; 1072 struct trm_dcb *dcb; 1073 struct trm_srb *srb; 1074 void (*state_v) (struct trm_softc *, struct trm_srb *, int *); 1075 int phase, intstat, stat = 0; 1076 1077 #ifdef TRM_DEBUG 1078 printf("trm_intr......\n"); 1079 #endif 1080 sc = (struct trm_softc *)vsc; 1081 iot = sc->sc_iot; 1082 ioh = sc->sc_ioh; 1083 1084 if (sc == NULL) 1085 return (0); 1086 1087 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1088 if ((stat & SCSIINTERRUPT) == 0) 1089 return (0); 1090 1091 #ifdef TRM_DEBUG 1092 printf("stat=%2x,", stat); 1093 #endif 1094 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1095 1096 #ifdef TRM_DEBUG 1097 printf("intstat=%2x,", intstat); 1098 #endif 1099 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1100 trm_disconnect(sc); 1101 return (1); 1102 } 1103 if (intstat & INT_RESELECTED) { 1104 trm_reselect(sc); 1105 return (1); 1106 } 1107 if (intstat & INT_SCSIRESET) { 1108 trm_scsi_reset_detect(sc); 1109 return (1); 1110 } 1111 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1112 dcb = sc->sc_actdcb; 1113 srb = dcb->actsrb; 1114 if (dcb != NULL) 1115 if (dcb->flag & ABORT_DEV_) { 1116 srb->msgout[0] = MSG_ABORT; 1117 trm_msgout_abort(sc, srb); 1118 } 1119 /* 1120 * software sequential machine 1121 */ 1122 phase = srb->phase; /* phase: */ 1123 1124 /* 1125 * 62037 or 62137 call trm_scsi_phase0[]... "phase 1126 * entry" handle every phase before start transfer 1127 */ 1128 state_v = (void *)trm_scsi_phase0[phase]; 1129 state_v(sc, srb, &stat); 1130 1131 /* 1132 * if there were any exception occured 1133 * stat will be modify to bus free phase new 1134 * stat transfer out from ... prvious state_v 1135 * 1136 */ 1137 /* phase:0,1,2,3,4,5,6,7 */ 1138 srb->phase = stat & PHASEMASK; 1139 phase = stat & PHASEMASK; 1140 1141 /* 1142 * call trm_scsi_phase1[]... "phase entry" handle every 1143 * phase do transfer 1144 */ 1145 state_v = (void *)trm_scsi_phase1[phase]; 1146 state_v(sc, srb, &stat); 1147 return (1); 1148 } 1149 return (0); 1150 } 1151 1152 static void 1153 trm_msgout_phase0(sc, srb, pstat) 1154 struct trm_softc *sc; 1155 struct trm_srb *srb; 1156 int *pstat; 1157 { 1158 1159 if (srb->state & (SRB_UNEXPECT_RESEL | SRB_ABORT_SENT)) 1160 *pstat = PH_BUS_FREE; /* .. initial phase */ 1161 } 1162 1163 static void 1164 trm_msgout_phase1(sc, srb, pstat) 1165 struct trm_softc *sc; 1166 struct trm_srb *srb; 1167 int *pstat; 1168 { 1169 bus_space_tag_t iot = sc->sc_iot; 1170 bus_space_handle_t ioh = sc->sc_ioh; 1171 struct trm_dcb *dcb; 1172 1173 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1174 dcb = sc->sc_actdcb; 1175 if ((srb->state & SRB_MSGOUT) == 0) { 1176 if (srb->msgcnt > 0) { 1177 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1178 srb->msgout, srb->msgcnt); 1179 srb->msgcnt = 0; 1180 if ((dcb->flag & ABORT_DEV_) && 1181 (srb->msgout[0] == MSG_ABORT)) 1182 srb->state = SRB_ABORT_SENT; 1183 } else { 1184 if ((srb->cmd[0] == INQUIRY) || 1185 (srb->cmd[0] == REQUEST_SENSE) || 1186 (srb->flag & AUTO_REQSENSE)) 1187 if (dcb->mode & SYNC_NEGO_ENABLE) 1188 goto mop1; 1189 1190 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, MSG_ABORT); 1191 } 1192 } else { 1193 mop1: /* message out phase */ 1194 if ((srb->state & SRB_DO_WIDE_NEGO) == 0 && 1195 (dcb->mode & WIDE_NEGO_ENABLE)) { 1196 /* 1197 * WIDE DATA TRANSFER REQUEST code (03h) 1198 */ 1199 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1200 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1201 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1202 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1203 MSG_EXTENDED); /* (01h) */ 1204 1205 /* Message length (02h) */ 1206 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1207 MSG_EXT_WDTR_LEN); 1208 1209 /* wide data xfer (03h) */ 1210 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1211 MSG_EXT_WDTR); 1212 1213 /* width: 0(8bit), 1(16bit) ,2(32bit) */ 1214 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1215 MSG_EXT_WDTR_BUS_16_BIT); 1216 1217 srb->state |= SRB_DO_WIDE_NEGO; 1218 } else if ((srb->state & SRB_DO_SYNC_NEGO) == 0 && 1219 (dcb->mode & SYNC_NEGO_ENABLE)) { 1220 /* 1221 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1222 */ 1223 if ((dcb->mode & WIDE_NEGO_DONE) == 0) 1224 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1225 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1226 1227 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1228 MSG_EXTENDED); /* (01h) */ 1229 1230 /* Message length (03h) */ 1231 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1232 MSG_EXT_SDTR_LEN); 1233 1234 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1235 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1236 MSG_EXT_SDTR); 1237 1238 /* Transfer peeriod factor */ 1239 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, dcb->period); 1240 1241 /* REQ/ACK offset */ 1242 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1243 SYNC_NEGO_OFFSET); 1244 srb->state |= SRB_DO_SYNC_NEGO; 1245 } 1246 } 1247 /* it's important for atn stop */ 1248 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1249 1250 /* 1251 * SCSI cammand 1252 */ 1253 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1254 } 1255 1256 static void 1257 trm_command_phase0(sc, srb, pstat) 1258 struct trm_softc *sc; 1259 struct trm_srb *srb; 1260 int *pstat; 1261 { 1262 1263 } 1264 1265 static void 1266 trm_command_phase1(sc, srb, pstat) 1267 struct trm_softc *sc; 1268 struct trm_srb *srb; 1269 int *pstat; 1270 { 1271 bus_space_tag_t iot = sc->sc_iot; 1272 bus_space_handle_t ioh = sc->sc_ioh; 1273 struct trm_dcb *dcb; 1274 1275 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1276 if (srb->flag & AUTO_REQSENSE) { 1277 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, REQUEST_SENSE); 1278 dcb = sc->sc_actdcb; 1279 /* target id */ 1280 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1281 dcb->idmsg << SCSI_CMD_LUN_SHIFT); 1282 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1283 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1284 /* sizeof(struct scsi_sense_data) */ 1285 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1286 sizeof(struct scsipi_sense_data)); 1287 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1288 } else 1289 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1290 srb->cmd, srb->cmdlen); 1291 1292 srb->state = SRB_COMMAND; 1293 /* it's important for atn stop */ 1294 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1295 1296 /* 1297 * SCSI cammand 1298 */ 1299 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1300 } 1301 1302 static void 1303 trm_dataout_phase0(sc, srb, pstat) 1304 struct trm_softc *sc; 1305 struct trm_srb *srb; 1306 int *pstat; 1307 { 1308 bus_space_tag_t iot = sc->sc_iot; 1309 bus_space_handle_t ioh = sc->sc_ioh; 1310 struct trm_dcb *dcb; 1311 struct trm_sg_entry *sg; 1312 int sgindex; 1313 u_int32_t xferlen, leftcnt = 0; 1314 1315 dcb = srb->dcb; 1316 1317 if ((srb->state & SRB_XFERPAD) == 0) { 1318 if (*pstat & PARITYERROR) 1319 srb->srbstat |= PARITY_ERROR; 1320 1321 if ((*pstat & SCSIXFERDONE) == 0) { 1322 /* 1323 * when data transfer from DMA FIFO to SCSI FIFO 1324 * if there was some data left in SCSI FIFO 1325 */ 1326 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1327 SCSI_FIFOCNT_MASK; 1328 if (dcb->synctl & WIDE_SYNC) 1329 /* 1330 * if WIDE scsi SCSI FIFOCNT unit is word 1331 * so need to * 2 1332 */ 1333 leftcnt <<= 1; 1334 } 1335 /* 1336 * caculate all the residue data that not yet tranfered 1337 * SCSI transfer counter + left in SCSI FIFO data 1338 * 1339 * .....TRM_SCSI_XCNT (24bits) 1340 * The counter always decrement by one for every SCSI 1341 * byte transfer. 1342 * .....TRM_SCSI_FIFOCNT ( 5bits) 1343 * The counter is SCSI FIFO offset counter 1344 */ 1345 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1346 if (leftcnt == 1) { 1347 leftcnt = 0; 1348 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1349 DO_CLRFIFO); 1350 } 1351 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1352 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1353 DMAXFERCOMP) == 0) 1354 ; 1355 1356 srb->buflen = 0; 1357 } else { /* Update SG list */ 1358 /* 1359 * if transfer not yet complete 1360 * there were some data residue in SCSI FIFO or 1361 * SCSI transfer counter not empty 1362 */ 1363 if (srb->buflen != leftcnt) { 1364 /* data that had transferred length */ 1365 xferlen = srb->buflen - leftcnt; 1366 1367 /* next time to be transferred length */ 1368 srb->buflen = leftcnt; 1369 1370 /* 1371 * parsing from last time disconnect sgindex 1372 */ 1373 sg = srb->sgentry + srb->sgindex; 1374 for (sgindex = srb->sgindex; 1375 sgindex < srb->sgcnt; 1376 sgindex++, sg++) { 1377 /* 1378 * find last time which SG transfer 1379 * be disconnect 1380 */ 1381 if (xferlen >= le32toh(sg->length)) 1382 xferlen -= le32toh(sg->length); 1383 else { 1384 /* 1385 * update last time 1386 * disconnected SG list 1387 */ 1388 /* residue data length */ 1389 sg->length = htole32( 1390 le32toh(sg->length) 1391 - xferlen); 1392 /* residue data pointer */ 1393 sg->address = htole32( 1394 le32toh(sg->address) 1395 + xferlen); 1396 srb->sgindex = sgindex; 1397 break; 1398 } 1399 } 1400 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1401 srb->sgoffset, TRM_SG_SIZE, 1402 BUS_DMASYNC_PREWRITE); 1403 } 1404 } 1405 } 1406 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1407 } 1408 1409 static void 1410 trm_dataout_phase1(sc, srb, pstat) 1411 struct trm_softc *sc; 1412 struct trm_srb *srb; 1413 int *pstat; 1414 { 1415 1416 /* 1417 * do prepare befor transfer when data out phase 1418 */ 1419 trm_dataio_xfer(sc, srb, XFERDATAOUT); 1420 } 1421 1422 static void 1423 trm_datain_phase0(sc, srb, pstat) 1424 struct trm_softc *sc; 1425 struct trm_srb *srb; 1426 int *pstat; 1427 { 1428 bus_space_tag_t iot = sc->sc_iot; 1429 bus_space_handle_t ioh = sc->sc_ioh; 1430 struct trm_sg_entry *sg; 1431 int sgindex; 1432 u_int32_t xferlen, leftcnt = 0; 1433 1434 if ((srb->state & SRB_XFERPAD) == 0) { 1435 if (*pstat & PARITYERROR) 1436 srb->srbstat |= PARITY_ERROR; 1437 1438 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1439 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1440 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1441 DMAXFERCOMP) == 0) 1442 ; 1443 1444 srb->buflen = 0; 1445 } else { /* phase changed */ 1446 /* 1447 * parsing the case: 1448 * when a transfer not yet complete 1449 * but be disconnected by uper layer 1450 * if transfer not yet complete 1451 * there were some data residue in SCSI FIFO or 1452 * SCSI transfer counter not empty 1453 */ 1454 if (srb->buflen != leftcnt) { 1455 /* 1456 * data that had transferred length 1457 */ 1458 xferlen = srb->buflen - leftcnt; 1459 1460 /* 1461 * next time to be transferred length 1462 */ 1463 srb->buflen = leftcnt; 1464 1465 /* 1466 * parsing from last time disconnect sgindex 1467 */ 1468 sg = srb->sgentry + srb->sgindex; 1469 for (sgindex = srb->sgindex; 1470 sgindex < srb->sgcnt; 1471 sgindex++, sg++) { 1472 /* 1473 * find last time which SG transfer 1474 * be disconnect 1475 */ 1476 if (xferlen >= le32toh(sg->length)) 1477 xferlen -= le32toh(sg->length); 1478 else { 1479 /* 1480 * update last time 1481 * disconnected SG list 1482 */ 1483 /* residue data length */ 1484 sg->length = htole32( 1485 le32toh(sg->length) 1486 - xferlen); 1487 /* residue data pointer */ 1488 sg->address = htole32( 1489 le32toh(sg->address) 1490 + xferlen); 1491 srb->sgindex = sgindex; 1492 break; 1493 } 1494 } 1495 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1496 srb->sgoffset, TRM_SG_SIZE, 1497 BUS_DMASYNC_PREWRITE); 1498 } 1499 } 1500 } 1501 } 1502 1503 static void 1504 trm_datain_phase1(sc, srb, pstat) 1505 struct trm_softc *sc; 1506 struct trm_srb *srb; 1507 int *pstat; 1508 { 1509 1510 /* 1511 * do prepare befor transfer when data in phase 1512 */ 1513 trm_dataio_xfer(sc, srb, XFERDATAIN); 1514 } 1515 1516 static void 1517 trm_dataio_xfer(sc, srb, iodir) 1518 struct trm_softc *sc; 1519 struct trm_srb *srb; 1520 int iodir; 1521 { 1522 bus_space_tag_t iot = sc->sc_iot; 1523 bus_space_handle_t ioh = sc->sc_ioh; 1524 struct trm_dcb *dcb = srb->dcb; 1525 1526 if (srb->sgindex < srb->sgcnt) { 1527 if (srb->buflen > 0) { 1528 /* 1529 * load what physical address of Scatter/Gather 1530 * list table want to be transfer 1531 */ 1532 srb->state = SRB_DATA_XFER; 1533 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1534 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1535 srb->sgaddr + 1536 srb->sgindex * sizeof(struct trm_sg_entry)); 1537 /* 1538 * load how many bytes in the Scatter/Gather list table 1539 */ 1540 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1541 (srb->sgcnt - srb->sgindex) 1542 * sizeof(struct trm_sg_entry)); 1543 /* 1544 * load total xfer length (24bits) max value 16Mbyte 1545 */ 1546 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1547 /* Start DMA transfer */ 1548 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1549 iodir | SGXFER); 1550 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1551 STARTDMAXFER); 1552 1553 /* Start SCSI transfer */ 1554 /* it's important for atn stop */ 1555 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1556 DO_DATALATCH); 1557 1558 /* 1559 * SCSI cammand 1560 */ 1561 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1562 (iodir == XFERDATAOUT) ? 1563 SCMD_DMA_OUT : SCMD_DMA_IN); 1564 } else { /* xfer pad */ 1565 if (srb->sgcnt) { 1566 srb->hastat = H_OVER_UNDER_RUN; 1567 srb->srbstat |= OVER_RUN; 1568 } 1569 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1570 (dcb->synctl & WIDE_SYNC) ? 2 : 1); 1571 1572 if (iodir == XFERDATAOUT) 1573 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1574 else 1575 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1576 1577 srb->state |= SRB_XFERPAD; 1578 /* it's important for atn stop */ 1579 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1580 DO_DATALATCH); 1581 1582 /* 1583 * SCSI cammand 1584 */ 1585 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1586 (iodir == XFERDATAOUT) ? 1587 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1588 } 1589 } 1590 } 1591 1592 static void 1593 trm_status_phase0(sc, srb, pstat) 1594 struct trm_softc *sc; 1595 struct trm_srb *srb; 1596 int *pstat; 1597 { 1598 bus_space_tag_t iot = sc->sc_iot; 1599 bus_space_handle_t ioh = sc->sc_ioh; 1600 1601 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1602 srb->state = SRB_COMPLETED; 1603 *pstat = PH_BUS_FREE; /* .. initial phase */ 1604 /* it's important for atn stop */ 1605 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1606 1607 /* 1608 * SCSI cammand 1609 */ 1610 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1611 } 1612 1613 static void 1614 trm_status_phase1(sc, srb, pstat) 1615 struct trm_softc *sc; 1616 struct trm_srb *srb; 1617 int *pstat; 1618 { 1619 bus_space_tag_t iot = sc->sc_iot; 1620 bus_space_handle_t ioh = sc->sc_ioh; 1621 1622 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1623 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1624 & SCSI_FIFO_EMPTY) == 0) 1625 bus_space_write_2(iot, ioh, 1626 TRM_SCSI_CONTROL, DO_CLRFIFO); 1627 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1628 & DMA_FIFO_EMPTY) == 0) 1629 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1630 } else { 1631 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1632 & DMA_FIFO_EMPTY) == 0) 1633 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1634 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1635 & SCSI_FIFO_EMPTY) == 0) 1636 bus_space_write_2(iot, ioh, 1637 TRM_SCSI_CONTROL, DO_CLRFIFO); 1638 } 1639 srb->state = SRB_STATUS; 1640 /* it's important for atn stop */ 1641 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1642 1643 /* 1644 * SCSI cammand 1645 */ 1646 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1647 } 1648 1649 static void 1650 trm_msgin_phase0(sc, srb, pstat) 1651 struct trm_softc *sc; 1652 struct trm_srb *srb; 1653 int *pstat; 1654 { 1655 bus_space_tag_t iot = sc->sc_iot; 1656 bus_space_handle_t ioh = sc->sc_ioh; 1657 struct trm_dcb *dcb = sc->sc_actdcb; 1658 struct trm_srb *tempsrb; 1659 int syncxfer, tagid, index; 1660 u_int8_t msgin_code; 1661 1662 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1663 if ((srb->state & SRB_EXTEND_MSGIN) == 0) { 1664 if (msgin_code == MSG_DISCONNECT) { 1665 srb->state = SRB_DISCONNECT; 1666 goto min6; 1667 } else if (msgin_code == MSG_SAVEDATAPOINTER) { 1668 goto min6; 1669 } else if ((msgin_code == MSG_EXTENDED) || 1670 ((msgin_code >= MSG_SIMPLE_Q_TAG) && 1671 (msgin_code <= MSG_ORDERED_Q_TAG))) { 1672 srb->state |= SRB_EXTEND_MSGIN; 1673 /* extended message (01h) */ 1674 srb->msgin[0] = msgin_code; 1675 1676 srb->msgcnt = 1; 1677 /* extended message length (n) */ 1678 srb->msg = &srb->msgin[1]; 1679 1680 goto min6; 1681 } else if (msgin_code == MSG_MESSAGE_REJECT) { 1682 /* Reject message */ 1683 /* do wide nego reject */ 1684 if (dcb->mode & WIDE_NEGO_ENABLE) { 1685 dcb = srb->dcb; 1686 dcb->mode |= WIDE_NEGO_DONE; 1687 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP | 1688 WIDE_NEGO_ENABLE); 1689 srb->state &= ~(SRB_DO_WIDE_NEGO | SRB_MSGIN); 1690 if ((dcb->mode & SYNC_NEGO_ENABLE) && 1691 (dcb->mode & SYNC_NEGO_DONE) == 0) { 1692 /* Set ATN, in case ATN was clear */ 1693 srb->state |= SRB_MSGOUT; 1694 bus_space_write_2(iot, ioh, 1695 TRM_SCSI_CONTROL, DO_SETATN); 1696 } else 1697 /* Clear ATN */ 1698 bus_space_write_2(iot, ioh, 1699 TRM_SCSI_CONTROL, DO_CLRATN); 1700 } else if (dcb->mode & SYNC_NEGO_ENABLE) { 1701 /* do sync nego reject */ 1702 bus_space_write_2(iot, ioh, 1703 TRM_SCSI_CONTROL, DO_CLRATN); 1704 if (srb->state & SRB_DO_SYNC_NEGO) { 1705 dcb = srb->dcb; 1706 dcb->mode &= ~(SYNC_NEGO_ENABLE | 1707 SYNC_NEGO_DONE); 1708 dcb->synctl = 0; 1709 dcb->offset = 0; 1710 goto re_prog; 1711 } 1712 } 1713 goto min6; 1714 } else if (msgin_code == MSG_IGN_WIDE_RESIDUE) { 1715 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1716 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1717 goto min6; 1718 } else { 1719 /* 1720 * Restore data pointer message 1721 * Save data pointer message 1722 * Completion message 1723 * NOP message 1724 */ 1725 goto min6; 1726 } 1727 } else { 1728 /* 1729 * when extend message in:srb->state = SRB_EXTEND_MSGIN 1730 * Parsing incomming extented messages 1731 */ 1732 *srb->msg = msgin_code; 1733 srb->msgcnt++; 1734 srb->msg++; 1735 #ifdef TRM_DEBUG 1736 printf("srb->msgin[0]=%2x\n", srb->msgin[0]); 1737 printf("srb->msgin[1]=%2x\n", srb->msgin[1]); 1738 printf("srb->msgin[2]=%2x\n", srb->msgin[2]); 1739 printf("srb->msgin[3]=%2x\n", srb->msgin[3]); 1740 printf("srb->msgin[4]=%2x\n", srb->msgin[4]); 1741 #endif 1742 if ((srb->msgin[0] >= MSG_SIMPLE_Q_TAG) && 1743 (srb->msgin[0] <= MSG_ORDERED_Q_TAG)) { 1744 /* 1745 * is QUEUE tag message : 1746 * 1747 * byte 0: 1748 * HEAD QUEUE TAG (20h) 1749 * ORDERED QUEUE TAG (21h) 1750 * SIMPLE QUEUE TAG (22h) 1751 * byte 1: 1752 * Queue tag (00h - FFh) 1753 */ 1754 if (srb->msgcnt == 2) { 1755 srb->state = 0; 1756 tagid = srb->msgin[1]; 1757 srb = dcb->gosrb; 1758 tempsrb = dcb->last_gosrb; 1759 if (srb) { 1760 for (;;) { 1761 if (srb->tagnum != tagid) { 1762 if (srb == tempsrb) 1763 goto mingx0; 1764 1765 srb = srb->next; 1766 } else 1767 break; 1768 } 1769 if (dcb->flag & ABORT_DEV_) { 1770 srb->state = SRB_ABORT_SENT; 1771 srb->msgout[0] = MSG_ABORT; 1772 trm_msgout_abort(sc, srb); 1773 } 1774 if ((srb->state & SRB_DISCONNECT) == 0) 1775 goto mingx0; 1776 1777 dcb->actsrb = srb; 1778 srb->state = SRB_DATA_XFER; 1779 } else { 1780 mingx0: 1781 srb = &sc->sc_tempsrb; 1782 srb->state = SRB_UNEXPECT_RESEL; 1783 dcb->actsrb = srb; 1784 srb->msgout[0] = MSG_ABORT_TAG; 1785 trm_msgout_abort(sc, srb); 1786 } 1787 } 1788 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1789 (srb->msgin[2] == MSG_EXT_WDTR) && 1790 (srb->msgcnt == 4)) { 1791 /* 1792 * is Wide data xfer Extended message : 1793 * ====================================== 1794 * WIDE DATA TRANSFER REQUEST 1795 * ====================================== 1796 * byte 0 : Extended message (01h) 1797 * byte 1 : Extended message length (02h) 1798 * byte 2 : WIDE DATA TRANSFER code (03h) 1799 * byte 3 : Transfer width exponent 1800 */ 1801 dcb = srb->dcb; 1802 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_WIDE_NEGO); 1803 if ((srb->msgin[1] != MSG_EXT_WDTR_LEN)) { 1804 /* Length is wrong, reject it */ 1805 dcb->mode &= 1806 ~(WIDE_NEGO_ENABLE | WIDE_NEGO_DONE); 1807 srb->msgcnt = 1; 1808 srb->msgin[0] = MSG_MESSAGE_REJECT; 1809 bus_space_write_2(iot, ioh, 1810 TRM_SCSI_CONTROL, DO_SETATN); 1811 goto min6; 1812 } 1813 if (dcb->mode & WIDE_NEGO_ENABLE) { 1814 /* Do wide negoniation */ 1815 if (srb->msgin[3] > MSG_EXT_WDTR_BUS_32_BIT) { 1816 /* reject_msg: */ 1817 dcb->mode &= ~(WIDE_NEGO_ENABLE | 1818 WIDE_NEGO_DONE); 1819 srb->msgcnt = 1; 1820 srb->msgin[0] = MSG_MESSAGE_REJECT; 1821 bus_space_write_2(iot, ioh, 1822 TRM_SCSI_CONTROL, DO_SETATN); 1823 goto min6; 1824 } 1825 if (srb->msgin[3] == MSG_EXT_WDTR_BUS_32_BIT) 1826 /* do 16 bits */ 1827 srb->msgin[3] = MSG_EXT_WDTR_BUS_16_BIT; 1828 else { 1829 if ((dcb->mode & WIDE_NEGO_DONE) == 0) { 1830 srb->state &= 1831 ~(SRB_DO_WIDE_NEGO | 1832 SRB_MSGIN); 1833 dcb->mode |= WIDE_NEGO_DONE; 1834 dcb->mode &= 1835 ~(SYNC_NEGO_DONE | 1836 EN_ATN_STOP | 1837 WIDE_NEGO_ENABLE); 1838 if (srb->msgin[3] != 1839 MSG_EXT_WDTR_BUS_8_BIT) 1840 /* is Wide data xfer */ 1841 dcb->synctl |= 1842 WIDE_SYNC; 1843 } 1844 } 1845 } else 1846 srb->msgin[3] = MSG_EXT_WDTR_BUS_8_BIT; 1847 1848 srb->state |= SRB_MSGOUT; 1849 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1850 DO_SETATN); 1851 goto min6; 1852 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1853 (srb->msgin[2] == MSG_EXT_SDTR) && 1854 (srb->msgcnt == 5)) { 1855 /* 1856 * is 8bit transfer Extended message : 1857 * ================================= 1858 * SYNCHRONOUS DATA TRANSFER REQUEST 1859 * ================================= 1860 * byte 0 : Extended message (01h) 1861 * byte 1 : Extended message length (03) 1862 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1863 * byte 3 : Transfer period factor 1864 * byte 4 : REQ/ACK offset 1865 */ 1866 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_SYNC_NEGO); 1867 if (srb->msgin[1] != MSG_EXT_SDTR_LEN) { 1868 /* reject_msg: */ 1869 srb->msgcnt = 1; 1870 srb->msgin[0] = MSG_MESSAGE_REJECT; 1871 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1872 DO_SETATN); 1873 } else if (srb->msgin[3] == 0 || srb->msgin[4] == 0) { 1874 /* set async */ 1875 dcb = srb->dcb; 1876 /* disable sync & sync nego */ 1877 dcb->mode &= 1878 ~(SYNC_NEGO_ENABLE | SYNC_NEGO_DONE); 1879 dcb->synctl = 0; 1880 dcb->offset = 0; 1881 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1882 (dcb->lun == 0)) { 1883 printf("%s: target %d, Sync period=0 " 1884 "or Sync offset=0 to be " 1885 "asynchronous transfer\n", 1886 sc->sc_dev.dv_xname, dcb->id); 1887 dcb->flag |= SHOW_MESSAGE_; 1888 } 1889 goto re_prog; 1890 } else { /* set sync */ 1891 dcb = srb->dcb; 1892 dcb->mode |= SYNC_NEGO_ENABLE | SYNC_NEGO_DONE; 1893 1894 /* Transfer period factor */ 1895 dcb->period = srb->msgin[3]; 1896 1897 /* REQ/ACK offset */ 1898 dcb->offset = srb->msgin[4]; 1899 for (index = 0; index < 7; index++) 1900 if (srb->msgin[3] <= 1901 trm_clock_period[index]) 1902 break; 1903 1904 dcb->synctl |= (index | ALT_SYNC); 1905 /* 1906 * show negotiation message 1907 */ 1908 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1909 (dcb->lun == 0)) { 1910 syncxfer = 100000 / 1911 (trm_clock_period[index] * 4); 1912 if (dcb->synctl & WIDE_SYNC) { 1913 printf("%s: target %d, " 1914 "16bits Wide transfer\n", 1915 sc->sc_dev.dv_xname, 1916 dcb->id); 1917 syncxfer = syncxfer * 2; 1918 } else 1919 printf("%s: target %d, " 1920 "8bits Narrow transfer\n", 1921 sc->sc_dev.dv_xname, 1922 dcb->id); 1923 1924 printf("%s: target %d, " 1925 "Sync transfer %d.%01d MB/sec, " 1926 "Offset %d\n", sc->sc_dev.dv_xname, 1927 dcb->id, syncxfer / 100, 1928 syncxfer % 100, dcb->offset); 1929 dcb->flag |= SHOW_MESSAGE_; 1930 } 1931 re_prog: 1932 /* 1933 * program SCSI control register 1934 */ 1935 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, 1936 dcb->synctl); 1937 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 1938 dcb->offset); 1939 trm_set_xfer_rate(sc, srb, dcb); 1940 } 1941 } 1942 } 1943 min6: 1944 *pstat = PH_BUS_FREE; /* .. initial phase */ 1945 /* it's important for atn stop */ 1946 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1947 1948 /* 1949 * SCSI cammand 1950 */ 1951 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1952 } 1953 1954 static void 1955 trm_msgin_phase1(sc, srb, pstat) 1956 struct trm_softc *sc; 1957 struct trm_srb *srb; 1958 int *pstat; 1959 { 1960 bus_space_tag_t iot = sc->sc_iot; 1961 bus_space_handle_t ioh = sc->sc_ioh; 1962 1963 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1964 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1965 if ((srb->state & SRB_MSGIN) == 0) { 1966 srb->state &= SRB_DISCONNECT; 1967 srb->state |= SRB_MSGIN; 1968 } 1969 /* it's important for atn stop */ 1970 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1971 1972 /* 1973 * SCSI cammand 1974 */ 1975 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1976 } 1977 1978 static void 1979 trm_nop0(sc, srb, pstat) 1980 struct trm_softc *sc; 1981 struct trm_srb *srb; 1982 int *pstat; 1983 { 1984 1985 } 1986 1987 static void 1988 trm_nop1(sc, srb, pstat) 1989 struct trm_softc *sc; 1990 struct trm_srb *srb; 1991 int *pstat; 1992 { 1993 1994 } 1995 1996 static void 1997 trm_set_xfer_rate(sc, srb, dcb) 1998 struct trm_softc *sc; 1999 struct trm_srb *srb; 2000 struct trm_dcb *dcb; 2001 { 2002 struct trm_dcb *tempdcb; 2003 int i; 2004 2005 /* 2006 * set all lun device's (period, offset) 2007 */ 2008 #ifdef TRM_DEBUG 2009 printf("trm_set_xfer_rate............\n"); 2010 #endif 2011 if ((dcb->idmsg & 0x07) == 0) { 2012 if (sc->devscan_end == 0) 2013 sc->cur_offset = dcb->offset; 2014 else { 2015 tempdcb = sc->sc_linkdcb; 2016 for (i = 0; i < sc->devcnt; i++) { 2017 /* 2018 * different LUN but had same target ID 2019 */ 2020 if (tempdcb->id == dcb->id) { 2021 tempdcb->synctl = dcb->synctl; 2022 tempdcb->offset = dcb->offset; 2023 tempdcb->mode = dcb->mode; 2024 } 2025 tempdcb = tempdcb->next; 2026 } 2027 } 2028 } 2029 } 2030 2031 static void 2032 trm_disconnect(sc) 2033 struct trm_softc *sc; 2034 { 2035 bus_space_tag_t iot = sc->sc_iot; 2036 bus_space_handle_t ioh = sc->sc_ioh; 2037 struct trm_dcb *dcb; 2038 struct trm_srb *srb, *psrb; 2039 int i, s; 2040 2041 #ifdef TRM_DEBUG 2042 printf("trm_disconnect...............\n"); 2043 #endif 2044 s = splbio(); 2045 2046 dcb = sc->sc_actdcb; 2047 if (dcb == NULL) { 2048 DELAY(1000); /* 1 msec */ 2049 2050 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2051 DO_CLRFIFO | DO_HWRESELECT); 2052 return; 2053 } 2054 srb = dcb->actsrb; 2055 sc->sc_actdcb = 0; 2056 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2057 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2058 DO_CLRFIFO | DO_HWRESELECT); 2059 DELAY(100); 2060 if (srb->state & SRB_UNEXPECT_RESEL) { 2061 srb->state = 0; 2062 trm_wait_srb(sc); 2063 } else if (srb->state & SRB_ABORT_SENT) { 2064 dcb->tagmask = 0; 2065 dcb->flag &= ~ABORT_DEV_; 2066 srb = dcb->gosrb; 2067 for (i = 0; i < dcb->gosrb_cnt; i++) { 2068 psrb = srb->next; 2069 srb->next = sc->sc_freesrb; 2070 sc->sc_freesrb = srb; 2071 srb = psrb; 2072 } 2073 dcb->gosrb_cnt = 0; 2074 dcb->gosrb = 0; 2075 trm_wait_srb(sc); 2076 } else { 2077 if ((srb->state & (SRB_START_ | SRB_MSGOUT)) || 2078 (srb->state & (SRB_DISCONNECT | SRB_COMPLETED)) == 0) { 2079 /* Selection time out */ 2080 if (sc->devscan_end) { 2081 srb->state = SRB_READY; 2082 trm_rewait_srb(dcb, srb); 2083 } else { 2084 srb->tastat = SCSI_SEL_TIMEOUT; 2085 goto disc1; 2086 } 2087 } else if (srb->state & SRB_DISCONNECT) { 2088 /* 2089 * SRB_DISCONNECT 2090 */ 2091 trm_wait_srb(sc); 2092 } else if (srb->state & SRB_COMPLETED) { 2093 disc1: 2094 /* 2095 * SRB_COMPLETED 2096 */ 2097 if (dcb->maxcmd > 1) { 2098 /* free tag mask */ 2099 dcb->tagmask &= ~(1 << srb->tagnum); 2100 } 2101 dcb->actsrb = 0; 2102 srb->state = SRB_FREE; 2103 trm_srb_done(sc, dcb, srb); 2104 } 2105 } 2106 splx(s); 2107 } 2108 2109 static void 2110 trm_reselect(sc) 2111 struct trm_softc *sc; 2112 { 2113 bus_space_tag_t iot = sc->sc_iot; 2114 bus_space_handle_t ioh = sc->sc_ioh; 2115 struct trm_dcb *dcb; 2116 struct trm_srb *srb; 2117 int id, lun; 2118 2119 #ifdef TRM_DEBUG 2120 printf("trm_reselect.................\n"); 2121 #endif 2122 dcb = sc->sc_actdcb; 2123 if (dcb != NULL) { /* Arbitration lost but Reselection win */ 2124 srb = dcb->actsrb; 2125 srb->state = SRB_READY; 2126 trm_rewait_srb(dcb, srb); 2127 } 2128 /* Read Reselected Target Id and LUN */ 2129 id = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2130 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2131 dcb = sc->sc_linkdcb; 2132 while (id != dcb->id && lun != dcb->lun) 2133 /* get dcb of the reselect id */ 2134 dcb = dcb->next; 2135 2136 sc->sc_actdcb = dcb; 2137 if (dcb->mode & EN_TAG_QUEUING) { 2138 srb = &sc->sc_tempsrb; 2139 dcb->actsrb = srb; 2140 } else { 2141 srb = dcb->actsrb; 2142 if (srb == NULL || (srb->state & SRB_DISCONNECT) == 0) { 2143 /* 2144 * abort command 2145 */ 2146 srb = &sc->sc_tempsrb; 2147 srb->state = SRB_UNEXPECT_RESEL; 2148 dcb->actsrb = srb; 2149 srb->msgout[0] = MSG_ABORT; 2150 trm_msgout_abort(sc, srb); 2151 } else { 2152 if (dcb->flag & ABORT_DEV_) { 2153 srb->state = SRB_ABORT_SENT; 2154 srb->msgout[0] = MSG_ABORT; 2155 trm_msgout_abort(sc, srb); 2156 } else 2157 srb->state = SRB_DATA_XFER; 2158 } 2159 } 2160 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2161 /* 2162 * Program HA ID, target ID, period and offset 2163 */ 2164 /* target ID */ 2165 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, id); 2166 2167 /* host ID */ 2168 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2169 2170 /* period */ 2171 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 2172 2173 /* offset */ 2174 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 2175 2176 /* it's important for atn stop */ 2177 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2178 DELAY(30); 2179 /* 2180 * SCSI cammand 2181 */ 2182 /* to rls the /ACK signal */ 2183 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2184 } 2185 2186 /* 2187 * Complete execution of a SCSI command 2188 * Signal completion to the generic SCSI driver 2189 */ 2190 static void 2191 trm_srb_done(sc, dcb, srb) 2192 struct trm_softc *sc; 2193 struct trm_dcb *dcb; 2194 struct trm_srb *srb; 2195 { 2196 struct scsipi_xfer *xs = srb->xs; 2197 struct scsipi_inquiry_data *ptr; 2198 struct trm_dcb *tempdcb; 2199 int i, j, id, lun, s, tastat; 2200 u_int8_t bval; 2201 2202 #ifdef TRM_DEBUG 2203 printf("trm_srb_done..................\n"); 2204 #endif 2205 if ((xs->xs_control & XS_CTL_POLL) == 0) 2206 callout_stop(&xs->xs_callout); 2207 2208 if (xs == NULL) 2209 return; 2210 2211 /* 2212 * target status 2213 */ 2214 tastat = srb->tastat; 2215 2216 if (srb->flag & AUTO_REQSENSE) { 2217 /* 2218 * status of auto request sense 2219 */ 2220 srb->flag &= ~AUTO_REQSENSE; 2221 srb->hastat = 0; 2222 srb->tastat = SCSI_CHECK; 2223 if (tastat == SCSI_CHECK) { 2224 xs->error = XS_TIMEOUT; 2225 goto ckc_e; 2226 } 2227 memcpy(srb->cmd, srb->tempcmd, sizeof(srb->tempcmd)); 2228 2229 srb->buflen = srb->templen; 2230 srb->sgentry[0].address = srb->tempsg.address; 2231 srb->sgentry[0].length = srb->tempsg.length; 2232 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2233 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2234 xs->status = SCSI_CHECK; 2235 goto ckc_e; 2236 } 2237 /* 2238 * target status 2239 */ 2240 if (tastat) 2241 switch (tastat) { 2242 case SCSI_CHECK: 2243 trm_request_sense(sc, dcb, srb); 2244 return; 2245 case SCSI_QUEUE_FULL: 2246 dcb->maxcmd = dcb->gosrb_cnt - 1; 2247 trm_rewait_srb(dcb, srb); 2248 srb->hastat = 0; 2249 srb->tastat = 0; 2250 goto ckc_e; 2251 case SCSI_SEL_TIMEOUT: 2252 srb->hastat = H_SEL_TIMEOUT; 2253 srb->tastat = 0; 2254 xs->error = XS_TIMEOUT; 2255 break; 2256 case SCSI_BUSY: 2257 xs->error = XS_BUSY; 2258 break; 2259 case SCSI_RESV_CONFLICT: 2260 #ifdef TRM_DEBUG 2261 printf("%s: target reserved at ", sc->sc_dev.dv_xname); 2262 printf("%s %d\n", __FILE__, __LINE__); 2263 #endif 2264 xs->error = XS_BUSY; 2265 break; 2266 default: 2267 srb->hastat = 0; 2268 if (srb->retry) { 2269 srb->retry--; 2270 srb->tastat = 0; 2271 srb->sgindex = 0; 2272 if (trm_start_scsi(sc, dcb, srb)) 2273 /* 2274 * If trm_start_scsi return 1 : 2275 * current interrupt status is 2276 * interrupt disreenable. It's said 2277 * that SCSI processor has more one 2278 * SRB need to do. 2279 */ 2280 trm_rewait_srb(dcb, srb); 2281 return; 2282 } else { 2283 #ifdef TRM_DEBUG 2284 printf("%s: driver stuffup at %s %d\n", 2285 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2286 #endif 2287 xs->error = XS_DRIVER_STUFFUP; 2288 break; 2289 } 2290 } 2291 else { 2292 /* 2293 * process initiator status...... 2294 * Adapter (initiator) status 2295 */ 2296 if (srb->hastat & H_OVER_UNDER_RUN) { 2297 srb->tastat = 0; 2298 /* Illegal length (over/under run) */ 2299 xs->error = XS_DRIVER_STUFFUP; 2300 } else if (srb->srbstat & PARITY_ERROR) { 2301 #ifdef TRM_DEBUG 2302 printf("%s: driver stuffup at %s %d\n", 2303 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2304 #endif 2305 /* Driver failed to perform operation */ 2306 xs->error = XS_DRIVER_STUFFUP; 2307 } else { /* No error */ 2308 srb->hastat = 0; 2309 srb->tastat = 0; 2310 xs->error = XS_NOERROR; 2311 /* there is no error, (sense is invalid) */ 2312 } 2313 } 2314 ckc_e: 2315 id = srb->xs->xs_periph->periph_target; 2316 lun = srb->xs->xs_periph->periph_lun; 2317 if (sc->devscan[id][lun]) { 2318 /* 2319 * if SCSI command in "scan devices" duty 2320 */ 2321 if (srb->cmd[0] == TEST_UNIT_READY) { 2322 /* SCSI command phase: test unit ready */ 2323 #ifdef TRM_DEBUG 2324 printf("srb->cmd[0] == TEST_UNIT_READY....\n"); 2325 #endif 2326 } else if (srb->cmd[0] == INQUIRY) { 2327 /* 2328 * SCSI command phase: inquiry scsi device data 2329 * (type,capacity,manufacture.... 2330 */ 2331 if (xs->error == XS_TIMEOUT) 2332 goto NO_DEV; 2333 2334 ptr = (struct scsipi_inquiry_data *)xs->data; 2335 bval = ptr->device & SID_TYPE; 2336 /* 2337 * #define T_NODEVICE 0x1f Unknown or no device type 2338 */ 2339 if (bval == T_NODEVICE) { 2340 NO_DEV: 2341 #ifdef TRM_DEBUG 2342 printf("trm_srb_done NO Device: "); 2343 printf("id= %d ,lun= %d\n", id, lun); 2344 #endif 2345 s = splbio(); 2346 /* 2347 * dcb Q link 2348 * move the head of DCB to temdcb 2349 */ 2350 tempdcb = sc->sc_linkdcb; 2351 2352 /* 2353 * search current DCB for pass link 2354 */ 2355 while (tempdcb->next != dcb) 2356 tempdcb = tempdcb->next; 2357 2358 /* 2359 * when the current DCB been found 2360 * than connect current DCB tail 2361 * to the DCB tail that before current DCB 2362 */ 2363 tempdcb->next = dcb->next; 2364 2365 /* 2366 * if there was only one DCB ,connect his 2367 * tail to his head 2368 */ 2369 if (sc->sc_linkdcb == dcb) 2370 sc->sc_linkdcb = tempdcb->next; 2371 2372 if (sc->sc_roundcb == dcb) 2373 sc->sc_roundcb = tempdcb->next; 2374 2375 /* 2376 * if no device than free this device DCB 2377 * free( dcb, M_DEVBUF); 2378 */ 2379 sc->devcnt--; 2380 #ifdef TRM_DEBUG 2381 printf("sc->devcnt=%d\n", sc->devcnt); 2382 #endif 2383 if (sc->devcnt == 0) { 2384 sc->sc_linkdcb = NULL; 2385 sc->sc_roundcb = NULL; 2386 } 2387 /* no device set scan device flag=0 */ 2388 sc->devscan[id][lun] = 0; 2389 i = 0; 2390 j = 0; 2391 while (i <= sc->maxid) { 2392 while (j < 8) { 2393 if (sc->devscan[i][j] == 1) { 2394 sc->devscan_end = 0; 2395 splx(s); 2396 goto exit; 2397 } else 2398 sc->devscan_end = 1; 2399 2400 j++; 2401 } 2402 j = 0; 2403 i++; 2404 } 2405 splx(s); 2406 } else { 2407 dcb->type = bval; 2408 if (bval == T_DIRECT || bval == T_OPTICAL) { 2409 if ((((ptr->version & 0x07) >= 2) || 2410 ((ptr->response_format & 0x0F) 2411 == 2)) && 2412 (ptr->flags3 & SID_CmdQue) && 2413 (dcb->tacfg & NTC_DO_TAG_QUEUING) && 2414 (dcb->tacfg & NTC_DO_DISCONNECT)) { 2415 dcb->maxcmd = sc->maxtag; 2416 dcb->mode |= EN_TAG_QUEUING; 2417 dcb->tagmask = 0; 2418 } else 2419 dcb->mode |= EN_ATN_STOP; 2420 } 2421 } 2422 /* srb->cmd[0] == INQUIRY */ 2423 } 2424 /* sc->devscan[id][lun] */ 2425 } 2426 exit: 2427 if (xs->datalen > 0) { 2428 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2429 srb->dmap->dm_mapsize, (xs->xs_control & XS_CTL_DATA_IN) ? 2430 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2431 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2432 } 2433 trm_release_srb(sc, dcb, srb); 2434 trm_wait_srb(sc); 2435 xs->xs_status |= XS_STS_DONE; 2436 /* Notify cmd done */ 2437 scsipi_done(xs); 2438 } 2439 2440 static void 2441 trm_release_srb(sc, dcb, srb) 2442 struct trm_softc *sc; 2443 struct trm_dcb *dcb; 2444 struct trm_srb *srb; 2445 { 2446 struct trm_srb *psrb; 2447 int s; 2448 2449 s = splbio(); 2450 if (srb == dcb->gosrb) 2451 dcb->gosrb = srb->next; 2452 else { 2453 psrb = dcb->gosrb; 2454 while (psrb->next != srb) 2455 psrb = psrb->next; 2456 2457 psrb->next = srb->next; 2458 if (srb == dcb->last_gosrb) 2459 dcb->last_gosrb = psrb; 2460 } 2461 srb->next = sc->sc_freesrb; 2462 sc->sc_freesrb = srb; 2463 dcb->gosrb_cnt--; 2464 splx(s); 2465 return; 2466 } 2467 2468 static void 2469 trm_doing_srb_done(sc) 2470 struct trm_softc *sc; 2471 { 2472 struct trm_dcb *dcb, *pdcb; 2473 struct trm_srb *psrb, *psrb2; 2474 struct scsipi_xfer *xs; 2475 int i; 2476 2477 dcb = sc->sc_linkdcb; 2478 if (dcb == NULL) 2479 return; 2480 2481 pdcb = dcb; 2482 do { 2483 psrb = pdcb->gosrb; 2484 for (i = 0; i < pdcb->gosrb_cnt; i++) { 2485 psrb2 = psrb->next; 2486 xs = psrb->xs; 2487 xs->error = XS_TIMEOUT; 2488 /* ReleaseSRB( dcb, srb ); */ 2489 psrb->next = sc->sc_freesrb; 2490 sc->sc_freesrb = psrb; 2491 scsipi_done(xs); 2492 psrb = psrb2; 2493 } 2494 pdcb->gosrb_cnt = 0;; 2495 pdcb->gosrb = NULL; 2496 pdcb->tagmask = 0; 2497 pdcb = pdcb->next; 2498 } 2499 while (pdcb != dcb); 2500 } 2501 2502 static void 2503 trm_reset_scsi_bus(sc) 2504 struct trm_softc *sc; 2505 { 2506 bus_space_tag_t iot = sc->sc_iot; 2507 bus_space_handle_t ioh = sc->sc_ioh; 2508 int s; 2509 2510 s = splbio(); 2511 2512 sc->sc_flag |= RESET_DEV; 2513 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2514 while ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2515 INT_SCSIRESET) == 0) 2516 ; 2517 2518 splx(s); 2519 } 2520 2521 static void 2522 trm_scsi_reset_detect(sc) 2523 struct trm_softc *sc; 2524 { 2525 bus_space_tag_t iot = sc->sc_iot; 2526 bus_space_handle_t ioh = sc->sc_ioh; 2527 int s; 2528 2529 #ifdef TRM_DEBUG 2530 printf("trm_scsi_reset_detect...............\n"); 2531 #endif 2532 DELAY(1000000); /* delay 1 sec */ 2533 2534 s = splbio(); 2535 2536 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2537 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2538 2539 if (sc->sc_flag & RESET_DEV) { 2540 sc->sc_flag |= RESET_DONE; 2541 } else { 2542 sc->sc_flag |= RESET_DETECT; 2543 trm_reset_device(sc); 2544 /* trm_doing_srb_done( sc ); ???? */ 2545 trm_recover_srb(sc); 2546 sc->sc_actdcb = NULL; 2547 sc->sc_flag = 0; 2548 trm_wait_srb(sc); 2549 } 2550 splx(s); 2551 } 2552 2553 static void 2554 trm_request_sense(sc, dcb, srb) 2555 struct trm_softc *sc; 2556 struct trm_dcb *dcb; 2557 struct trm_srb *srb; 2558 { 2559 struct scsipi_xfer *xs = srb->xs; 2560 struct scsipi_sense *ss; 2561 int error, lun = xs->xs_periph->periph_lun; 2562 2563 srb->flag |= AUTO_REQSENSE; 2564 memcpy(srb->tempcmd, srb->cmd, sizeof(srb->tempcmd)); 2565 2566 srb->templen = srb->buflen; 2567 srb->tempsg.address = srb->sgentry[0].address; 2568 srb->tempsg.length = srb->sgentry[0].length; 2569 2570 /* Status of initiator/target */ 2571 srb->hastat = 0; 2572 srb->tastat = 0; 2573 2574 ss = (struct scsipi_sense *)srb->cmd; 2575 ss->opcode = REQUEST_SENSE; 2576 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 2577 ss->unused[0] = ss->unused[1] = 0; 2578 ss->length = sizeof(struct scsipi_sense_data); 2579 ss->control = 0; 2580 2581 srb->buflen = sizeof(struct scsipi_sense_data); 2582 srb->sgcnt = 1; 2583 srb->sgindex = 0; 2584 srb->cmdlen = sizeof(struct scsipi_sense); 2585 2586 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2587 &xs->sense.scsi_sense, srb->buflen, NULL, 2588 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2589 printf("trm_request_sense: can not bus_dmamap_load()\n"); 2590 xs->error = XS_DRIVER_STUFFUP; 2591 return; 2592 } 2593 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2594 srb->buflen, BUS_DMASYNC_PREREAD); 2595 2596 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2597 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2598 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2599 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2600 2601 if (trm_start_scsi(sc, dcb, srb)) 2602 /* 2603 * If trm_start_scsi return 1: current interrupt status 2604 * is interrupt disreenable. It's said that SCSI processor 2605 * has more one SRB need to do. 2606 */ 2607 trm_rewait_srb(dcb, srb); 2608 } 2609 2610 static void 2611 trm_msgout_abort(sc, srb) 2612 struct trm_softc *sc; 2613 struct trm_srb *srb; 2614 { 2615 bus_space_tag_t iot = sc->sc_iot; 2616 bus_space_handle_t ioh = sc->sc_ioh; 2617 2618 srb->msgcnt = 1; 2619 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_SETATN); 2620 srb->dcb->flag &= ~ABORT_DEV_; 2621 } 2622 2623 /* 2624 * initialize the internal structures for a given DCB 2625 */ 2626 static void 2627 trm_init_dcb(sc, dcb, xs) 2628 struct trm_softc *sc; 2629 struct trm_dcb *dcb; 2630 struct scsipi_xfer *xs; 2631 { 2632 struct trm_nvram *eeprom; 2633 struct trm_dcb *tempdcb; 2634 int index, id, lun, s; 2635 2636 id = xs->xs_periph->periph_target; 2637 lun = xs->xs_periph->periph_lun; 2638 2639 s = splbio(); 2640 if (sc->sc_linkdcb == 0) { 2641 sc->sc_linkdcb = dcb; 2642 /* 2643 * RunRobin impersonate the role that let each device had 2644 * good proportion about SCSI command proceeding. 2645 */ 2646 sc->sc_roundcb = dcb; 2647 dcb->next = dcb; 2648 } else { 2649 tempdcb = sc->sc_linkdcb; 2650 /* search the last nod of DCB link */ 2651 while (tempdcb->next != sc->sc_linkdcb) 2652 tempdcb = tempdcb->next; 2653 2654 /* connect current DCB with last DCB tail */ 2655 tempdcb->next = dcb; 2656 /* connect current DCB tail to this DCB Q head */ 2657 dcb->next = sc->sc_linkdcb; 2658 } 2659 splx(s); 2660 2661 sc->devcnt++; 2662 dcb->id = id; 2663 dcb->lun = lun; 2664 dcb->waitsrb = NULL; 2665 dcb->gosrb = NULL; 2666 dcb->gosrb_cnt = 0; 2667 dcb->actsrb = NULL; 2668 dcb->tagmask = 0; 2669 dcb->maxcmd = 1; 2670 dcb->flag = 0; 2671 2672 eeprom = &sc->sc_eeprom; 2673 dcb->tacfg = eeprom->target[id].config0; 2674 /* 2675 * disconnect enable? 2676 */ 2677 dcb->idmsg = MSG_IDENTIFY(lun, dcb->tacfg & NTC_DO_DISCONNECT); 2678 /* 2679 * tag Qing enable? 2680 * wide nego, sync nego enable? 2681 */ 2682 dcb->synctl = 0; 2683 dcb->offset = 0; 2684 index = eeprom->target[id].period & 0x07; 2685 dcb->period = trm_clock_period[index]; 2686 dcb->mode = 0; 2687 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && (sc->sc_config & HCC_WIDE_CARD)) 2688 /* enable wide nego */ 2689 dcb->mode |= WIDE_NEGO_ENABLE; 2690 2691 if ((dcb->tacfg & NTC_DO_SYNC_NEGO) && (lun == 0 || sc->cur_offset > 0)) 2692 /* enable sync nego */ 2693 dcb->mode |= SYNC_NEGO_ENABLE; 2694 } 2695 2696 static void 2697 trm_link_srb(sc) 2698 struct trm_softc *sc; 2699 { 2700 struct trm_srb *srb; 2701 int i; 2702 2703 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 2704 M_DEVBUF, M_NOWAIT); 2705 if (sc->sc_srb == NULL) { 2706 printf("%s: can not allocate SRB\n", sc->sc_dev.dv_xname); 2707 return; 2708 } 2709 memset(sc->sc_srb, 0, sizeof(struct trm_srb) * TRM_MAX_SRB); 2710 2711 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++, srb++) { 2712 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 2713 srb->sgoffset = TRM_SG_SIZE * i; 2714 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 2715 /* 2716 * map all SRB space to SRB_array 2717 */ 2718 if (bus_dmamap_create(sc->sc_dmat, 2719 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 2720 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 2721 printf("%s: unable to create DMA transfer map...\n", 2722 sc->sc_dev.dv_xname); 2723 free(sc->sc_srb, M_DEVBUF); 2724 return; 2725 } 2726 if (i != TRM_MAX_SRB - 1) { 2727 /* 2728 * link all SRB 2729 */ 2730 srb->next = srb + 1; 2731 #ifdef TRM_DEBUG 2732 printf("srb->next = %8x ", (int) (srb + 1)); 2733 #endif 2734 } else { 2735 /* 2736 * load NULL to NextSRB of the last SRB 2737 */ 2738 srb->next = NULL; 2739 } 2740 #ifdef TRM_DEBUG 2741 printf("srb = %8x\n", (int) srb); 2742 #endif 2743 } 2744 return; 2745 } 2746 2747 /* 2748 * initialize the internal structures for a given SCSI host 2749 */ 2750 static void 2751 trm_init_sc(sc) 2752 struct trm_softc *sc; 2753 { 2754 bus_space_tag_t iot = sc->sc_iot; 2755 bus_space_handle_t ioh = sc->sc_ioh; 2756 struct trm_nvram *eeprom; 2757 int i, j; 2758 2759 eeprom = &sc->sc_eeprom; 2760 sc->maxid = 7; 2761 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2762 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 2763 sc->sc_config |= HCC_WIDE_CARD; 2764 sc->maxid = 15; 2765 } 2766 if (eeprom->channel_cfg & NAC_POWERON_SCSI_RESET) 2767 sc->sc_config |= HCC_SCSI_RESET; 2768 2769 sc->sc_linkdcb = NULL; 2770 sc->sc_roundcb = NULL; 2771 sc->sc_actdcb = NULL; 2772 sc->sc_id = eeprom->scsi_id; 2773 sc->devcnt = 0; 2774 sc->maxtag = 2 << eeprom->max_tag; 2775 sc->sc_flag = 0; 2776 sc->devscan_end = 0; 2777 /* 2778 * link all device's SRB Q of this adapter 2779 */ 2780 trm_link_srb(sc); 2781 sc->sc_freesrb = sc->sc_srb; 2782 /* allocate DCB array for scan device */ 2783 for (i = 0; i <= sc->maxid; i++) 2784 if (sc->sc_id != i) 2785 for (j = 0; j < 8; j++) { 2786 sc->devscan[i][j] = 1; 2787 sc->devflag[i][j] = 0; 2788 sc->sc_dcb[i][j] = 2789 malloc(sizeof(struct trm_dcb), 2790 M_DEVBUF, M_WAITOK); 2791 } 2792 2793 #ifdef TRM_DEBUG 2794 printf("sizeof(struct trm_dcb)= %8x\n", sizeof(struct trm_dcb)); 2795 printf("sizeof(struct trm_softc)= %8x\n", sizeof(struct trm_softc)); 2796 printf("sizeof(struct trm_srb)= %8x\n", sizeof(struct trm_srb)); 2797 #endif 2798 sc->sc_adapter.adapt_dev = &sc->sc_dev; 2799 sc->sc_adapter.adapt_nchannels = 1; 2800 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 2801 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 2802 sc->sc_adapter.adapt_request = trm_scsipi_request; 2803 sc->sc_adapter.adapt_minphys = minphys; 2804 2805 sc->sc_channel.chan_adapter = &sc->sc_adapter; 2806 sc->sc_channel.chan_bustype = &scsi_bustype; 2807 sc->sc_channel.chan_channel = 0; 2808 sc->sc_channel.chan_ntargets = sc->maxid + 1; 2809 sc->sc_channel.chan_nluns = 8; 2810 sc->sc_channel.chan_id = sc->sc_id; 2811 } 2812 2813 /* 2814 * write sc_eeprom 128 bytes to seeprom 2815 */ 2816 static void 2817 trm_eeprom_write_all(sc, eeprom) 2818 struct trm_softc *sc; 2819 struct trm_nvram *eeprom; 2820 { 2821 bus_space_tag_t iot = sc->sc_iot; 2822 bus_space_handle_t ioh = sc->sc_ioh; 2823 u_int8_t *buf = (u_int8_t *)eeprom; 2824 u_int8_t addr; 2825 2826 /* Enable SEEPROM */ 2827 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2828 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2829 2830 /* 2831 * Write enable 2832 */ 2833 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2834 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2835 trm_wait_30us(); 2836 2837 for (addr = 0; addr < 128; addr++, buf++) 2838 trm_eeprom_set_data(sc, addr, *buf); 2839 2840 /* 2841 * Write disable 2842 */ 2843 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2844 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2845 trm_wait_30us(); 2846 2847 /* Disable SEEPROM */ 2848 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2849 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2850 } 2851 2852 /* 2853 * write one byte to seeprom 2854 */ 2855 static void 2856 trm_eeprom_set_data(sc, addr, data) 2857 struct trm_softc *sc; 2858 u_int8_t addr; 2859 u_int8_t data; 2860 { 2861 bus_space_tag_t iot = sc->sc_iot; 2862 bus_space_handle_t ioh = sc->sc_ioh; 2863 int i; 2864 u_int8_t send; 2865 2866 /* 2867 * Send write command & address 2868 */ 2869 trm_eeprom_write_cmd(sc, 0x05, addr); 2870 /* 2871 * Write data 2872 */ 2873 for (i = 0; i < 8; i++, data <<= 1) { 2874 send = NVR_SELECT; 2875 if (data & 0x80) /* Start from bit 7 */ 2876 send |= NVR_BITOUT; 2877 2878 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2879 trm_wait_30us(); 2880 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2881 trm_wait_30us(); 2882 } 2883 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2884 trm_wait_30us(); 2885 /* 2886 * Disable chip select 2887 */ 2888 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2889 trm_wait_30us(); 2890 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2891 trm_wait_30us(); 2892 /* 2893 * Wait for write ready 2894 */ 2895 for (;;) { 2896 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2897 NVR_SELECT | NVR_CLOCK); 2898 trm_wait_30us(); 2899 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2900 trm_wait_30us(); 2901 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2902 break; 2903 } 2904 /* 2905 * Disable chip select 2906 */ 2907 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2908 } 2909 2910 /* 2911 * read seeprom 128 bytes to sc_eeprom 2912 */ 2913 static void 2914 trm_eeprom_read_all(sc, eeprom) 2915 struct trm_softc *sc; 2916 struct trm_nvram *eeprom; 2917 { 2918 bus_space_tag_t iot = sc->sc_iot; 2919 bus_space_handle_t ioh = sc->sc_ioh; 2920 u_int8_t *buf = (u_int8_t *)eeprom; 2921 u_int8_t addr; 2922 2923 /* 2924 * Enable SEEPROM 2925 */ 2926 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2927 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2928 2929 for (addr = 0; addr < 128; addr++, buf++) 2930 *buf = trm_eeprom_get_data(sc, addr); 2931 2932 /* 2933 * Disable SEEPROM 2934 */ 2935 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2936 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2937 } 2938 2939 /* 2940 * read one byte from seeprom 2941 */ 2942 static u_int8_t 2943 trm_eeprom_get_data(sc, addr) 2944 struct trm_softc *sc; 2945 u_int8_t addr; 2946 { 2947 bus_space_tag_t iot = sc->sc_iot; 2948 bus_space_handle_t ioh = sc->sc_ioh; 2949 int i; 2950 u_int8_t read, data = 0; 2951 2952 /* 2953 * Send read command & address 2954 */ 2955 trm_eeprom_write_cmd(sc, 0x06, addr); 2956 2957 for (i = 0; i < 8; i++) { /* Read data */ 2958 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2959 NVR_SELECT | NVR_CLOCK); 2960 trm_wait_30us(); 2961 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2962 /* 2963 * Get data bit while falling edge 2964 */ 2965 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2966 data <<= 1; 2967 if (read & NVR_BITIN) 2968 data |= 1; 2969 2970 trm_wait_30us(); 2971 } 2972 /* 2973 * Disable chip select 2974 */ 2975 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2976 return (data); 2977 } 2978 2979 /* 2980 * write SB and Op Code into seeprom 2981 */ 2982 static void 2983 trm_eeprom_write_cmd(sc, cmd, addr) 2984 struct trm_softc *sc; 2985 u_int8_t cmd; 2986 u_int8_t addr; 2987 { 2988 bus_space_tag_t iot = sc->sc_iot; 2989 bus_space_handle_t ioh = sc->sc_ioh; 2990 int i; 2991 u_int8_t send; 2992 2993 /* Program SB+OP code */ 2994 for (i = 0; i < 3; i++, cmd <<= 1) { 2995 send = NVR_SELECT; 2996 if (cmd & 0x04) /* Start from bit 2 */ 2997 send |= NVR_BITOUT; 2998 2999 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 3000 trm_wait_30us(); 3001 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 3002 trm_wait_30us(); 3003 } 3004 3005 /* Program address */ 3006 for (i = 0; i < 7; i++, addr <<= 1) { 3007 send = NVR_SELECT; 3008 if (addr & 0x40) /* Start from bit 6 */ 3009 send |= NVR_BITOUT; 3010 3011 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 3012 trm_wait_30us(); 3013 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 3014 trm_wait_30us(); 3015 } 3016 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 3017 trm_wait_30us(); 3018 } 3019 3020 /* 3021 * read seeprom 128 bytes to sc_eeprom and check checksum. 3022 * If it is wrong, updated with default value. 3023 */ 3024 static void 3025 trm_check_eeprom(sc, eeprom) 3026 struct trm_softc *sc; 3027 struct trm_nvram *eeprom; 3028 { 3029 struct nvram_target *target; 3030 u_int16_t *ep; 3031 u_int16_t chksum; 3032 int i; 3033 3034 #ifdef TRM_DEBUG 3035 printf("\n trm_check_eeprom......\n"); 3036 #endif 3037 trm_eeprom_read_all(sc, eeprom); 3038 ep = (u_int16_t *)eeprom; 3039 chksum = 0; 3040 for (i = 0; i < 64; i++) 3041 chksum += le16toh(*ep++); 3042 3043 if (chksum != TRM_NVRAM_CKSUM) { 3044 #ifdef TRM_DEBUG 3045 printf("TRM_S1040 EEPROM Check Sum ERROR (load default).\n"); 3046 #endif 3047 /* 3048 * Checksum error, load default 3049 */ 3050 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 3051 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 3052 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 3053 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 3054 eeprom->subclass = 0x00; 3055 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 3056 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 3057 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 3058 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 3059 eeprom->reserved0 = 0x00; 3060 3061 for (i = 0, target = eeprom->target; 3062 i < TRM_MAX_TARGETS; 3063 i++, target++) { 3064 target->config0 = 0x77; 3065 target->period = 0x00; 3066 target->config2 = 0x00; 3067 target->config3 = 0x00; 3068 } 3069 3070 eeprom->scsi_id = 7; 3071 eeprom->channel_cfg = 0x0F; 3072 eeprom->delay_time = 0; 3073 eeprom->max_tag = 4; 3074 eeprom->reserved1 = 0x15; 3075 eeprom->boot_target = 0; 3076 eeprom->boot_lun = 0; 3077 eeprom->reserved2 = 0; 3078 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 3079 3080 chksum = 0; 3081 ep = (u_int16_t *)eeprom; 3082 for (i = 0; i < 63; i++) 3083 chksum += le16toh(*ep++); 3084 3085 chksum = TRM_NVRAM_CKSUM - chksum; 3086 eeprom->checksum0 = chksum & 0xFF; 3087 eeprom->checksum1 = chksum >> 8; 3088 3089 trm_eeprom_write_all(sc, eeprom); 3090 } 3091 } 3092 3093 /* 3094 * initialize the SCSI chip ctrl registers 3095 */ 3096 static void 3097 trm_init_adapter(sc) 3098 struct trm_softc *sc; 3099 { 3100 bus_space_tag_t iot = sc->sc_iot; 3101 bus_space_handle_t ioh = sc->sc_ioh; 3102 u_int8_t bval; 3103 3104 /* program configuration 0 */ 3105 bval = PHASELATCH | INITIATOR | BLOCKRST; 3106 if (sc->sc_config & HCC_PARITY) 3107 bval |= PARITYCHECK; 3108 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 3109 3110 /* program configuration 1 */ 3111 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 3112 ACTIVE_NEG | ACTIVE_NEGPLUS); 3113 3114 /* 250ms selection timeout */ 3115 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 3116 3117 /* Mask all the interrupt */ 3118 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 3119 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 3120 3121 /* Reset SCSI module */ 3122 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 3123 3124 /* program Host ID */ 3125 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 3126 3127 /* set ansynchronous transfer */ 3128 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 3129 3130 /* Trun LED control off */ 3131 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 3132 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 3133 3134 /* DMA config */ 3135 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 3136 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 3137 3138 /* Clear pending interrupt status */ 3139 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 3140 3141 /* Enable SCSI interrupt */ 3142 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 3143 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 3144 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 3145 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 3146 } 3147 3148 /* 3149 * initialize the internal structures for a given SCSI host 3150 */ 3151 static int 3152 trm_init(sc) 3153 struct trm_softc *sc; 3154 { 3155 bus_dma_segment_t seg; 3156 int error, rseg, all_sgsize; 3157 3158 /* 3159 * EEPROM CHECKSUM 3160 */ 3161 trm_check_eeprom(sc, &sc->sc_eeprom); 3162 /* 3163 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 3164 * allocate the space for all SCSI control blocks (SRB) for DMA memory 3165 */ 3166 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 3167 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 3168 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 3169 printf("%s: unable to allocate SCSI REQUEST BLOCKS, " 3170 "error = %d\n", sc->sc_dev.dv_xname, error); 3171 return (-1); 3172 } 3173 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 3174 all_sgsize, (caddr_t *) &sc->sc_sglist, 3175 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 3176 printf("%s: unable to map SCSI REQUEST BLOCKS, " 3177 "error = %d\n", sc->sc_dev.dv_xname, error); 3178 return (-1); 3179 } 3180 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 3181 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 3182 printf("%s: unable to create SRB DMA maps, " 3183 "error = %d\n", sc->sc_dev.dv_xname, error); 3184 return (-1); 3185 } 3186 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 3187 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 3188 printf("%s: unable to load SRB DMA maps, " 3189 "error = %d\n", sc->sc_dev.dv_xname, error); 3190 return (-1); 3191 } 3192 #ifdef TRM_DEBUG 3193 printf("\n\n%s: all_sgsize=%x\n", sc->sc_dev.dv_xname, all_sgsize); 3194 #endif 3195 memset(sc->sc_sglist, 0, all_sgsize); 3196 trm_init_sc(sc); 3197 trm_init_adapter(sc); 3198 trm_reset(sc); 3199 return (0); 3200 } 3201 3202 /* 3203 * attach and init a host adapter 3204 */ 3205 static void 3206 trm_attach(parent, self, aux) 3207 struct device *parent; 3208 struct device *self; 3209 void *aux; 3210 { 3211 struct pci_attach_args *const pa = aux; 3212 struct trm_softc *sc = (void *) self; 3213 bus_space_tag_t iot; /* bus space tag */ 3214 bus_space_handle_t ioh; /* bus space handle */ 3215 pci_intr_handle_t ih; 3216 pcireg_t command; 3217 const char *intrstr; 3218 3219 /* 3220 * These cards do not allow memory mapped accesses 3221 * pa_pc: chipset tag 3222 * pa_tag: pci tag 3223 */ 3224 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3225 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 3226 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 3227 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3228 pci_conf_write(pa->pa_pc, pa->pa_tag, 3229 PCI_COMMAND_STATUS_REG, command); 3230 } 3231 /* 3232 * mask for get correct base address of pci IO port 3233 */ 3234 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 3235 &iot, &ioh, NULL, NULL)) { 3236 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 3237 return; 3238 } 3239 /* 3240 * test checksum of eeprom..& initial "ACB" adapter control block... 3241 */ 3242 sc->sc_iot = iot; 3243 sc->sc_ioh = ioh; 3244 sc->sc_dmat = pa->pa_dmat; 3245 if (trm_init(sc)) { 3246 /* 3247 * Error during initialization! 3248 */ 3249 printf(": Error during initialization\n"); 3250 return; 3251 } 3252 /* 3253 * Now try to attach all the sub-devices 3254 */ 3255 if (sc->sc_config & HCC_WIDE_CARD) 3256 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 3257 "Ultra Wide SCSI Adapter\n"); 3258 else 3259 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 3260 "Ultra SCSI Adapter\n"); 3261 3262 printf("%s: Adapter ID=%d, Max tag number=%d, %d SCBs\n", 3263 sc->sc_dev.dv_xname, sc->sc_id, sc->maxtag, TRM_MAX_SRB); 3264 /* 3265 * Now tell the generic SCSI layer about our bus. 3266 * map and establish interrupt 3267 */ 3268 if (pci_intr_map(pa, &ih)) { 3269 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 3270 return; 3271 } 3272 intrstr = pci_intr_string(pa->pa_pc, ih); 3273 3274 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 3275 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 3276 if (intrstr != NULL) 3277 printf(" at %s", intrstr); 3278 printf("\n"); 3279 return; 3280 } 3281 if (intrstr != NULL) 3282 printf("%s: interrupting at %s\n", 3283 sc->sc_dev.dv_xname, intrstr); 3284 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 3285 } 3286 3287 /* 3288 * match pci device 3289 */ 3290 static int 3291 trm_probe(parent, match, aux) 3292 struct device *parent; 3293 struct cfdata *match; 3294 void *aux; 3295 { 3296 struct pci_attach_args *pa = aux; 3297 3298 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 3299 switch (PCI_PRODUCT(pa->pa_id)) { 3300 case PCI_PRODUCT_TEKRAM2_DC315: 3301 return (1); 3302 } 3303 return (0); 3304 } 3305