1 /* $NetBSD: tga.c,v 1.63 2006/04/26 14:30:27 rpaulo Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.63 2006/04/26 14:30:27 rpaulo Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 int tgamatch(struct device *, struct cfdata *, void *); 63 void tgaattach(struct device *, struct device *, void *); 64 int tgaprint(void *, const char *); 65 66 CFATTACH_DECL(tga, sizeof(struct tga_softc), 67 tgamatch, tgaattach, NULL, NULL); 68 69 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 70 pcitag_t tag, struct tga_devconfig *dc); 71 72 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 73 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 74 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 75 unsigned tga_getdotclock(struct tga_devconfig *dc); 76 77 struct tga_devconfig tga_console_dc; 78 79 int tga_ioctl(void *, void *, u_long, caddr_t, int, struct lwp *); 80 paddr_t tga_mmap(void *, void *, off_t, int); 81 static void tga_copyrows(void *, int, int, int); 82 static void tga_copycols(void *, int, int, int, int); 83 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 84 void **, int *, int *, long *); 85 static void tga_free_screen(void *, void *); 86 static int tga_show_screen(void *, void *, int, 87 void (*) (void *, int, int), void *); 88 static int tga_rop(struct rasops_info *, int, int, int, int, int, 89 struct rasops_info *, int, int); 90 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 91 int, struct rasops_info *, int, int); 92 static void tga_putchar(void *c, int row, int col, 93 u_int uc, long attr); 94 static void tga_eraserows(void *, int, int, long); 95 static void tga_erasecols(void *, int, int, int, long); 96 void tga2_init(struct tga_devconfig *); 97 98 static void tga_config_interrupts(struct device *); 99 100 /* RAMDAC interface functions */ 101 static int tga_sched_update(void *, void (*)(void *)); 102 static void tga_ramdac_wr(void *, u_int, u_int8_t); 103 static u_int8_t tga_ramdac_rd(void *, u_int); 104 static void tga_bt463_wr(void *, u_int, u_int8_t); 105 static u_int8_t tga_bt463_rd(void *, u_int); 106 static void tga2_ramdac_wr(void *, u_int, u_int8_t); 107 static u_int8_t tga2_ramdac_rd(void *, u_int); 108 109 /* Interrupt handler */ 110 static int tga_intr(void *); 111 112 /* The NULL entries will get filled in by rasops_init(). 113 * XXX and the non-NULL ones will be overwritten; reset after calling it. 114 */ 115 struct wsdisplay_emulops tga_emulops = { 116 NULL, 117 NULL, 118 tga_putchar, 119 tga_copycols, 120 tga_erasecols, 121 tga_copyrows, 122 tga_eraserows, 123 NULL, 124 }; 125 126 struct wsscreen_descr tga_stdscreen = { 127 "std", 128 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 129 &tga_emulops, 130 0, 0, 131 WSSCREEN_REVERSE 132 }; 133 134 const struct wsscreen_descr *_tga_scrlist[] = { 135 &tga_stdscreen, 136 /* XXX other formats, graphics screen? */ 137 }; 138 139 struct wsscreen_list tga_screenlist = { 140 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 141 }; 142 143 struct wsdisplay_accessops tga_accessops = { 144 tga_ioctl, 145 tga_mmap, 146 tga_alloc_screen, 147 tga_free_screen, 148 tga_show_screen, 149 0 /* load_font */ 150 }; 151 152 static void tga_blank(struct tga_devconfig *); 153 static void tga_unblank(struct tga_devconfig *); 154 155 int 156 tga_cnmatch(iot, memt, pc, tag) 157 bus_space_tag_t iot, memt; 158 pci_chipset_tag_t pc; 159 pcitag_t tag; 160 { 161 return tga_matchcommon(memt, pc, tag); 162 } 163 164 int 165 tgamatch(parent, match, aux) 166 struct device *parent; 167 struct cfdata *match; 168 void *aux; 169 { 170 struct pci_attach_args *pa = aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 173 return (0); 174 175 switch (PCI_PRODUCT(pa->pa_id)) { 176 case PCI_PRODUCT_DEC_21030: 177 case PCI_PRODUCT_DEC_PBXGB: 178 break; 179 default: 180 return 0; 181 } 182 183 #if defined(__alpha__) || defined(arc) 184 /* short-circuit the following test, as we 185 * already have the memory mapped and hence 186 * cannot perform it---and we are the console 187 * anyway. 188 */ 189 if (pa->pa_tag == tga_console_dc.dc_pcitag) 190 return 10; 191 #endif 192 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 193 } 194 195 static int 196 tga_matchcommon(memt, pc, tag) 197 bus_space_tag_t memt; 198 pci_chipset_tag_t pc; 199 pcitag_t tag; 200 { 201 struct tga_devconfig tmp_dc; 202 struct tga_devconfig *dc = &tmp_dc; 203 bus_size_t pcisize; 204 205 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 206 dc->dc_tga_type = tga_identify(dc); 207 208 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 209 bus_space_unmap(memt, dc->dc_memh, pcisize); 210 if (dc->dc_tgaconf) 211 return 10; 212 return 0; 213 } 214 215 static void 216 tga_mapaddrs(memt, pc, tag, pcisize, dc) 217 bus_space_tag_t memt; 218 pci_chipset_tag_t pc; 219 pcitag_t tag; 220 bus_size_t *pcisize; 221 struct tga_devconfig *dc; 222 { 223 int flags; 224 225 dc->dc_memt = memt; 226 dc->dc_tgaconf = NULL; 227 228 /* XXX magic number */ 229 if (pci_mapreg_info(pc, tag, 0x10, 230 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 231 &dc->dc_pcipaddr, pcisize, &flags)) 232 panic("tga_mapaddrs: pci_mapreg_info() failed"); 233 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 234 panic("tga memory not prefetchable"); 235 236 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 237 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 238 panic("tga_mapaddrs: could not map TGA address space"); 239 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 240 241 bus_space_subregion(dc->dc_memt, dc->dc_memh, 242 TGA_MEM_CREGS, TGA_CREGS_SIZE, 243 &dc->dc_regs); 244 } 245 246 static void 247 tga_init(memt, pc, tag, dc) 248 bus_space_tag_t memt; 249 pci_chipset_tag_t pc; 250 pcitag_t tag; 251 struct tga_devconfig *dc; 252 { 253 const struct tga_conf *tgac; 254 struct rasops_info *rip; 255 int cookie; 256 bus_size_t pcisize; 257 int i; 258 259 dc->dc_pcitag = tag; 260 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 261 dc->dc_tga_type = tga_identify(dc); 262 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 263 #if 0 264 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 265 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 266 panic("tga_init: memory size mismatch?"); 267 #endif 268 269 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 270 case 0x01: 271 case 0x02: 272 case 0x03: 273 case 0x04: 274 dc->dc_tga2 = 0; 275 break; 276 case 0x20: 277 case 0x21: 278 case 0x22: 279 dc->dc_tga2 = 1; 280 break; 281 default: 282 panic("tga_init: TGA Revision not recognized"); 283 } 284 285 if (dc->dc_tga2) 286 tga2_init(dc); 287 288 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 289 case 0: 290 dc->dc_wid = 8192; 291 break; 292 293 case 1: 294 dc->dc_wid = 8196; 295 break; 296 297 default: 298 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 299 break; 300 } 301 302 /* 303 * XXX XXX Turning off "odd" shouldn't be necessary, 304 * XXX XXX but I can't make X work with the weird size. 305 */ 306 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 307 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 308 TGAWREG(dc, TGA_REG_VHCR, 309 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 310 dc->dc_wid -= 4; 311 } 312 313 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 314 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 315 316 /* XXX this seems to be what DEC does */ 317 TGAWREG(dc, TGA_REG_CCBR, 0); 318 TGAWREG(dc, TGA_REG_VVBR, 1); 319 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 320 1 * tgac->tgac_vvbr_units; 321 dc->dc_blanked = 1; 322 tga_unblank(dc); 323 324 /* 325 * Set all bits in the pixel mask, to enable writes to all pixels. 326 * It seems that the console firmware clears some of them 327 * under some circumstances, which causes cute vertical stripes. 328 */ 329 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 330 331 /* clear the screen */ 332 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 333 *(u_int32_t *)(dc->dc_videobase + i) = 0; 334 335 /* Initialize rasops descriptor */ 336 rip = &dc->dc_rinfo; 337 rip->ri_flg = RI_CENTER; 338 rip->ri_depth = tgac->tgac_phys_depth; 339 rip->ri_bits = (void *)dc->dc_videobase; 340 rip->ri_width = dc->dc_wid; 341 rip->ri_height = dc->dc_ht; 342 rip->ri_stride = dc->dc_rowbytes; 343 rip->ri_hw = dc; 344 345 if (tgac->tgac_phys_depth == 32) { 346 rip->ri_rnum = 8; 347 rip->ri_gnum = 8; 348 rip->ri_bnum = 8; 349 rip->ri_rpos = 16; 350 rip->ri_gpos = 8; 351 rip->ri_bpos = 0; 352 } 353 354 wsfont_init(); 355 /* prefer 8 pixel wide font */ 356 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 357 WSDISPLAY_FONTORDER_L2R); 358 if (cookie <= 0) 359 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 360 WSDISPLAY_FONTORDER_L2R); 361 if (cookie <= 0) { 362 printf("tga: no appropriate fonts.\n"); 363 return; 364 } 365 366 /* the accelerated tga_putchar() needs LSbit left */ 367 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 368 printf("tga: couldn't lock font\n"); 369 return; 370 } 371 dc->dc_rinfo.ri_wsfcookie = cookie; 372 373 rasops_init(rip, 34, 80); 374 375 /* add our accelerated functions */ 376 /* XXX shouldn't have to do this; rasops should leave non-NULL 377 * XXX entries alone. 378 */ 379 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 380 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 381 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 382 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 383 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 384 385 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 386 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 387 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 388 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 389 390 391 dc->dc_intrenabled = 0; 392 } 393 394 void 395 tgaattach(parent, self, aux) 396 struct device *parent, *self; 397 void *aux; 398 { 399 struct pci_attach_args *pa = aux; 400 struct tga_softc *sc = (struct tga_softc *)self; 401 struct wsemuldisplaydev_attach_args aa; 402 pci_intr_handle_t intrh; 403 const char *intrstr; 404 u_int8_t rev; 405 int console; 406 407 #if defined(__alpha__) || defined(arc) 408 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 409 #else 410 console = 0; 411 #endif 412 if (console) { 413 sc->sc_dc = &tga_console_dc; 414 sc->nscreens = 1; 415 } else { 416 sc->sc_dc = (struct tga_devconfig *) 417 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 418 M_WAITOK|M_ZERO); 419 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 420 } 421 if (sc->sc_dc->dc_vaddr == 0) { 422 printf(": couldn't map memory space; punt!\n"); 423 return; 424 } 425 426 /* XXX say what's going on. */ 427 intrstr = NULL; 428 if (pci_intr_map(pa, &intrh)) { 429 printf(": couldn't map interrupt"); 430 return; 431 } 432 intrstr = pci_intr_string(pa->pa_pc, intrh); 433 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 434 sc->sc_dc); 435 if (sc->sc_intr == NULL) { 436 printf(": couldn't establish interrupt"); 437 if (intrstr != NULL) 438 printf("at %s", intrstr); 439 printf("\n"); 440 return; 441 } 442 443 rev = PCI_REVISION(pa->pa_class); 444 switch (rev) { 445 case 0x1: 446 case 0x2: 447 case 0x3: 448 printf(": DC21030 step %c", 'A' + rev - 1); 449 break; 450 case 0x20: 451 printf(": TGA2 abstract software model"); 452 break; 453 case 0x21: 454 case 0x22: 455 printf(": TGA2 pass %d", rev - 0x20); 456 break; 457 458 default: 459 printf("unknown stepping (0x%x)", rev); 460 break; 461 } 462 printf(", "); 463 464 /* 465 * Get RAMDAC function vectors and call the RAMDAC functions 466 * to allocate its private storage and pass that back to us. 467 */ 468 469 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 470 if (!sc->sc_dc->dc_tga2) { 471 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 472 sc->sc_dc->dc_ramdac_cookie = 473 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 474 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 475 else 476 sc->sc_dc->dc_ramdac_cookie = 477 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 478 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 479 } else { 480 sc->sc_dc->dc_ramdac_cookie = 481 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 482 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 483 484 /* XXX this is a bit of a hack, setting the dotclock here */ 485 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 486 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 487 (sc->sc_dc->dc_ramdac_cookie, 488 tga_getdotclock(sc->sc_dc)); 489 } 490 491 /* 492 * Initialize the RAMDAC. Initialization includes disabling 493 * cursor, setting a sane colormap, etc. We presume that we've 494 * filled in the necessary dot clock for PowerStorm 4d20. 495 */ 496 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 497 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 498 499 if (sc->sc_dc->dc_tgaconf == NULL) { 500 printf("unknown board configuration\n"); 501 return; 502 } 503 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 504 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 505 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 506 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 507 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 508 509 if (intrstr != NULL) 510 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 511 intrstr); 512 513 aa.console = console; 514 aa.scrdata = &tga_screenlist; 515 aa.accessops = &tga_accessops; 516 aa.accesscookie = sc; 517 518 config_found(self, &aa, wsemuldisplaydevprint); 519 520 config_interrupts(self, tga_config_interrupts); 521 } 522 523 static void 524 tga_config_interrupts (d) 525 struct device *d; 526 { 527 struct tga_softc *sc = (struct tga_softc *)d; 528 sc->sc_dc->dc_intrenabled = 1; 529 } 530 531 int 532 tga_ioctl(v, vs, cmd, data, flag, l) 533 void *v; 534 void *vs; 535 u_long cmd; 536 caddr_t data; 537 int flag; 538 struct lwp *l; 539 { 540 struct tga_softc *sc = v; 541 struct tga_devconfig *dc = sc->sc_dc; 542 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 543 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 544 545 switch (cmd) { 546 case WSDISPLAYIO_GTYPE: 547 *(u_int *)data = WSDISPLAY_TYPE_TGA; 548 return (0); 549 550 case WSDISPLAYIO_GINFO: 551 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 552 wsd_fbip->height = sc->sc_dc->dc_ht; 553 wsd_fbip->width = sc->sc_dc->dc_wid; 554 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 555 #if 0 556 wsd_fbip->cmsize = 256; /* XXX ??? */ 557 #else 558 wsd_fbip->cmsize = 1024; /* XXX ??? */ 559 #endif 560 #undef wsd_fbip 561 return (0); 562 563 case WSDISPLAYIO_GETCMAP: 564 return (*dcrf->ramdac_get_cmap)(dcrc, 565 (struct wsdisplay_cmap *)data); 566 567 case WSDISPLAYIO_PUTCMAP: 568 return (*dcrf->ramdac_set_cmap)(dcrc, 569 (struct wsdisplay_cmap *)data); 570 571 case WSDISPLAYIO_SVIDEO: 572 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 573 tga_blank(sc->sc_dc); 574 else 575 tga_unblank(sc->sc_dc); 576 return (0); 577 578 case WSDISPLAYIO_GVIDEO: 579 *(u_int *)data = dc->dc_blanked ? 580 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 581 return (0); 582 583 case WSDISPLAYIO_GCURPOS: 584 return (*dcrf->ramdac_get_curpos)(dcrc, 585 (struct wsdisplay_curpos *)data); 586 587 case WSDISPLAYIO_SCURPOS: 588 return (*dcrf->ramdac_set_curpos)(dcrc, 589 (struct wsdisplay_curpos *)data); 590 591 case WSDISPLAYIO_GCURMAX: 592 return (*dcrf->ramdac_get_curmax)(dcrc, 593 (struct wsdisplay_curpos *)data); 594 595 case WSDISPLAYIO_GCURSOR: 596 return (*dcrf->ramdac_get_cursor)(dcrc, 597 (struct wsdisplay_cursor *)data); 598 599 case WSDISPLAYIO_SCURSOR: 600 return (*dcrf->ramdac_set_cursor)(dcrc, 601 (struct wsdisplay_cursor *)data); 602 } 603 return (EPASSTHROUGH); 604 } 605 606 static int 607 tga_sched_update(v, f) 608 void *v; 609 void (*f)(void *); 610 { 611 struct tga_devconfig *dc = v; 612 613 if (dc->dc_intrenabled) { 614 /* Arrange for f to be called at the next end-of-frame interrupt */ 615 dc->dc_ramdac_intr = f; 616 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 617 } else { 618 /* Spin until the end-of-frame, then call f */ 619 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 620 TGAREGWB(dc, TGA_REG_SISR, 1); 621 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 622 ; 623 f(dc->dc_ramdac_cookie); 624 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 625 TGAREGWB(dc, TGA_REG_SISR, 1); 626 } 627 628 return 0; 629 } 630 631 static int 632 tga_intr(v) 633 void *v; 634 { 635 struct tga_devconfig *dc = v; 636 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 637 638 u_int32_t reg; 639 640 reg = TGARREG(dc, TGA_REG_SISR); 641 if (( reg & 0x00010001) != 0x00010001) { 642 /* Odd. We never set any of the other interrupt enables. */ 643 if ((reg & 0x1f) != 0) { 644 /* Clear the mysterious pending interrupts. */ 645 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 646 TGAREGWB(dc, TGA_REG_SISR, 1); 647 /* This was our interrupt, even if we're puzzled as to why 648 * we got it. Don't make the interrupt handler think it 649 * was a stray. 650 */ 651 return -1; 652 } else { 653 return 0; 654 } 655 } 656 /* if we have something to do, do it */ 657 if (dc->dc_ramdac_intr) { 658 dc->dc_ramdac_intr(dcrc); 659 dc->dc_ramdac_intr = NULL; 660 } 661 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 662 TGAREGWB(dc, TGA_REG_SISR, 1); 663 return (1); 664 } 665 666 paddr_t 667 tga_mmap(v, vs, offset, prot) 668 void *v; 669 void *vs; 670 off_t offset; 671 int prot; 672 { 673 struct tga_softc *sc = v; 674 675 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 676 return -1; 677 678 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 679 offset, prot, BUS_SPACE_MAP_LINEAR)); 680 } 681 682 static int 683 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 684 void *v; 685 const struct wsscreen_descr *type; 686 void **cookiep; 687 int *curxp, *curyp; 688 long *attrp; 689 { 690 struct tga_softc *sc = v; 691 long defattr; 692 693 if (sc->nscreens > 0) 694 return (ENOMEM); 695 696 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 697 *curxp = 0; 698 *curyp = 0; 699 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 700 0, 0, 0, &defattr); 701 *attrp = defattr; 702 sc->nscreens++; 703 return (0); 704 } 705 706 static void 707 tga_free_screen(v, cookie) 708 void *v; 709 void *cookie; 710 { 711 struct tga_softc *sc = v; 712 713 if (sc->sc_dc == &tga_console_dc) 714 panic("tga_free_screen: console"); 715 716 sc->nscreens--; 717 } 718 719 static int 720 tga_show_screen(v, cookie, waitok, cb, cbarg) 721 void *v; 722 void *cookie; 723 int waitok; 724 void (*cb)(void *, int, int); 725 void *cbarg; 726 { 727 728 return (0); 729 } 730 731 int 732 tga_cnattach(iot, memt, pc, bus, device, function) 733 bus_space_tag_t iot, memt; 734 pci_chipset_tag_t pc; 735 int bus, device, function; 736 { 737 struct tga_devconfig *dcp = &tga_console_dc; 738 long defattr; 739 740 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 741 742 /* sanity checks */ 743 if (dcp->dc_vaddr == 0) 744 panic("tga_console(%d, %d): couldn't map memory space", 745 device, function); 746 if (dcp->dc_tgaconf == NULL) 747 panic("tga_console(%d, %d): unknown board configuration", 748 device, function); 749 750 /* 751 * Initialize the RAMDAC but DO NOT allocate any private storage. 752 * Initialization includes disabling cursor, setting a sane 753 * colormap, etc. It will be reinitialized in tgaattach(). 754 */ 755 if (dcp->dc_tga2) { 756 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 757 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 758 tga2_ramdac_rd); 759 else 760 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 761 tga2_ramdac_rd, tga_getdotclock(dcp)); 762 } else { 763 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 764 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 765 tga_ramdac_rd); 766 else { 767 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 768 tga_bt463_rd); 769 } 770 } 771 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 772 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 773 774 return(0); 775 } 776 777 /* 778 * Functions to blank and unblank the display. 779 */ 780 static void 781 tga_blank(dc) 782 struct tga_devconfig *dc; 783 { 784 785 if (!dc->dc_blanked) { 786 dc->dc_blanked = 1; 787 /* XXX */ 788 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 789 } 790 } 791 792 static void 793 tga_unblank(dc) 794 struct tga_devconfig *dc; 795 { 796 797 if (dc->dc_blanked) { 798 dc->dc_blanked = 0; 799 /* XXX */ 800 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 801 } 802 } 803 804 /* 805 * Functions to manipulate the built-in cursor handing hardware. 806 */ 807 int 808 tga_builtin_set_cursor(dc, cursorp) 809 struct tga_devconfig *dc; 810 struct wsdisplay_cursor *cursorp; 811 { 812 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 813 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 814 u_char image[512]; 815 u_int count, v; 816 int error; 817 818 v = cursorp->which; 819 if (v & WSDISPLAY_CURSOR_DOCMAP) { 820 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 821 if (error) 822 return (error); 823 } 824 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 825 if ((u_int)cursorp->size.x != 64 || 826 (u_int)cursorp->size.y > 64) 827 return (EINVAL); 828 /* The cursor is 2 bits deep, and there is no mask */ 829 count = (cursorp->size.y * 64 * 2) / NBBY; 830 error = copyin(cursorp->image, image, count); 831 if (error) 832 return error; 833 } 834 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 835 return EINVAL; 836 837 /* parameters are OK; do it */ 838 if (v & WSDISPLAY_CURSOR_DOCUR) { 839 if (cursorp->enable) 840 /* XXX */ 841 TGAWREG(dc, TGA_REG_VVVR, 842 TGARREG(dc, TGA_REG_VVVR) | 0x04); 843 else 844 /* XXX */ 845 TGAWREG(dc, TGA_REG_VVVR, 846 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 847 } 848 if (v & WSDISPLAY_CURSOR_DOPOS) { 849 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 850 (cursorp->pos.x & 0xfff)); 851 } 852 if (v & WSDISPLAY_CURSOR_DOCMAP) { 853 dcrf->ramdac_set_curcmap(dcrc, cursorp); 854 } 855 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 856 count = ((64 * 2) / NBBY) * cursorp->size.y; 857 TGAWREG(dc, TGA_REG_CCBR, 858 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 859 (cursorp->size.y << 10)); 860 memcpy((char *)(dc->dc_vaddr + 861 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 862 image, count); 863 } 864 return (0); 865 } 866 867 int 868 tga_builtin_get_cursor(dc, cursorp) 869 struct tga_devconfig *dc; 870 struct wsdisplay_cursor *cursorp; 871 { 872 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 873 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 874 int count, error; 875 876 cursorp->which = WSDISPLAY_CURSOR_DOALL & 877 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 878 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 879 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 880 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 881 cursorp->size.x = 64; 882 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 883 884 if (cursorp->image != NULL) { 885 count = (cursorp->size.y * 64 * 2) / NBBY; 886 error = copyout((char *)(dc->dc_vaddr + 887 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 888 cursorp->image, count); 889 if (error) 890 return (error); 891 /* No mask */ 892 } 893 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 894 return (error); 895 } 896 897 int 898 tga_builtin_set_curpos(dc, curposp) 899 struct tga_devconfig *dc; 900 struct wsdisplay_curpos *curposp; 901 { 902 903 TGAWREG(dc, TGA_REG_CXYR, 904 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 905 return (0); 906 } 907 908 int 909 tga_builtin_get_curpos(dc, curposp) 910 struct tga_devconfig *dc; 911 struct wsdisplay_curpos *curposp; 912 { 913 914 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 915 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 916 return (0); 917 } 918 919 int 920 tga_builtin_get_curmax(dc, curposp) 921 struct tga_devconfig *dc; 922 struct wsdisplay_curpos *curposp; 923 { 924 925 curposp->x = curposp->y = 64; 926 return (0); 927 } 928 929 /* 930 * Copy columns (characters) in a row (line). 931 */ 932 static void 933 tga_copycols(id, row, srccol, dstcol, ncols) 934 void *id; 935 int row, srccol, dstcol, ncols; 936 { 937 struct rasops_info *ri = id; 938 int y, srcx, dstx, nx; 939 940 y = ri->ri_font->fontheight * row; 941 srcx = ri->ri_font->fontwidth * srccol; 942 dstx = ri->ri_font->fontwidth * dstcol; 943 nx = ri->ri_font->fontwidth * ncols; 944 945 tga_rop(ri, dstx, y, 946 nx, ri->ri_font->fontheight, RAS_SRC, 947 ri, srcx, y); 948 } 949 950 /* 951 * Copy rows (lines). 952 */ 953 static void 954 tga_copyrows(id, srcrow, dstrow, nrows) 955 void *id; 956 int srcrow, dstrow, nrows; 957 { 958 struct rasops_info *ri = id; 959 int srcy, dsty, ny; 960 961 srcy = ri->ri_font->fontheight * srcrow; 962 dsty = ri->ri_font->fontheight * dstrow; 963 ny = ri->ri_font->fontheight * nrows; 964 965 tga_rop(ri, 0, dsty, 966 ri->ri_emuwidth, ny, RAS_SRC, 967 ri, 0, srcy); 968 } 969 970 /* Do we need the src? */ 971 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 972 973 /* A mapping between our API and the TGA card */ 974 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 975 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 976 }; 977 978 /* 979 * Generic TGA raster op. 980 * This covers all possible raster ops, and 981 * clips the sizes and all of that. 982 */ 983 static int 984 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 985 struct rasops_info *dst; 986 int dx, dy, w, h, rop; 987 struct rasops_info *src; 988 int sx, sy; 989 { 990 if (!dst) 991 return -1; 992 if (needsrc[RAS_GETOP(rop)]) { 993 if (src == NULL) 994 return -1; /* We want a src */ 995 /* Clip against src */ 996 if (sx < 0) { 997 w += sx; 998 sx = 0; 999 } 1000 if (sy < 0) { 1001 h += sy; 1002 sy = 0; 1003 } 1004 if (sx + w > src->ri_emuwidth) 1005 w = src->ri_emuwidth - sx; 1006 if (sy + h > src->ri_emuheight) 1007 h = src->ri_emuheight - sy; 1008 } else { 1009 if (src != NULL) 1010 return -1; /* We need no src */ 1011 } 1012 /* Clip against dst. We modify src regardless of using it, 1013 * since it really doesn't matter. 1014 */ 1015 if (dx < 0) { 1016 w += dx; 1017 sx -= dx; 1018 dx = 0; 1019 } 1020 if (dy < 0) { 1021 h += dy; 1022 sy -= dy; 1023 dy = 0; 1024 } 1025 if (dx + w > dst->ri_emuwidth) 1026 w = dst->ri_emuwidth - dx; 1027 if (dy + h > dst->ri_emuheight) 1028 h = dst->ri_emuheight - dy; 1029 if (w <= 0 || h <= 0) 1030 return 0; /* Vacuously true; */ 1031 if (!src) { 1032 /* XXX Punt! */ 1033 return -1; 1034 } 1035 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1036 } 1037 1038 1039 1040 /* 1041 * Video to Video raster ops. 1042 * This function deals with all raster ops that have a src and dst 1043 * that are on the card. 1044 */ 1045 static int 1046 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1047 struct rasops_info *dst; 1048 int dx, dy, w, h, rop; 1049 struct rasops_info *src; 1050 int sx, sy; 1051 { 1052 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1053 int srcb, dstb, tga_srcb, tga_dstb; 1054 int x, y, wb; 1055 int xstart, xend, xdir; 1056 int ystart, yend, ydir, yinc; 1057 int xleft, lastx, lastleft; 1058 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1059 1060 /* 1061 * I don't yet want to deal with unaligned guys, really. And we don't 1062 * deal with copies from one card to another. 1063 */ 1064 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1065 /* XXX Punt! */ 1066 /* XXX should never happen, since it's only being used to 1067 * XXX copy 8-pixel-wide characters. 1068 */ 1069 return -1; 1070 } 1071 1072 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1073 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1074 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1075 (sx + src->ri_xorigin) * (src->ri_depth/8); 1076 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1077 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1078 1079 if (sy >= dy) { 1080 ystart = 0; 1081 yend = (h - 1) * dst->ri_stride; 1082 ydir = 1; 1083 } else { 1084 ystart = (h - 1) * dst->ri_stride; 1085 yend = 0; 1086 ydir = -1; 1087 } 1088 yinc = ydir * dst->ri_stride; 1089 1090 wb = w * (dst->ri_depth / 8); 1091 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1092 xstart = 0; 1093 xend = wb; 1094 xdir = 1; 1095 } else { /* copy backwards */ 1096 xstart = wb; 1097 xend = 0; 1098 xdir = -1; 1099 } 1100 1101 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1102 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1103 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1104 1105 /* 1106 * we have 3 sizes of pixels to move in X direction: 1107 * 4 * 64 (unrolled TGA ops) 1108 * 64 (single TGA op) 1109 * 4 (CPU, using long word) 1110 */ 1111 1112 if (xdir == 1) { /* move to the left */ 1113 1114 if (wb & ~63) 1115 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1116 /* 4*64 byte chunks */ 1117 for (xleft = wb, x = xstart; xleft >= 4*64; 1118 x += 4*64, xleft -= 4*64) { 1119 1120 /* XXX XXX Eight writes to different addresses should fill 1121 * XXX XXX up the write buffers on 21064 and 21164 chips, 1122 * XXX XXX but later CPUs might have larger write buffers which 1123 * XXX XXX require further unrolling of this loop, or the 1124 * XXX XXX insertion of memory barriers. 1125 */ 1126 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1127 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1128 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1129 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1130 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1131 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1132 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1133 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1134 } 1135 1136 /* 64 byte chunks */ 1137 for (; xleft >= 64; x += 64, xleft -= 64) { 1138 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1139 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1140 } 1141 } 1142 1143 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1144 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1145 1146 lastleft = wb & 63; 1147 if (lastleft) { 1148 lastx = xstart + (wb & ~63); 1149 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1150 /* 4 byte granularity */ 1151 for (x = lastx, xleft = lastleft; xleft >= 4; 1152 x += 4, xleft -= 4) { 1153 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1154 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1155 } 1156 } 1157 } 1158 } 1159 else { /* above move to the left, below move to the right */ 1160 1161 if (wb & ~63) 1162 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1163 /* 4*64 byte chunks */ 1164 for (xleft = wb, x = xstart; xleft >= 4*64; 1165 x -= 4*64, xleft -= 4*64) { 1166 1167 /* XXX XXX Eight writes to different addresses should fill 1168 * XXX XXX up the write buffers on 21064 and 21164 chips, 1169 * XXX XXX but later CPUs might have larger write buffers which 1170 * XXX XXX require further unrolling of this loop, or the 1171 * XXX XXX insertion of memory barriers. 1172 */ 1173 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1174 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1175 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1176 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1177 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1178 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1179 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1180 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1181 } 1182 1183 /* 64 byte chunks */ 1184 for (; xleft >= 64; x -= 64, xleft -= 64) { 1185 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1186 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1187 } 1188 } 1189 1190 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1191 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1192 1193 lastleft = wb & 63; 1194 if (lastleft) { 1195 lastx = xstart - (wb & ~63); 1196 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1197 /* 4 byte granularity */ 1198 for (x = lastx, xleft = lastleft; xleft >= 4; 1199 x -= 4, xleft -= 4) { 1200 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1201 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1202 } 1203 } 1204 } 1205 } 1206 return 0; 1207 } 1208 1209 1210 void tga_putchar (c, row, col, uc, attr) 1211 void *c; 1212 int row, col; 1213 u_int uc; 1214 long attr; 1215 { 1216 struct rasops_info *ri = c; 1217 struct tga_devconfig *dc = ri->ri_hw; 1218 int fs, height, width; 1219 u_char *fr; 1220 int32_t *rp; 1221 1222 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1223 1224 height = ri->ri_font->fontheight; 1225 width = ri->ri_font->fontwidth; 1226 1227 uc -= ri->ri_font->firstchar; 1228 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1229 fs = ri->ri_font->stride; 1230 1231 /* Set foreground and background color. XXX memoize this somehow? 1232 * The rasops code has already expanded the color entry to 32 bits 1233 * for us, even for 8-bit displays, so we don't have to do anything. 1234 */ 1235 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1236 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1237 1238 /* Set raster operation to "copy"... */ 1239 if (ri->ri_depth == 8) 1240 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1241 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1242 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1243 1244 /* Set which pixels we're drawing (of a possible 32). */ 1245 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1246 1247 /* Set drawing mode to opaque stipple. */ 1248 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1249 1250 /* Insert write barrier before actually sending data */ 1251 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1252 TGAREGWB(dc, TGA_REG_GMOR, 1); 1253 1254 while(height--) { 1255 /* The actual stipple write */ 1256 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1257 1258 fr += fs; 1259 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1260 } 1261 1262 /* Do underline */ 1263 if ((attr & 1) != 0) { 1264 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1265 *rp = 0xffffffff; 1266 } 1267 1268 /* Set grapics mode back to normal. */ 1269 TGAWREG(dc, TGA_REG_GMOR, 0); 1270 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1271 1272 } 1273 1274 static void 1275 tga_eraserows(c, row, num, attr) 1276 void *c; 1277 int row, num; 1278 long attr; 1279 { 1280 struct rasops_info *ri = c; 1281 struct tga_devconfig *dc = ri->ri_hw; 1282 int32_t color, lines, pixels; 1283 int32_t *rp; 1284 1285 color = ri->ri_devcmap[(attr >> 16) & 15]; 1286 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1287 lines = num * ri->ri_font->fontheight; 1288 pixels = ri->ri_emuwidth - 1; 1289 1290 /* Set fill color in block-color registers */ 1291 TGAWREG(dc, TGA_REG_GBCR0, color); 1292 TGAWREG(dc, TGA_REG_GBCR1, color); 1293 if (ri->ri_depth != 8) { 1294 TGAWREG(dc, TGA_REG_GBCR2, color); 1295 TGAWREG(dc, TGA_REG_GBCR3, color); 1296 TGAWREG(dc, TGA_REG_GBCR4, color); 1297 TGAWREG(dc, TGA_REG_GBCR5, color); 1298 TGAWREG(dc, TGA_REG_GBCR6, color); 1299 TGAWREG(dc, TGA_REG_GBCR7, color); 1300 } 1301 1302 /* Set raster operation to "copy"... */ 1303 if (ri->ri_depth == 8) 1304 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1305 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1306 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1307 1308 /* Set which pixels we're drawing (of a possible 32). */ 1309 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1310 1311 /* Set drawing mode to block fill. */ 1312 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1313 1314 /* Insert write barrier before actually sending data */ 1315 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1316 TGAREGWB(dc, TGA_REG_GMOR, 1); 1317 1318 while (lines--) { 1319 *rp = pixels; 1320 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1321 } 1322 1323 /* Set grapics mode back to normal. */ 1324 TGAWREG(dc, TGA_REG_GMOR, 0); 1325 1326 } 1327 1328 static void 1329 tga_erasecols (c, row, col, num, attr) 1330 void *c; 1331 int row, col, num; 1332 long attr; 1333 { 1334 struct rasops_info *ri = c; 1335 struct tga_devconfig *dc = ri->ri_hw; 1336 int32_t color, lines, pixels; 1337 int32_t *rp; 1338 1339 color = ri->ri_devcmap[(attr >> 16) & 15]; 1340 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1341 lines = ri->ri_font->fontheight; 1342 pixels = (num * ri->ri_font->fontwidth) - 1; 1343 1344 /* Set fill color in block-color registers */ 1345 TGAWREG(dc, TGA_REG_GBCR0, color); 1346 TGAWREG(dc, TGA_REG_GBCR1, color); 1347 if (ri->ri_depth != 8) { 1348 TGAWREG(dc, TGA_REG_GBCR2, color); 1349 TGAWREG(dc, TGA_REG_GBCR3, color); 1350 TGAWREG(dc, TGA_REG_GBCR4, color); 1351 TGAWREG(dc, TGA_REG_GBCR5, color); 1352 TGAWREG(dc, TGA_REG_GBCR6, color); 1353 TGAWREG(dc, TGA_REG_GBCR7, color); 1354 } 1355 1356 /* Set raster operation to "copy"... */ 1357 if (ri->ri_depth == 8) 1358 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1359 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1360 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1361 1362 /* Set which pixels we're drawing (of a possible 32). */ 1363 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1364 1365 /* Set drawing mode to block fill. */ 1366 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1367 1368 /* Insert write barrier before actually sending data */ 1369 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1370 TGAREGWB(dc, TGA_REG_GMOR, 1); 1371 1372 while (lines--) { 1373 *rp = pixels; 1374 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1375 } 1376 1377 /* Set grapics mode back to normal. */ 1378 TGAWREG(dc, TGA_REG_GMOR, 0); 1379 } 1380 1381 1382 static void 1383 tga_ramdac_wr(v, btreg, val) 1384 void *v; 1385 u_int btreg; 1386 u_int8_t val; 1387 { 1388 struct tga_devconfig *dc = v; 1389 1390 if (btreg > BT485_REG_MAX) 1391 panic("tga_ramdac_wr: reg %d out of range", btreg); 1392 1393 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1394 TGAREGWB(dc, TGA_REG_EPDR, 1); 1395 } 1396 1397 static void 1398 tga2_ramdac_wr(v, btreg, val) 1399 void *v; 1400 u_int btreg; 1401 u_int8_t val; 1402 { 1403 struct tga_devconfig *dc = v; 1404 bus_space_handle_t ramdac; 1405 1406 if (btreg > BT485_REG_MAX) 1407 panic("tga_ramdac_wr: reg %d out of range", btreg); 1408 1409 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1410 (0xe << 12) + (btreg << 8), 4, &ramdac); 1411 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1412 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1413 } 1414 1415 static u_int8_t 1416 tga_bt463_rd(v, btreg) 1417 void *v; 1418 u_int btreg; 1419 { 1420 struct tga_devconfig *dc = v; 1421 tga_reg_t rdval; 1422 1423 /* 1424 * Strobe CE# (high->low->high) since status and data are latched on 1425 * the falling and rising edges (repsectively) of this active-low signal. 1426 */ 1427 1428 TGAREGWB(dc, TGA_REG_EPSR, 1); 1429 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1430 TGAREGWB(dc, TGA_REG_EPSR, 1); 1431 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1432 1433 TGAREGRB(dc, TGA_REG_EPSR, 1); 1434 1435 rdval = TGARREG(dc, TGA_REG_EPDR); 1436 TGAREGWB(dc, TGA_REG_EPSR, 1); 1437 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1438 1439 return (rdval >> 16) & 0xff; 1440 } 1441 1442 static void 1443 tga_bt463_wr(v, btreg, val) 1444 void *v; 1445 u_int btreg; 1446 u_int8_t val; 1447 { 1448 struct tga_devconfig *dc = v; 1449 1450 /* 1451 * In spite of the 21030 documentation, to set the MPU bus bits for 1452 * a write, you set them in the upper bits of EPDR, not EPSR. 1453 */ 1454 1455 /* 1456 * Strobe CE# (high->low->high) since status and data are latched on 1457 * the falling and rising edges of this active-low signal. 1458 */ 1459 1460 TGAREGWB(dc, TGA_REG_EPDR, 1); 1461 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1462 TGAREGWB(dc, TGA_REG_EPDR, 1); 1463 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1464 TGAREGWB(dc, TGA_REG_EPDR, 1); 1465 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1466 1467 } 1468 1469 static u_int8_t 1470 tga_ramdac_rd(v, btreg) 1471 void *v; 1472 u_int btreg; 1473 { 1474 struct tga_devconfig *dc = v; 1475 tga_reg_t rdval; 1476 1477 if (btreg > BT485_REG_MAX) 1478 panic("tga_ramdac_rd: reg %d out of range", btreg); 1479 1480 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1481 TGAREGWB(dc, TGA_REG_EPSR, 1); 1482 1483 rdval = TGARREG(dc, TGA_REG_EPDR); 1484 return (rdval >> 16) & 0xff; /* XXX */ 1485 } 1486 1487 static u_int8_t 1488 tga2_ramdac_rd(v, btreg) 1489 void *v; 1490 u_int btreg; 1491 { 1492 struct tga_devconfig *dc = v; 1493 bus_space_handle_t ramdac; 1494 u_int8_t retval; 1495 1496 if (btreg > BT485_REG_MAX) 1497 panic("tga_ramdac_rd: reg %d out of range", btreg); 1498 1499 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1500 (0xe << 12) + (btreg << 8), 4, &ramdac); 1501 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1502 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1503 return retval; 1504 } 1505 1506 #include <dev/ic/decmonitors.c> 1507 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1508 1509 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1510 1511 void 1512 tga2_init(dc) 1513 struct tga_devconfig *dc; 1514 { 1515 struct monitor *m = tga_getmonitor(dc); 1516 1517 /* Deal with the dot clocks. 1518 */ 1519 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1520 /* Set this up as a reference clock for the 1521 * ibm561's PLL. 1522 */ 1523 tga2_ics9110_wr(dc, 14300000); 1524 /* XXX Can't set up the dotclock properly, until such time 1525 * as the RAMDAC is configured. 1526 */ 1527 } else { 1528 /* otherwise the ics9110 is our clock. */ 1529 tga2_ics9110_wr(dc, m->dotclock); 1530 } 1531 #if 0 1532 TGAWREG(dc, TGA_REG_VHCR, 1533 ((m->hbp / 4) << 21) | 1534 ((m->hsync / 4) << 14) | 1535 (((m->hfp - 4) / 4) << 9) | 1536 ((m->cols + 4) / 4)); 1537 #else 1538 TGAWREG(dc, TGA_REG_VHCR, 1539 ((m->hbp / 4) << 21) | 1540 ((m->hsync / 4) << 14) | 1541 (((m->hfp) / 4) << 9) | 1542 ((m->cols) / 4)); 1543 #endif 1544 TGAWREG(dc, TGA_REG_VVCR, 1545 (m->vbp << 22) | 1546 (m->vsync << 16) | 1547 (m->vfp << 11) | 1548 (m->rows)); 1549 TGAWREG(dc, TGA_REG_VVBR, 1); 1550 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1551 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1552 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1553 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1554 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1555 } 1556 1557 void 1558 tga2_ics9110_wr(dc, dotclock) 1559 struct tga_devconfig *dc; 1560 int dotclock; 1561 { 1562 bus_space_handle_t clock; 1563 u_int32_t valU; 1564 int N, M, R, V, X; 1565 int i; 1566 1567 switch (dotclock) { 1568 case 130808000: 1569 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1570 case 119840000: 1571 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1572 case 108180000: 1573 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1574 case 103994000: 1575 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1576 case 175000000: 1577 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1578 case 75000000: 1579 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1580 case 74000000: 1581 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1582 case 69000000: 1583 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1584 case 65000000: 1585 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1586 case 50000000: 1587 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1588 case 40000000: 1589 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1590 case 31500000: 1591 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1592 case 25175000: 1593 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1594 case 135000000: 1595 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1596 case 110000000: 1597 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1598 case 202500000: 1599 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1600 case 14300000: /* this one is just a ref clock */ 1601 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1602 default: 1603 panic("unrecognized clock rate %d", dotclock); 1604 } 1605 1606 /* XXX -- hard coded, bad */ 1607 valU = N | ( M << 7 ) | (V << 14); 1608 valU |= (X << 15) | (R << 17); 1609 valU |= 0x17 << 19; 1610 1611 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1612 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1613 1614 for (i=24; i>0; i--) { 1615 u_int32_t writeval; 1616 1617 writeval = valU & 0x1; 1618 if (i == 1) 1619 writeval |= 0x2; 1620 valU >>= 1; 1621 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1622 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1623 } 1624 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1625 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1626 &clock); /* XXX */ 1627 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1628 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1629 } 1630 1631 struct monitor * 1632 tga_getmonitor(dc) 1633 struct tga_devconfig *dc; 1634 { 1635 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1636 } 1637 1638 unsigned 1639 tga_getdotclock(dc) 1640 struct tga_devconfig *dc; 1641 { 1642 return tga_getmonitor(dc)->dotclock; 1643 } 1644