1 /* $NetBSD: tga.c,v 1.67 2007/10/19 12:00:55 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.67 2007/10/19 12:00:55 ad Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 int tgamatch(struct device *, struct cfdata *, void *); 63 void tgaattach(struct device *, struct device *, void *); 64 int tgaprint(void *, const char *); 65 66 CFATTACH_DECL(tga, sizeof(struct tga_softc), 67 tgamatch, tgaattach, NULL, NULL); 68 69 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 70 pcitag_t tag, struct tga_devconfig *dc); 71 72 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 73 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 74 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 75 unsigned tga_getdotclock(struct tga_devconfig *dc); 76 77 struct tga_devconfig tga_console_dc; 78 79 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 80 paddr_t tga_mmap(void *, void *, off_t, int); 81 static void tga_copyrows(void *, int, int, int); 82 static void tga_copycols(void *, int, int, int, int); 83 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 84 void **, int *, int *, long *); 85 static void tga_free_screen(void *, void *); 86 static int tga_show_screen(void *, void *, int, 87 void (*) (void *, int, int), void *); 88 static int tga_rop(struct rasops_info *, int, int, int, int, int, 89 struct rasops_info *, int, int); 90 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 91 int, struct rasops_info *, int, int); 92 static void tga_putchar(void *c, int row, int col, 93 u_int uc, long attr); 94 static void tga_eraserows(void *, int, int, long); 95 static void tga_erasecols(void *, int, int, int, long); 96 void tga2_init(struct tga_devconfig *); 97 98 static void tga_config_interrupts(struct device *); 99 100 /* RAMDAC interface functions */ 101 static int tga_sched_update(void *, void (*)(void *)); 102 static void tga_ramdac_wr(void *, u_int, u_int8_t); 103 static u_int8_t tga_ramdac_rd(void *, u_int); 104 static void tga_bt463_wr(void *, u_int, u_int8_t); 105 static u_int8_t tga_bt463_rd(void *, u_int); 106 static void tga2_ramdac_wr(void *, u_int, u_int8_t); 107 static u_int8_t tga2_ramdac_rd(void *, u_int); 108 109 /* Interrupt handler */ 110 static int tga_intr(void *); 111 112 /* The NULL entries will get filled in by rasops_init(). 113 * XXX and the non-NULL ones will be overwritten; reset after calling it. 114 */ 115 struct wsdisplay_emulops tga_emulops = { 116 NULL, 117 NULL, 118 tga_putchar, 119 tga_copycols, 120 tga_erasecols, 121 tga_copyrows, 122 tga_eraserows, 123 NULL, 124 NULL, 125 }; 126 127 struct wsscreen_descr tga_stdscreen = { 128 "std", 129 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 130 &tga_emulops, 131 0, 0, 132 WSSCREEN_REVERSE, 133 NULL, 134 }; 135 136 const struct wsscreen_descr *_tga_scrlist[] = { 137 &tga_stdscreen, 138 /* XXX other formats, graphics screen? */ 139 }; 140 141 struct wsscreen_list tga_screenlist = { 142 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 143 }; 144 145 struct wsdisplay_accessops tga_accessops = { 146 tga_ioctl, 147 tga_mmap, 148 tga_alloc_screen, 149 tga_free_screen, 150 tga_show_screen, 151 NULL, /* load_font */ 152 NULL, 153 NULL, 154 }; 155 156 static void tga_blank(struct tga_devconfig *); 157 static void tga_unblank(struct tga_devconfig *); 158 159 int 160 tga_cnmatch(iot, memt, pc, tag) 161 bus_space_tag_t iot, memt; 162 pci_chipset_tag_t pc; 163 pcitag_t tag; 164 { 165 return tga_matchcommon(memt, pc, tag); 166 } 167 168 int 169 tgamatch(parent, match, aux) 170 struct device *parent; 171 struct cfdata *match; 172 void *aux; 173 { 174 struct pci_attach_args *pa = aux; 175 176 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 177 return (0); 178 179 switch (PCI_PRODUCT(pa->pa_id)) { 180 case PCI_PRODUCT_DEC_21030: 181 case PCI_PRODUCT_DEC_PBXGB: 182 break; 183 default: 184 return 0; 185 } 186 187 #if defined(__alpha__) || defined(arc) 188 /* short-circuit the following test, as we 189 * already have the memory mapped and hence 190 * cannot perform it---and we are the console 191 * anyway. 192 */ 193 if (pa->pa_tag == tga_console_dc.dc_pcitag) 194 return 10; 195 #endif 196 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 197 } 198 199 static int 200 tga_matchcommon(memt, pc, tag) 201 bus_space_tag_t memt; 202 pci_chipset_tag_t pc; 203 pcitag_t tag; 204 { 205 struct tga_devconfig tmp_dc; 206 struct tga_devconfig *dc = &tmp_dc; 207 bus_size_t pcisize; 208 209 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 210 dc->dc_tga_type = tga_identify(dc); 211 212 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 213 bus_space_unmap(memt, dc->dc_memh, pcisize); 214 if (dc->dc_tgaconf) 215 return 10; 216 return 0; 217 } 218 219 static void 220 tga_mapaddrs(memt, pc, tag, pcisize, dc) 221 bus_space_tag_t memt; 222 pci_chipset_tag_t pc; 223 pcitag_t tag; 224 bus_size_t *pcisize; 225 struct tga_devconfig *dc; 226 { 227 int flags; 228 229 dc->dc_memt = memt; 230 dc->dc_tgaconf = NULL; 231 232 /* XXX magic number */ 233 if (pci_mapreg_info(pc, tag, 0x10, 234 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 235 &dc->dc_pcipaddr, pcisize, &flags)) 236 panic("tga_mapaddrs: pci_mapreg_info() failed"); 237 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 238 panic("tga memory not prefetchable"); 239 240 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 241 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 242 panic("tga_mapaddrs: could not map TGA address space"); 243 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 244 245 bus_space_subregion(dc->dc_memt, dc->dc_memh, 246 TGA_MEM_CREGS, TGA_CREGS_SIZE, 247 &dc->dc_regs); 248 } 249 250 static void 251 tga_init(memt, pc, tag, dc) 252 bus_space_tag_t memt; 253 pci_chipset_tag_t pc; 254 pcitag_t tag; 255 struct tga_devconfig *dc; 256 { 257 const struct tga_conf *tgac; 258 struct rasops_info *rip; 259 int cookie; 260 bus_size_t pcisize; 261 int i; 262 263 dc->dc_pcitag = tag; 264 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 265 dc->dc_tga_type = tga_identify(dc); 266 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 267 #if 0 268 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 269 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 270 panic("tga_init: memory size mismatch?"); 271 #endif 272 273 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 274 case 0x01: 275 case 0x02: 276 case 0x03: 277 case 0x04: 278 dc->dc_tga2 = 0; 279 break; 280 case 0x20: 281 case 0x21: 282 case 0x22: 283 dc->dc_tga2 = 1; 284 break; 285 default: 286 panic("tga_init: TGA Revision not recognized"); 287 } 288 289 if (dc->dc_tga2) 290 tga2_init(dc); 291 292 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 293 case 0: 294 dc->dc_wid = 8192; 295 break; 296 297 case 1: 298 dc->dc_wid = 8196; 299 break; 300 301 default: 302 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 303 break; 304 } 305 306 /* 307 * XXX XXX Turning off "odd" shouldn't be necessary, 308 * XXX XXX but I can't make X work with the weird size. 309 */ 310 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 311 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 312 TGAWREG(dc, TGA_REG_VHCR, 313 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 314 dc->dc_wid -= 4; 315 } 316 317 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 318 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 319 320 /* XXX this seems to be what DEC does */ 321 TGAWREG(dc, TGA_REG_CCBR, 0); 322 TGAWREG(dc, TGA_REG_VVBR, 1); 323 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 324 1 * tgac->tgac_vvbr_units; 325 dc->dc_blanked = 1; 326 tga_unblank(dc); 327 328 /* 329 * Set all bits in the pixel mask, to enable writes to all pixels. 330 * It seems that the console firmware clears some of them 331 * under some circumstances, which causes cute vertical stripes. 332 */ 333 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 334 335 /* clear the screen */ 336 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 337 *(u_int32_t *)(dc->dc_videobase + i) = 0; 338 339 /* Initialize rasops descriptor */ 340 rip = &dc->dc_rinfo; 341 rip->ri_flg = RI_CENTER; 342 rip->ri_depth = tgac->tgac_phys_depth; 343 rip->ri_bits = (void *)dc->dc_videobase; 344 rip->ri_width = dc->dc_wid; 345 rip->ri_height = dc->dc_ht; 346 rip->ri_stride = dc->dc_rowbytes; 347 rip->ri_hw = dc; 348 349 if (tgac->tgac_phys_depth == 32) { 350 rip->ri_rnum = 8; 351 rip->ri_gnum = 8; 352 rip->ri_bnum = 8; 353 rip->ri_rpos = 16; 354 rip->ri_gpos = 8; 355 rip->ri_bpos = 0; 356 } 357 358 wsfont_init(); 359 /* prefer 8 pixel wide font */ 360 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 361 WSDISPLAY_FONTORDER_L2R); 362 if (cookie <= 0) 363 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 364 WSDISPLAY_FONTORDER_L2R); 365 if (cookie <= 0) { 366 printf("tga: no appropriate fonts.\n"); 367 return; 368 } 369 370 /* the accelerated tga_putchar() needs LSbit left */ 371 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 372 printf("tga: couldn't lock font\n"); 373 return; 374 } 375 dc->dc_rinfo.ri_wsfcookie = cookie; 376 377 rasops_init(rip, 34, 80); 378 379 /* add our accelerated functions */ 380 /* XXX shouldn't have to do this; rasops should leave non-NULL 381 * XXX entries alone. 382 */ 383 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 384 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 385 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 386 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 387 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 388 389 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 390 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 391 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 392 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 393 394 395 dc->dc_intrenabled = 0; 396 } 397 398 void 399 tgaattach(parent, self, aux) 400 struct device *parent, *self; 401 void *aux; 402 { 403 struct pci_attach_args *pa = aux; 404 struct tga_softc *sc = (struct tga_softc *)self; 405 struct wsemuldisplaydev_attach_args aa; 406 pci_intr_handle_t intrh; 407 const char *intrstr; 408 u_int8_t rev; 409 int console; 410 411 #if defined(__alpha__) || defined(arc) 412 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 413 #else 414 console = 0; 415 #endif 416 if (console) { 417 sc->sc_dc = &tga_console_dc; 418 sc->nscreens = 1; 419 } else { 420 sc->sc_dc = (struct tga_devconfig *) 421 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 422 M_WAITOK|M_ZERO); 423 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 424 } 425 if (sc->sc_dc->dc_vaddr == 0) { 426 printf(": couldn't map memory space; punt!\n"); 427 return; 428 } 429 430 /* XXX say what's going on. */ 431 intrstr = NULL; 432 if (pci_intr_map(pa, &intrh)) { 433 printf(": couldn't map interrupt"); 434 return; 435 } 436 intrstr = pci_intr_string(pa->pa_pc, intrh); 437 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 438 sc->sc_dc); 439 if (sc->sc_intr == NULL) { 440 printf(": couldn't establish interrupt"); 441 if (intrstr != NULL) 442 printf("at %s", intrstr); 443 printf("\n"); 444 return; 445 } 446 447 rev = PCI_REVISION(pa->pa_class); 448 switch (rev) { 449 case 0x1: 450 case 0x2: 451 case 0x3: 452 printf(": DC21030 step %c", 'A' + rev - 1); 453 break; 454 case 0x20: 455 printf(": TGA2 abstract software model"); 456 break; 457 case 0x21: 458 case 0x22: 459 printf(": TGA2 pass %d", rev - 0x20); 460 break; 461 462 default: 463 printf("unknown stepping (0x%x)", rev); 464 break; 465 } 466 printf(", "); 467 468 /* 469 * Get RAMDAC function vectors and call the RAMDAC functions 470 * to allocate its private storage and pass that back to us. 471 */ 472 473 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 474 if (!sc->sc_dc->dc_tga2) { 475 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 476 sc->sc_dc->dc_ramdac_cookie = 477 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 478 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 479 else 480 sc->sc_dc->dc_ramdac_cookie = 481 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 482 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 483 } else { 484 sc->sc_dc->dc_ramdac_cookie = 485 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 486 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 487 488 /* XXX this is a bit of a hack, setting the dotclock here */ 489 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 490 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 491 (sc->sc_dc->dc_ramdac_cookie, 492 tga_getdotclock(sc->sc_dc)); 493 } 494 495 /* 496 * Initialize the RAMDAC. Initialization includes disabling 497 * cursor, setting a sane colormap, etc. We presume that we've 498 * filled in the necessary dot clock for PowerStorm 4d20. 499 */ 500 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 501 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 502 503 if (sc->sc_dc->dc_tgaconf == NULL) { 504 printf("unknown board configuration\n"); 505 return; 506 } 507 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 508 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 509 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 510 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 511 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 512 513 if (intrstr != NULL) 514 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 515 intrstr); 516 517 aa.console = console; 518 aa.scrdata = &tga_screenlist; 519 aa.accessops = &tga_accessops; 520 aa.accesscookie = sc; 521 522 config_found(self, &aa, wsemuldisplaydevprint); 523 524 config_interrupts(self, tga_config_interrupts); 525 } 526 527 static void 528 tga_config_interrupts (d) 529 struct device *d; 530 { 531 struct tga_softc *sc = (struct tga_softc *)d; 532 sc->sc_dc->dc_intrenabled = 1; 533 } 534 535 int 536 tga_ioctl(v, vs, cmd, data, flag, l) 537 void *v; 538 void *vs; 539 u_long cmd; 540 void *data; 541 int flag; 542 struct lwp *l; 543 { 544 struct tga_softc *sc = v; 545 struct tga_devconfig *dc = sc->sc_dc; 546 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 547 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 548 549 switch (cmd) { 550 case WSDISPLAYIO_GTYPE: 551 *(u_int *)data = WSDISPLAY_TYPE_TGA; 552 return (0); 553 554 case WSDISPLAYIO_GINFO: 555 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 556 wsd_fbip->height = sc->sc_dc->dc_ht; 557 wsd_fbip->width = sc->sc_dc->dc_wid; 558 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 559 #if 0 560 wsd_fbip->cmsize = 256; /* XXX ??? */ 561 #else 562 wsd_fbip->cmsize = 1024; /* XXX ??? */ 563 #endif 564 #undef wsd_fbip 565 return (0); 566 567 case WSDISPLAYIO_GETCMAP: 568 return (*dcrf->ramdac_get_cmap)(dcrc, 569 (struct wsdisplay_cmap *)data); 570 571 case WSDISPLAYIO_PUTCMAP: 572 return (*dcrf->ramdac_set_cmap)(dcrc, 573 (struct wsdisplay_cmap *)data); 574 575 case WSDISPLAYIO_SVIDEO: 576 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 577 tga_blank(sc->sc_dc); 578 else 579 tga_unblank(sc->sc_dc); 580 return (0); 581 582 case WSDISPLAYIO_GVIDEO: 583 *(u_int *)data = dc->dc_blanked ? 584 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 585 return (0); 586 587 case WSDISPLAYIO_GCURPOS: 588 return (*dcrf->ramdac_get_curpos)(dcrc, 589 (struct wsdisplay_curpos *)data); 590 591 case WSDISPLAYIO_SCURPOS: 592 return (*dcrf->ramdac_set_curpos)(dcrc, 593 (struct wsdisplay_curpos *)data); 594 595 case WSDISPLAYIO_GCURMAX: 596 return (*dcrf->ramdac_get_curmax)(dcrc, 597 (struct wsdisplay_curpos *)data); 598 599 case WSDISPLAYIO_GCURSOR: 600 return (*dcrf->ramdac_get_cursor)(dcrc, 601 (struct wsdisplay_cursor *)data); 602 603 case WSDISPLAYIO_SCURSOR: 604 return (*dcrf->ramdac_set_cursor)(dcrc, 605 (struct wsdisplay_cursor *)data); 606 } 607 return (EPASSTHROUGH); 608 } 609 610 static int 611 tga_sched_update(v, f) 612 void *v; 613 void (*f)(void *); 614 { 615 struct tga_devconfig *dc = v; 616 617 if (dc->dc_intrenabled) { 618 /* Arrange for f to be called at the next end-of-frame interrupt */ 619 dc->dc_ramdac_intr = f; 620 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 621 } else { 622 /* Spin until the end-of-frame, then call f */ 623 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 624 TGAREGWB(dc, TGA_REG_SISR, 1); 625 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 626 ; 627 f(dc->dc_ramdac_cookie); 628 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 629 TGAREGWB(dc, TGA_REG_SISR, 1); 630 } 631 632 return 0; 633 } 634 635 static int 636 tga_intr(v) 637 void *v; 638 { 639 struct tga_devconfig *dc = v; 640 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 641 642 u_int32_t reg; 643 644 reg = TGARREG(dc, TGA_REG_SISR); 645 if (( reg & 0x00010001) != 0x00010001) { 646 /* Odd. We never set any of the other interrupt enables. */ 647 if ((reg & 0x1f) != 0) { 648 /* Clear the mysterious pending interrupts. */ 649 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 650 TGAREGWB(dc, TGA_REG_SISR, 1); 651 /* This was our interrupt, even if we're puzzled as to why 652 * we got it. Don't make the interrupt handler think it 653 * was a stray. 654 */ 655 return -1; 656 } else { 657 return 0; 658 } 659 } 660 /* if we have something to do, do it */ 661 if (dc->dc_ramdac_intr) { 662 dc->dc_ramdac_intr(dcrc); 663 dc->dc_ramdac_intr = NULL; 664 } 665 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 666 TGAREGWB(dc, TGA_REG_SISR, 1); 667 return (1); 668 } 669 670 paddr_t 671 tga_mmap(v, vs, offset, prot) 672 void *v; 673 void *vs; 674 off_t offset; 675 int prot; 676 { 677 struct tga_softc *sc = v; 678 679 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 680 return -1; 681 682 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 683 offset, prot, BUS_SPACE_MAP_LINEAR)); 684 } 685 686 static int 687 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 688 void *v; 689 const struct wsscreen_descr *type; 690 void **cookiep; 691 int *curxp, *curyp; 692 long *attrp; 693 { 694 struct tga_softc *sc = v; 695 long defattr; 696 697 if (sc->nscreens > 0) 698 return (ENOMEM); 699 700 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 701 *curxp = 0; 702 *curyp = 0; 703 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 704 0, 0, 0, &defattr); 705 *attrp = defattr; 706 sc->nscreens++; 707 return (0); 708 } 709 710 static void 711 tga_free_screen(v, cookie) 712 void *v; 713 void *cookie; 714 { 715 struct tga_softc *sc = v; 716 717 if (sc->sc_dc == &tga_console_dc) 718 panic("tga_free_screen: console"); 719 720 sc->nscreens--; 721 } 722 723 static int 724 tga_show_screen(v, cookie, waitok, cb, cbarg) 725 void *v; 726 void *cookie; 727 int waitok; 728 void (*cb)(void *, int, int); 729 void *cbarg; 730 { 731 732 return (0); 733 } 734 735 int 736 tga_cnattach(iot, memt, pc, bus, device, function) 737 bus_space_tag_t iot, memt; 738 pci_chipset_tag_t pc; 739 int bus, device, function; 740 { 741 struct tga_devconfig *dcp = &tga_console_dc; 742 long defattr; 743 744 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 745 746 /* sanity checks */ 747 if (dcp->dc_vaddr == 0) 748 panic("tga_console(%d, %d): couldn't map memory space", 749 device, function); 750 if (dcp->dc_tgaconf == NULL) 751 panic("tga_console(%d, %d): unknown board configuration", 752 device, function); 753 754 /* 755 * Initialize the RAMDAC but DO NOT allocate any private storage. 756 * Initialization includes disabling cursor, setting a sane 757 * colormap, etc. It will be reinitialized in tgaattach(). 758 */ 759 if (dcp->dc_tga2) { 760 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 761 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 762 tga2_ramdac_rd); 763 else 764 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 765 tga2_ramdac_rd, tga_getdotclock(dcp)); 766 } else { 767 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 768 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 769 tga_ramdac_rd); 770 else { 771 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 772 tga_bt463_rd); 773 } 774 } 775 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 776 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 777 778 return(0); 779 } 780 781 /* 782 * Functions to blank and unblank the display. 783 */ 784 static void 785 tga_blank(dc) 786 struct tga_devconfig *dc; 787 { 788 789 if (!dc->dc_blanked) { 790 dc->dc_blanked = 1; 791 /* XXX */ 792 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 793 } 794 } 795 796 static void 797 tga_unblank(dc) 798 struct tga_devconfig *dc; 799 { 800 801 if (dc->dc_blanked) { 802 dc->dc_blanked = 0; 803 /* XXX */ 804 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 805 } 806 } 807 808 /* 809 * Functions to manipulate the built-in cursor handing hardware. 810 */ 811 int 812 tga_builtin_set_cursor(dc, cursorp) 813 struct tga_devconfig *dc; 814 struct wsdisplay_cursor *cursorp; 815 { 816 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 817 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 818 u_char image[512]; 819 u_int count, v; 820 int error; 821 822 v = cursorp->which; 823 if (v & WSDISPLAY_CURSOR_DOCMAP) { 824 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 825 if (error) 826 return (error); 827 } 828 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 829 if ((u_int)cursorp->size.x != 64 || 830 (u_int)cursorp->size.y > 64) 831 return (EINVAL); 832 /* The cursor is 2 bits deep, and there is no mask */ 833 count = (cursorp->size.y * 64 * 2) / NBBY; 834 error = copyin(cursorp->image, image, count); 835 if (error) 836 return error; 837 } 838 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 839 return EINVAL; 840 841 /* parameters are OK; do it */ 842 if (v & WSDISPLAY_CURSOR_DOCUR) { 843 if (cursorp->enable) 844 /* XXX */ 845 TGAWREG(dc, TGA_REG_VVVR, 846 TGARREG(dc, TGA_REG_VVVR) | 0x04); 847 else 848 /* XXX */ 849 TGAWREG(dc, TGA_REG_VVVR, 850 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 851 } 852 if (v & WSDISPLAY_CURSOR_DOPOS) { 853 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 854 (cursorp->pos.x & 0xfff)); 855 } 856 if (v & WSDISPLAY_CURSOR_DOCMAP) { 857 dcrf->ramdac_set_curcmap(dcrc, cursorp); 858 } 859 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 860 count = ((64 * 2) / NBBY) * cursorp->size.y; 861 TGAWREG(dc, TGA_REG_CCBR, 862 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 863 (cursorp->size.y << 10)); 864 memcpy((char *)(dc->dc_vaddr + 865 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 866 image, count); 867 } 868 return (0); 869 } 870 871 int 872 tga_builtin_get_cursor(dc, cursorp) 873 struct tga_devconfig *dc; 874 struct wsdisplay_cursor *cursorp; 875 { 876 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 877 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 878 int count, error; 879 880 cursorp->which = WSDISPLAY_CURSOR_DOALL & 881 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 882 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 883 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 884 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 885 cursorp->size.x = 64; 886 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 887 888 if (cursorp->image != NULL) { 889 count = (cursorp->size.y * 64 * 2) / NBBY; 890 error = copyout((char *)(dc->dc_vaddr + 891 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 892 cursorp->image, count); 893 if (error) 894 return (error); 895 /* No mask */ 896 } 897 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 898 return (error); 899 } 900 901 int 902 tga_builtin_set_curpos(dc, curposp) 903 struct tga_devconfig *dc; 904 struct wsdisplay_curpos *curposp; 905 { 906 907 TGAWREG(dc, TGA_REG_CXYR, 908 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 909 return (0); 910 } 911 912 int 913 tga_builtin_get_curpos(dc, curposp) 914 struct tga_devconfig *dc; 915 struct wsdisplay_curpos *curposp; 916 { 917 918 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 919 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 920 return (0); 921 } 922 923 int 924 tga_builtin_get_curmax(dc, curposp) 925 struct tga_devconfig *dc; 926 struct wsdisplay_curpos *curposp; 927 { 928 929 curposp->x = curposp->y = 64; 930 return (0); 931 } 932 933 /* 934 * Copy columns (characters) in a row (line). 935 */ 936 static void 937 tga_copycols(id, row, srccol, dstcol, ncols) 938 void *id; 939 int row, srccol, dstcol, ncols; 940 { 941 struct rasops_info *ri = id; 942 int y, srcx, dstx, nx; 943 944 y = ri->ri_font->fontheight * row; 945 srcx = ri->ri_font->fontwidth * srccol; 946 dstx = ri->ri_font->fontwidth * dstcol; 947 nx = ri->ri_font->fontwidth * ncols; 948 949 tga_rop(ri, dstx, y, 950 nx, ri->ri_font->fontheight, RAS_SRC, 951 ri, srcx, y); 952 } 953 954 /* 955 * Copy rows (lines). 956 */ 957 static void 958 tga_copyrows(id, srcrow, dstrow, nrows) 959 void *id; 960 int srcrow, dstrow, nrows; 961 { 962 struct rasops_info *ri = id; 963 int srcy, dsty, ny; 964 965 srcy = ri->ri_font->fontheight * srcrow; 966 dsty = ri->ri_font->fontheight * dstrow; 967 ny = ri->ri_font->fontheight * nrows; 968 969 tga_rop(ri, 0, dsty, 970 ri->ri_emuwidth, ny, RAS_SRC, 971 ri, 0, srcy); 972 } 973 974 /* Do we need the src? */ 975 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 976 977 /* A mapping between our API and the TGA card */ 978 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 979 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 980 }; 981 982 /* 983 * Generic TGA raster op. 984 * This covers all possible raster ops, and 985 * clips the sizes and all of that. 986 */ 987 static int 988 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 989 struct rasops_info *dst; 990 int dx, dy, w, h, rop; 991 struct rasops_info *src; 992 int sx, sy; 993 { 994 if (!dst) 995 return -1; 996 if (needsrc[RAS_GETOP(rop)]) { 997 if (src == NULL) 998 return -1; /* We want a src */ 999 /* Clip against src */ 1000 if (sx < 0) { 1001 w += sx; 1002 sx = 0; 1003 } 1004 if (sy < 0) { 1005 h += sy; 1006 sy = 0; 1007 } 1008 if (sx + w > src->ri_emuwidth) 1009 w = src->ri_emuwidth - sx; 1010 if (sy + h > src->ri_emuheight) 1011 h = src->ri_emuheight - sy; 1012 } else { 1013 if (src != NULL) 1014 return -1; /* We need no src */ 1015 } 1016 /* Clip against dst. We modify src regardless of using it, 1017 * since it really doesn't matter. 1018 */ 1019 if (dx < 0) { 1020 w += dx; 1021 sx -= dx; 1022 dx = 0; 1023 } 1024 if (dy < 0) { 1025 h += dy; 1026 sy -= dy; 1027 dy = 0; 1028 } 1029 if (dx + w > dst->ri_emuwidth) 1030 w = dst->ri_emuwidth - dx; 1031 if (dy + h > dst->ri_emuheight) 1032 h = dst->ri_emuheight - dy; 1033 if (w <= 0 || h <= 0) 1034 return 0; /* Vacuously true; */ 1035 if (!src) { 1036 /* XXX Punt! */ 1037 return -1; 1038 } 1039 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1040 } 1041 1042 1043 1044 /* 1045 * Video to Video raster ops. 1046 * This function deals with all raster ops that have a src and dst 1047 * that are on the card. 1048 */ 1049 static int 1050 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1051 struct rasops_info *dst; 1052 int dx, dy, w, h, rop; 1053 struct rasops_info *src; 1054 int sx, sy; 1055 { 1056 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1057 int srcb, dstb, tga_srcb, tga_dstb; 1058 int x, y, wb; 1059 int xstart, xend, xdir; 1060 int ystart, yend, ydir, yinc; 1061 int xleft, lastx, lastleft; 1062 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1063 1064 /* 1065 * I don't yet want to deal with unaligned guys, really. And we don't 1066 * deal with copies from one card to another. 1067 */ 1068 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1069 /* XXX Punt! */ 1070 /* XXX should never happen, since it's only being used to 1071 * XXX copy 8-pixel-wide characters. 1072 */ 1073 return -1; 1074 } 1075 1076 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1077 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1078 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1079 (sx + src->ri_xorigin) * (src->ri_depth/8); 1080 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1081 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1082 1083 if (sy >= dy) { 1084 ystart = 0; 1085 yend = (h - 1) * dst->ri_stride; 1086 ydir = 1; 1087 } else { 1088 ystart = (h - 1) * dst->ri_stride; 1089 yend = 0; 1090 ydir = -1; 1091 } 1092 yinc = ydir * dst->ri_stride; 1093 1094 wb = w * (dst->ri_depth / 8); 1095 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1096 xstart = 0; 1097 xend = wb; 1098 xdir = 1; 1099 } else { /* copy backwards */ 1100 xstart = wb; 1101 xend = 0; 1102 xdir = -1; 1103 } 1104 1105 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1106 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1107 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1108 1109 /* 1110 * we have 3 sizes of pixels to move in X direction: 1111 * 4 * 64 (unrolled TGA ops) 1112 * 64 (single TGA op) 1113 * 4 (CPU, using long word) 1114 */ 1115 1116 if (xdir == 1) { /* move to the left */ 1117 1118 if (wb & ~63) 1119 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1120 /* 4*64 byte chunks */ 1121 for (xleft = wb, x = xstart; xleft >= 4*64; 1122 x += 4*64, xleft -= 4*64) { 1123 1124 /* XXX XXX Eight writes to different addresses should fill 1125 * XXX XXX up the write buffers on 21064 and 21164 chips, 1126 * XXX XXX but later CPUs might have larger write buffers which 1127 * XXX XXX require further unrolling of this loop, or the 1128 * XXX XXX insertion of memory barriers. 1129 */ 1130 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1131 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1132 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1133 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1134 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1135 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1136 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1137 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1138 } 1139 1140 /* 64 byte chunks */ 1141 for (; xleft >= 64; x += 64, xleft -= 64) { 1142 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1143 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1144 } 1145 } 1146 1147 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1148 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1149 1150 lastleft = wb & 63; 1151 if (lastleft) { 1152 lastx = xstart + (wb & ~63); 1153 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1154 /* 4 byte granularity */ 1155 for (x = lastx, xleft = lastleft; xleft >= 4; 1156 x += 4, xleft -= 4) { 1157 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1158 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1159 } 1160 } 1161 } 1162 } 1163 else { /* above move to the left, below move to the right */ 1164 1165 if (wb & ~63) 1166 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1167 /* 4*64 byte chunks */ 1168 for (xleft = wb, x = xstart; xleft >= 4*64; 1169 x -= 4*64, xleft -= 4*64) { 1170 1171 /* XXX XXX Eight writes to different addresses should fill 1172 * XXX XXX up the write buffers on 21064 and 21164 chips, 1173 * XXX XXX but later CPUs might have larger write buffers which 1174 * XXX XXX require further unrolling of this loop, or the 1175 * XXX XXX insertion of memory barriers. 1176 */ 1177 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1178 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1179 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1180 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1181 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1182 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1183 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1184 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1185 } 1186 1187 /* 64 byte chunks */ 1188 for (; xleft >= 64; x -= 64, xleft -= 64) { 1189 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1190 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1191 } 1192 } 1193 1194 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1195 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1196 1197 lastleft = wb & 63; 1198 if (lastleft) { 1199 lastx = xstart - (wb & ~63); 1200 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1201 /* 4 byte granularity */ 1202 for (x = lastx, xleft = lastleft; xleft >= 4; 1203 x -= 4, xleft -= 4) { 1204 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1205 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1206 } 1207 } 1208 } 1209 } 1210 return 0; 1211 } 1212 1213 1214 void tga_putchar (c, row, col, uc, attr) 1215 void *c; 1216 int row, col; 1217 u_int uc; 1218 long attr; 1219 { 1220 struct rasops_info *ri = c; 1221 struct tga_devconfig *dc = ri->ri_hw; 1222 int fs, height, width; 1223 u_char *fr; 1224 int32_t *rp; 1225 1226 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1227 1228 height = ri->ri_font->fontheight; 1229 width = ri->ri_font->fontwidth; 1230 1231 uc -= ri->ri_font->firstchar; 1232 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1233 fs = ri->ri_font->stride; 1234 1235 /* Set foreground and background color. XXX memoize this somehow? 1236 * The rasops code has already expanded the color entry to 32 bits 1237 * for us, even for 8-bit displays, so we don't have to do anything. 1238 */ 1239 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1240 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1241 1242 /* Set raster operation to "copy"... */ 1243 if (ri->ri_depth == 8) 1244 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1245 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1246 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1247 1248 /* Set which pixels we're drawing (of a possible 32). */ 1249 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1250 1251 /* Set drawing mode to opaque stipple. */ 1252 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1253 1254 /* Insert write barrier before actually sending data */ 1255 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1256 TGAREGWB(dc, TGA_REG_GMOR, 1); 1257 1258 while(height--) { 1259 /* The actual stipple write */ 1260 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1261 1262 fr += fs; 1263 rp = (int32_t *)((char *)rp + ri->ri_stride); 1264 } 1265 1266 /* Do underline */ 1267 if ((attr & 1) != 0) { 1268 rp = (int32_t *)((char *)rp - (ri->ri_stride << 1)); 1269 *rp = 0xffffffff; 1270 } 1271 1272 /* Set grapics mode back to normal. */ 1273 TGAWREG(dc, TGA_REG_GMOR, 0); 1274 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1275 1276 } 1277 1278 static void 1279 tga_eraserows(c, row, num, attr) 1280 void *c; 1281 int row, num; 1282 long attr; 1283 { 1284 struct rasops_info *ri = c; 1285 struct tga_devconfig *dc = ri->ri_hw; 1286 int32_t color, lines, pixels; 1287 int32_t *rp; 1288 1289 color = ri->ri_devcmap[(attr >> 16) & 15]; 1290 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1291 lines = num * ri->ri_font->fontheight; 1292 pixels = ri->ri_emuwidth - 1; 1293 1294 /* Set fill color in block-color registers */ 1295 TGAWREG(dc, TGA_REG_GBCR0, color); 1296 TGAWREG(dc, TGA_REG_GBCR1, color); 1297 if (ri->ri_depth != 8) { 1298 TGAWREG(dc, TGA_REG_GBCR2, color); 1299 TGAWREG(dc, TGA_REG_GBCR3, color); 1300 TGAWREG(dc, TGA_REG_GBCR4, color); 1301 TGAWREG(dc, TGA_REG_GBCR5, color); 1302 TGAWREG(dc, TGA_REG_GBCR6, color); 1303 TGAWREG(dc, TGA_REG_GBCR7, color); 1304 } 1305 1306 /* Set raster operation to "copy"... */ 1307 if (ri->ri_depth == 8) 1308 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1309 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1310 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1311 1312 /* Set which pixels we're drawing (of a possible 32). */ 1313 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1314 1315 /* Set drawing mode to block fill. */ 1316 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1317 1318 /* Insert write barrier before actually sending data */ 1319 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1320 TGAREGWB(dc, TGA_REG_GMOR, 1); 1321 1322 while (lines--) { 1323 *rp = pixels; 1324 rp = (int32_t *)((char *)rp + ri->ri_stride); 1325 } 1326 1327 /* Set grapics mode back to normal. */ 1328 TGAWREG(dc, TGA_REG_GMOR, 0); 1329 1330 } 1331 1332 static void 1333 tga_erasecols (c, row, col, num, attr) 1334 void *c; 1335 int row, col, num; 1336 long attr; 1337 { 1338 struct rasops_info *ri = c; 1339 struct tga_devconfig *dc = ri->ri_hw; 1340 int32_t color, lines, pixels; 1341 int32_t *rp; 1342 1343 color = ri->ri_devcmap[(attr >> 16) & 15]; 1344 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1345 lines = ri->ri_font->fontheight; 1346 pixels = (num * ri->ri_font->fontwidth) - 1; 1347 1348 /* Set fill color in block-color registers */ 1349 TGAWREG(dc, TGA_REG_GBCR0, color); 1350 TGAWREG(dc, TGA_REG_GBCR1, color); 1351 if (ri->ri_depth != 8) { 1352 TGAWREG(dc, TGA_REG_GBCR2, color); 1353 TGAWREG(dc, TGA_REG_GBCR3, color); 1354 TGAWREG(dc, TGA_REG_GBCR4, color); 1355 TGAWREG(dc, TGA_REG_GBCR5, color); 1356 TGAWREG(dc, TGA_REG_GBCR6, color); 1357 TGAWREG(dc, TGA_REG_GBCR7, color); 1358 } 1359 1360 /* Set raster operation to "copy"... */ 1361 if (ri->ri_depth == 8) 1362 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1363 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1364 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1365 1366 /* Set which pixels we're drawing (of a possible 32). */ 1367 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1368 1369 /* Set drawing mode to block fill. */ 1370 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1371 1372 /* Insert write barrier before actually sending data */ 1373 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1374 TGAREGWB(dc, TGA_REG_GMOR, 1); 1375 1376 while (lines--) { 1377 *rp = pixels; 1378 rp = (int32_t *)((char *)rp + ri->ri_stride); 1379 } 1380 1381 /* Set grapics mode back to normal. */ 1382 TGAWREG(dc, TGA_REG_GMOR, 0); 1383 } 1384 1385 1386 static void 1387 tga_ramdac_wr(v, btreg, val) 1388 void *v; 1389 u_int btreg; 1390 u_int8_t val; 1391 { 1392 struct tga_devconfig *dc = v; 1393 1394 if (btreg > BT485_REG_MAX) 1395 panic("tga_ramdac_wr: reg %d out of range", btreg); 1396 1397 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1398 TGAREGWB(dc, TGA_REG_EPDR, 1); 1399 } 1400 1401 static void 1402 tga2_ramdac_wr(v, btreg, val) 1403 void *v; 1404 u_int btreg; 1405 u_int8_t val; 1406 { 1407 struct tga_devconfig *dc = v; 1408 bus_space_handle_t ramdac; 1409 1410 if (btreg > BT485_REG_MAX) 1411 panic("tga_ramdac_wr: reg %d out of range", btreg); 1412 1413 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1414 (0xe << 12) + (btreg << 8), 4, &ramdac); 1415 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1416 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1417 } 1418 1419 static u_int8_t 1420 tga_bt463_rd(v, btreg) 1421 void *v; 1422 u_int btreg; 1423 { 1424 struct tga_devconfig *dc = v; 1425 tga_reg_t rdval; 1426 1427 /* 1428 * Strobe CE# (high->low->high) since status and data are latched on 1429 * the falling and rising edges (repsectively) of this active-low signal. 1430 */ 1431 1432 TGAREGWB(dc, TGA_REG_EPSR, 1); 1433 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1434 TGAREGWB(dc, TGA_REG_EPSR, 1); 1435 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1436 1437 TGAREGRB(dc, TGA_REG_EPSR, 1); 1438 1439 rdval = TGARREG(dc, TGA_REG_EPDR); 1440 TGAREGWB(dc, TGA_REG_EPSR, 1); 1441 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1442 1443 return (rdval >> 16) & 0xff; 1444 } 1445 1446 static void 1447 tga_bt463_wr(v, btreg, val) 1448 void *v; 1449 u_int btreg; 1450 u_int8_t val; 1451 { 1452 struct tga_devconfig *dc = v; 1453 1454 /* 1455 * In spite of the 21030 documentation, to set the MPU bus bits for 1456 * a write, you set them in the upper bits of EPDR, not EPSR. 1457 */ 1458 1459 /* 1460 * Strobe CE# (high->low->high) since status and data are latched on 1461 * the falling and rising edges of this active-low signal. 1462 */ 1463 1464 TGAREGWB(dc, TGA_REG_EPDR, 1); 1465 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1466 TGAREGWB(dc, TGA_REG_EPDR, 1); 1467 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1468 TGAREGWB(dc, TGA_REG_EPDR, 1); 1469 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1470 1471 } 1472 1473 static u_int8_t 1474 tga_ramdac_rd(v, btreg) 1475 void *v; 1476 u_int btreg; 1477 { 1478 struct tga_devconfig *dc = v; 1479 tga_reg_t rdval; 1480 1481 if (btreg > BT485_REG_MAX) 1482 panic("tga_ramdac_rd: reg %d out of range", btreg); 1483 1484 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1485 TGAREGWB(dc, TGA_REG_EPSR, 1); 1486 1487 rdval = TGARREG(dc, TGA_REG_EPDR); 1488 return (rdval >> 16) & 0xff; /* XXX */ 1489 } 1490 1491 static u_int8_t 1492 tga2_ramdac_rd(v, btreg) 1493 void *v; 1494 u_int btreg; 1495 { 1496 struct tga_devconfig *dc = v; 1497 bus_space_handle_t ramdac; 1498 u_int8_t retval; 1499 1500 if (btreg > BT485_REG_MAX) 1501 panic("tga_ramdac_rd: reg %d out of range", btreg); 1502 1503 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1504 (0xe << 12) + (btreg << 8), 4, &ramdac); 1505 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1506 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1507 return retval; 1508 } 1509 1510 #include <dev/ic/decmonitors.c> 1511 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1512 1513 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1514 1515 void 1516 tga2_init(dc) 1517 struct tga_devconfig *dc; 1518 { 1519 struct monitor *m = tga_getmonitor(dc); 1520 1521 /* Deal with the dot clocks. 1522 */ 1523 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1524 /* Set this up as a reference clock for the 1525 * ibm561's PLL. 1526 */ 1527 tga2_ics9110_wr(dc, 14300000); 1528 /* XXX Can't set up the dotclock properly, until such time 1529 * as the RAMDAC is configured. 1530 */ 1531 } else { 1532 /* otherwise the ics9110 is our clock. */ 1533 tga2_ics9110_wr(dc, m->dotclock); 1534 } 1535 #if 0 1536 TGAWREG(dc, TGA_REG_VHCR, 1537 ((m->hbp / 4) << 21) | 1538 ((m->hsync / 4) << 14) | 1539 (((m->hfp - 4) / 4) << 9) | 1540 ((m->cols + 4) / 4)); 1541 #else 1542 TGAWREG(dc, TGA_REG_VHCR, 1543 ((m->hbp / 4) << 21) | 1544 ((m->hsync / 4) << 14) | 1545 (((m->hfp) / 4) << 9) | 1546 ((m->cols) / 4)); 1547 #endif 1548 TGAWREG(dc, TGA_REG_VVCR, 1549 (m->vbp << 22) | 1550 (m->vsync << 16) | 1551 (m->vfp << 11) | 1552 (m->rows)); 1553 TGAWREG(dc, TGA_REG_VVBR, 1); 1554 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1555 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1556 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1557 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1558 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1559 } 1560 1561 void 1562 tga2_ics9110_wr(dc, dotclock) 1563 struct tga_devconfig *dc; 1564 int dotclock; 1565 { 1566 bus_space_handle_t clock; 1567 u_int32_t valU; 1568 int N, M, R, V, X; 1569 int i; 1570 1571 switch (dotclock) { 1572 case 130808000: 1573 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1574 case 119840000: 1575 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1576 case 108180000: 1577 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1578 case 103994000: 1579 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1580 case 175000000: 1581 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1582 case 75000000: 1583 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1584 case 74000000: 1585 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1586 case 69000000: 1587 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1588 case 65000000: 1589 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1590 case 50000000: 1591 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1592 case 40000000: 1593 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1594 case 31500000: 1595 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1596 case 25175000: 1597 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1598 case 135000000: 1599 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1600 case 110000000: 1601 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1602 case 202500000: 1603 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1604 case 14300000: /* this one is just a ref clock */ 1605 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1606 default: 1607 panic("unrecognized clock rate %d", dotclock); 1608 } 1609 1610 /* XXX -- hard coded, bad */ 1611 valU = N | ( M << 7 ) | (V << 14); 1612 valU |= (X << 15) | (R << 17); 1613 valU |= 0x17 << 19; 1614 1615 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1616 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1617 1618 for (i=24; i>0; i--) { 1619 u_int32_t writeval; 1620 1621 writeval = valU & 0x1; 1622 if (i == 1) 1623 writeval |= 0x2; 1624 valU >>= 1; 1625 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1626 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1627 } 1628 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1629 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1630 &clock); /* XXX */ 1631 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1632 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1633 } 1634 1635 struct monitor * 1636 tga_getmonitor(dc) 1637 struct tga_devconfig *dc; 1638 { 1639 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1640 } 1641 1642 unsigned 1643 tga_getdotclock(dc) 1644 struct tga_devconfig *dc; 1645 { 1646 return tga_getmonitor(dc)->dotclock; 1647 } 1648