1 /* $NetBSD: tga.c,v 1.36 2001/09/04 06:59:10 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/ioctl.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/tgareg.h> 46 #include <dev/pci/tgavar.h> 47 #include <dev/ic/bt485reg.h> 48 #include <dev/ic/bt485var.h> 49 #include <dev/ic/bt463reg.h> 50 #include <dev/ic/bt463var.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wscons_raster.h> 54 #include <dev/rasops/rasops.h> 55 #include <dev/wsfont/wsfont.h> 56 #include <uvm/uvm_extern.h> 57 58 #ifdef __alpha__ 59 #include <machine/pte.h> 60 #endif 61 #ifdef __mips__ 62 #include <mips/pte.h> 63 #endif 64 65 int tgamatch __P((struct device *, struct cfdata *, void *)); 66 void tgaattach __P((struct device *, struct device *, void *)); 67 int tgaprint __P((void *, const char *)); 68 69 struct cfattach tga_ca = { 70 sizeof(struct tga_softc), tgamatch, tgaattach, 71 }; 72 73 int tga_identify __P((struct tga_devconfig *)); 74 const struct tga_conf *tga_getconf __P((int)); 75 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 76 pcitag_t tag, struct tga_devconfig *dc)); 77 78 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 79 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 80 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 81 82 struct tga_devconfig tga_console_dc; 83 84 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 85 paddr_t tga_mmap __P((void *, off_t, int)); 86 static void tga_copyrows __P((void *, int, int, int)); 87 static void tga_copycols __P((void *, int, int, int, int)); 88 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 89 void **, int *, int *, long *)); 90 static void tga_free_screen __P((void *, void *)); 91 static int tga_show_screen __P((void *, void *, int, 92 void (*) (void *, int, int), void *)); 93 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 94 struct rasops_info *, int, int)); 95 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 96 int, struct rasops_info *, int, int )); 97 static void tga_putchar __P((void *c, int row, int col, 98 u_int uc, long attr)); 99 static void tga_eraserows __P((void *, int, int, long)); 100 static void tga_erasecols __P((void *, int, int, int, long)); 101 void tga2_init __P((struct tga_devconfig *, int)); 102 103 static void tga_config_interrupts __P((struct device *)); 104 105 /* RAMDAC interface functions */ 106 static int tga_sched_update __P((void *, void (*)(void *))); 107 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 108 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 109 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 110 static u_int8_t tga_bt463_rd __P((void *, u_int)); 111 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 112 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 113 114 /* Interrupt handler */ 115 static int tga_intr __P((void *)); 116 117 /* The NULL entries will get filled in by rasops_init(). 118 * XXX and the non-NULL ones will be overwritten; reset after calling it. 119 */ 120 struct wsdisplay_emulops tga_emulops = { 121 NULL, 122 NULL, 123 tga_putchar, 124 tga_copycols, 125 tga_erasecols, 126 tga_copyrows, 127 tga_eraserows, 128 NULL, 129 }; 130 131 struct wsscreen_descr tga_stdscreen = { 132 "std", 133 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 134 &tga_emulops, 135 0, 0, 136 WSSCREEN_REVERSE 137 }; 138 139 const struct wsscreen_descr *_tga_scrlist[] = { 140 &tga_stdscreen, 141 /* XXX other formats, graphics screen? */ 142 }; 143 144 struct wsscreen_list tga_screenlist = { 145 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 146 }; 147 148 struct wsdisplay_accessops tga_accessops = { 149 tga_ioctl, 150 tga_mmap, 151 tga_alloc_screen, 152 tga_free_screen, 153 tga_show_screen, 154 0 /* load_font */ 155 }; 156 157 static void tga_blank __P((struct tga_devconfig *)); 158 static void tga_unblank __P((struct tga_devconfig *)); 159 160 int 161 tga_cnmatch(iot, memt, pc, tag) 162 bus_space_tag_t iot, memt; 163 pci_chipset_tag_t pc; 164 pcitag_t tag; 165 { 166 return tga_matchcommon(memt, pc, tag); 167 } 168 169 int 170 tgamatch(parent, match, aux) 171 struct device *parent; 172 struct cfdata *match; 173 void *aux; 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 178 return (0); 179 180 switch (PCI_PRODUCT(pa->pa_id)) { 181 case PCI_PRODUCT_DEC_21030: 182 case PCI_PRODUCT_DEC_PBXGB: 183 break; 184 default: 185 return 0; 186 } 187 188 /* short-circuit the following test, as we 189 * already have the memory mapped and hence 190 * cannot perform it---and we are the console 191 * anyway. 192 */ 193 if (pa->pa_tag == tga_console_dc.dc_pcitag) 194 return 10; 195 196 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 197 } 198 199 static int 200 tga_matchcommon(memt, pc, tag) 201 bus_space_tag_t memt; 202 pci_chipset_tag_t pc; 203 pcitag_t tag; 204 { 205 struct tga_devconfig tmp_dc; 206 struct tga_devconfig *dc = &tmp_dc; 207 bus_size_t pcisize; 208 209 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 210 dc->dc_tga_type = tga_identify(dc); 211 212 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 213 bus_space_unmap(memt, dc->dc_memh, pcisize); 214 if (dc->dc_tgaconf) 215 return 10; 216 return 0; 217 } 218 219 static void 220 tga_mapaddrs(memt, pc, tag, pcisize, dc) 221 bus_space_tag_t memt; 222 pci_chipset_tag_t pc; 223 pcitag_t tag; 224 bus_size_t *pcisize; 225 struct tga_devconfig *dc; 226 { 227 int flags; 228 229 dc->dc_memt = memt; 230 dc->dc_tgaconf = NULL; 231 232 /* XXX magic number */ 233 if (pci_mapreg_info(pc, tag, 0x10, 234 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 235 &dc->dc_pcipaddr, pcisize, &flags)) 236 panic("tga_mapaddrs: pci_mapreg_info() failed"); 237 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 238 panic("tga memory not prefetchable"); 239 240 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 241 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 242 panic("tga_mapaddrs: could not map TGA address space"); 243 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 244 245 bus_space_subregion(dc->dc_memt, dc->dc_memh, 246 TGA_MEM_CREGS, TGA_CREGS_SIZE, 247 &dc->dc_regs); 248 } 249 250 static void 251 tga_init(memt, pc, tag, dc) 252 bus_space_tag_t memt; 253 pci_chipset_tag_t pc; 254 pcitag_t tag; 255 struct tga_devconfig *dc; 256 { 257 const struct tga_conf *tgac; 258 struct rasops_info *rip; 259 int cookie; 260 bus_size_t pcisize; 261 int i; 262 263 dc->dc_pcitag = tag; 264 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 265 dc->dc_tga_type = tga_identify(dc); 266 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 267 #if 0 268 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 269 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 270 panic("tga_init: memory size mismatch?"); 271 #endif 272 273 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 274 case 0x01: 275 case 0x02: 276 case 0x03: 277 case 0x04: 278 dc->dc_tga2 = 0; 279 break; 280 case 0x20: 281 case 0x21: 282 case 0x22: 283 dc->dc_tga2 = 1; 284 break; 285 default: 286 panic("tga_init: TGA Revision not recognized"); 287 } 288 289 if (dc->dc_tga2) { 290 int monitor; 291 292 monitor = (~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f; 293 tga2_init(dc, monitor); 294 } 295 296 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 297 case 0: 298 dc->dc_wid = 8192; 299 break; 300 301 case 1: 302 dc->dc_wid = 8196; 303 break; 304 305 default: 306 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 307 break; 308 } 309 310 /* 311 * XXX XXX Turning off "odd" shouldn't be necessary, 312 * XXX XXX but I can't make X work with the weird size. 313 */ 314 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 315 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 316 TGAWREG(dc, TGA_REG_VHCR, 317 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 318 dc->dc_wid -= 4; 319 } 320 321 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 322 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 323 324 /* XXX this seems to be what DEC does */ 325 TGAWREG(dc, TGA_REG_CCBR, 0); 326 TGAWREG(dc, TGA_REG_VVBR, 1); 327 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 328 1 * tgac->tgac_vvbr_units; 329 dc->dc_blanked = 1; 330 tga_unblank(dc); 331 332 /* 333 * Set all bits in the pixel mask, to enable writes to all pixels. 334 * It seems that the console firmware clears some of them 335 * under some circumstances, which causes cute vertical stripes. 336 */ 337 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 338 339 /* clear the screen */ 340 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 341 *(u_int32_t *)(dc->dc_videobase + i) = 0; 342 343 /* Initialize rasops descriptor */ 344 rip = &dc->dc_rinfo; 345 rip->ri_flg = RI_CENTER; 346 rip->ri_depth = tgac->tgac_phys_depth; 347 rip->ri_bits = (void *)dc->dc_videobase; 348 rip->ri_width = dc->dc_wid; 349 rip->ri_height = dc->dc_ht; 350 rip->ri_stride = dc->dc_rowbytes; 351 rip->ri_hw = dc; 352 353 if (tgac->tgac_phys_depth == 32) { 354 rip->ri_rnum = 8; 355 rip->ri_gnum = 8; 356 rip->ri_bnum = 8; 357 rip->ri_rpos = 16; 358 rip->ri_gpos = 8; 359 rip->ri_bpos = 0; 360 } 361 362 wsfont_init(); 363 /* prefer 8 pixel wide font */ 364 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0) 365 cookie = wsfont_find(NULL, 0, 0, 0); 366 if (cookie <= 0) { 367 printf("tga: no appropriate fonts.\n"); 368 return; 369 } 370 371 /* the accelerated tga_putchar() needs LSbit left */ 372 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font, 373 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 374 printf("tga: couldn't lock font\n"); 375 return; 376 } 377 dc->dc_rinfo.ri_wsfcookie = cookie; 378 379 rasops_init(rip, 34, 80); 380 381 /* add our accelerated functions */ 382 /* XXX shouldn't have to do this; rasops should leave non-NULL 383 * XXX entries alone. 384 */ 385 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 386 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 387 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 388 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 389 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 390 391 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 392 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 393 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 394 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 395 396 397 dc->dc_intrenabled = 0; 398 } 399 400 void 401 tgaattach(parent, self, aux) 402 struct device *parent, *self; 403 void *aux; 404 { 405 struct pci_attach_args *pa = aux; 406 struct tga_softc *sc = (struct tga_softc *)self; 407 struct wsemuldisplaydev_attach_args aa; 408 pci_intr_handle_t intrh; 409 const char *intrstr; 410 u_int8_t rev; 411 int console; 412 413 #if defined(__alpha__) || defined(arc) 414 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 415 #else 416 console = 0; 417 #endif 418 if (console) { 419 sc->sc_dc = &tga_console_dc; 420 sc->nscreens = 1; 421 } else { 422 sc->sc_dc = (struct tga_devconfig *) 423 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK); 424 memset(sc->sc_dc, 0, sizeof(struct tga_devconfig)); 425 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 426 } 427 if (sc->sc_dc->dc_vaddr == NULL) { 428 printf(": couldn't map memory space; punt!\n"); 429 return; 430 } 431 432 /* XXX say what's going on. */ 433 intrstr = NULL; 434 if (pci_intr_map(pa, &intrh)) { 435 printf(": couldn't map interrupt"); 436 return; 437 } 438 intrstr = pci_intr_string(pa->pa_pc, intrh); 439 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 440 sc->sc_dc); 441 if (sc->sc_intr == NULL) { 442 printf(": couldn't establish interrupt"); 443 if (intrstr != NULL) 444 printf("at %s", intrstr); 445 printf("\n"); 446 return; 447 } 448 449 rev = PCI_REVISION(pa->pa_class); 450 switch (rev) { 451 case 0x1: 452 case 0x2: 453 case 0x3: 454 printf(": DC21030 step %c", 'A' + rev - 1); 455 break; 456 case 0x20: 457 printf(": TGA2 abstract software model"); 458 break; 459 case 0x21: 460 case 0x22: 461 printf(": TGA2 pass %d", rev - 0x20); 462 break; 463 464 default: 465 printf("unknown stepping (0x%x)", rev); 466 break; 467 } 468 printf(", "); 469 470 /* 471 * Get RAMDAC function vectors and call the RAMDAC functions 472 * to allocate its private storage and pass that back to us. 473 */ 474 475 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 476 if (!sc->sc_dc->dc_tga2) { 477 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 478 sc->sc_dc->dc_ramdac_cookie = 479 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 480 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 481 else 482 sc->sc_dc->dc_ramdac_cookie = 483 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 484 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 485 } else { 486 sc->sc_dc->dc_ramdac_cookie = 487 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 488 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 489 } 490 491 /* 492 * Initialize the RAMDAC. Initialization includes disabling 493 * cursor, setting a sane colormap, etc. 494 */ 495 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 496 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 497 498 if (sc->sc_dc->dc_tgaconf == NULL) { 499 printf("unknown board configuration\n"); 500 return; 501 } 502 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 503 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 504 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 505 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 506 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 507 508 if (intrstr != NULL) 509 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 510 intrstr); 511 512 aa.console = console; 513 aa.scrdata = &tga_screenlist; 514 aa.accessops = &tga_accessops; 515 aa.accesscookie = sc; 516 517 config_found(self, &aa, wsemuldisplaydevprint); 518 519 config_interrupts(self, tga_config_interrupts); 520 } 521 522 static void 523 tga_config_interrupts (d) 524 struct device *d; 525 { 526 struct tga_softc *sc = (struct tga_softc *)d; 527 sc->sc_dc->dc_intrenabled = 1; 528 } 529 530 int 531 tga_ioctl(v, cmd, data, flag, p) 532 void *v; 533 u_long cmd; 534 caddr_t data; 535 int flag; 536 struct proc *p; 537 { 538 struct tga_softc *sc = v; 539 struct tga_devconfig *dc = sc->sc_dc; 540 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 541 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 542 543 switch (cmd) { 544 case WSDISPLAYIO_GTYPE: 545 *(u_int *)data = WSDISPLAY_TYPE_TGA; 546 return (0); 547 548 case WSDISPLAYIO_GINFO: 549 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 550 wsd_fbip->height = sc->sc_dc->dc_ht; 551 wsd_fbip->width = sc->sc_dc->dc_wid; 552 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 553 wsd_fbip->cmsize = 256; /* XXX ??? */ 554 #undef wsd_fbip 555 return (0); 556 557 case WSDISPLAYIO_GETCMAP: 558 return (*dcrf->ramdac_get_cmap)(dcrc, 559 (struct wsdisplay_cmap *)data); 560 561 case WSDISPLAYIO_PUTCMAP: 562 return (*dcrf->ramdac_set_cmap)(dcrc, 563 (struct wsdisplay_cmap *)data); 564 565 case WSDISPLAYIO_SVIDEO: 566 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 567 tga_blank(sc->sc_dc); 568 else 569 tga_unblank(sc->sc_dc); 570 return (0); 571 572 case WSDISPLAYIO_GVIDEO: 573 *(u_int *)data = dc->dc_blanked ? 574 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 575 return (0); 576 577 case WSDISPLAYIO_GCURPOS: 578 return (*dcrf->ramdac_get_curpos)(dcrc, 579 (struct wsdisplay_curpos *)data); 580 581 case WSDISPLAYIO_SCURPOS: 582 return (*dcrf->ramdac_set_curpos)(dcrc, 583 (struct wsdisplay_curpos *)data); 584 585 case WSDISPLAYIO_GCURMAX: 586 return (*dcrf->ramdac_get_curmax)(dcrc, 587 (struct wsdisplay_curpos *)data); 588 589 case WSDISPLAYIO_GCURSOR: 590 return (*dcrf->ramdac_get_cursor)(dcrc, 591 (struct wsdisplay_cursor *)data); 592 593 case WSDISPLAYIO_SCURSOR: 594 return (*dcrf->ramdac_set_cursor)(dcrc, 595 (struct wsdisplay_cursor *)data); 596 } 597 return (-1); 598 } 599 600 static int 601 tga_sched_update(v, f) 602 void *v; 603 void (*f) __P((void *)); 604 { 605 struct tga_devconfig *dc = v; 606 607 if (dc->dc_intrenabled) { 608 /* Arrange for f to be called at the next end-of-frame interrupt */ 609 dc->dc_ramdac_intr = f; 610 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 611 } else { 612 /* Spin until the end-of-frame, then call f */ 613 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 614 TGAREGWB(dc, TGA_REG_SISR, 1); 615 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 616 ; 617 f(dc->dc_ramdac_cookie); 618 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 619 TGAREGWB(dc, TGA_REG_SISR, 1); 620 } 621 622 return 0; 623 } 624 625 static int 626 tga_intr(v) 627 void *v; 628 { 629 struct tga_devconfig *dc = v; 630 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 631 632 u_int32_t reg; 633 634 reg = TGARREG(dc, TGA_REG_SISR); 635 if (( reg & 0x00010001) != 0x00010001) { 636 /* Odd. We never set any of the other interrupt enables. */ 637 if ((reg & 0x1f) != 0) { 638 /* Clear the mysterious pending interrupts. */ 639 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 640 TGAREGWB(dc, TGA_REG_SISR, 1); 641 /* This was our interrupt, even if we're puzzled as to why 642 * we got it. Don't make the interrupt handler think it 643 * was a stray. 644 */ 645 return -1; 646 } else { 647 return 0; 648 } 649 } 650 /* if we have something to do, do it */ 651 if (dc->dc_ramdac_intr) { 652 dc->dc_ramdac_intr(dcrc); 653 dc->dc_ramdac_intr = NULL; 654 } 655 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 656 TGAREGWB(dc, TGA_REG_SISR, 1); 657 return (1); 658 } 659 660 paddr_t 661 tga_mmap(v, offset, prot) 662 void *v; 663 off_t offset; 664 int prot; 665 { 666 struct tga_softc *sc = v; 667 668 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 669 return -1; 670 671 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 672 offset, prot, BUS_SPACE_MAP_LINEAR)); 673 } 674 675 static int 676 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 677 void *v; 678 const struct wsscreen_descr *type; 679 void **cookiep; 680 int *curxp, *curyp; 681 long *attrp; 682 { 683 struct tga_softc *sc = v; 684 long defattr; 685 686 if (sc->nscreens > 0) 687 return (ENOMEM); 688 689 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 690 *curxp = 0; 691 *curyp = 0; 692 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 693 0, 0, 0, &defattr); 694 *attrp = defattr; 695 sc->nscreens++; 696 return (0); 697 } 698 699 static void 700 tga_free_screen(v, cookie) 701 void *v; 702 void *cookie; 703 { 704 struct tga_softc *sc = v; 705 706 if (sc->sc_dc == &tga_console_dc) 707 panic("tga_free_screen: console"); 708 709 sc->nscreens--; 710 } 711 712 static int 713 tga_show_screen(v, cookie, waitok, cb, cbarg) 714 void *v; 715 void *cookie; 716 int waitok; 717 void (*cb) __P((void *, int, int)); 718 void *cbarg; 719 { 720 721 return (0); 722 } 723 724 int 725 tga_cnattach(iot, memt, pc, bus, device, function) 726 bus_space_tag_t iot, memt; 727 pci_chipset_tag_t pc; 728 int bus, device, function; 729 { 730 struct tga_devconfig *dcp = &tga_console_dc; 731 long defattr; 732 733 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 734 735 /* sanity checks */ 736 if (dcp->dc_vaddr == NULL) 737 panic("tga_console(%d, %d): couldn't map memory space", 738 device, function); 739 if (dcp->dc_tgaconf == NULL) 740 panic("tga_console(%d, %d): unknown board configuration", 741 device, function); 742 743 /* 744 * Initialize the RAMDAC but DO NOT allocate any private storage. 745 * Initialization includes disabling cursor, setting a sane 746 * colormap, etc. It will be reinitialized in tgaattach(). 747 */ 748 if (dcp->dc_tga2) 749 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 750 tga2_ramdac_rd); 751 else { 752 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 753 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 754 tga_ramdac_rd); 755 else { 756 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 757 tga_bt463_rd); 758 } 759 } 760 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 761 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 762 763 return(0); 764 } 765 766 /* 767 * Functions to blank and unblank the display. 768 */ 769 static void 770 tga_blank(dc) 771 struct tga_devconfig *dc; 772 { 773 774 if (!dc->dc_blanked) { 775 dc->dc_blanked = 1; 776 /* XXX */ 777 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 778 } 779 } 780 781 static void 782 tga_unblank(dc) 783 struct tga_devconfig *dc; 784 { 785 786 if (dc->dc_blanked) { 787 dc->dc_blanked = 0; 788 /* XXX */ 789 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 790 } 791 } 792 793 /* 794 * Functions to manipulate the built-in cursor handing hardware. 795 */ 796 int 797 tga_builtin_set_cursor(dc, cursorp) 798 struct tga_devconfig *dc; 799 struct wsdisplay_cursor *cursorp; 800 { 801 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 802 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 803 u_int count, v; 804 int error; 805 806 v = cursorp->which; 807 if (v & WSDISPLAY_CURSOR_DOCMAP) { 808 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 809 if (error) 810 return (error); 811 } 812 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 813 if ((u_int)cursorp->size.x != 64 || 814 (u_int)cursorp->size.y > 64) 815 return (EINVAL); 816 /* The cursor is 2 bits deep, and there is no mask */ 817 count = (cursorp->size.y * 64 * 2) / NBBY; 818 if (!uvm_useracc(cursorp->image, count, B_READ)) 819 return (EFAULT); 820 } 821 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 822 return EINVAL; 823 824 /* parameters are OK; do it */ 825 if (v & WSDISPLAY_CURSOR_DOCUR) { 826 if (cursorp->enable) 827 /* XXX */ 828 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 829 else 830 /* XXX */ 831 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 832 } 833 if (v & WSDISPLAY_CURSOR_DOPOS) { 834 TGAWREG(dc, TGA_REG_CXYR, 835 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 836 } 837 if (v & WSDISPLAY_CURSOR_DOCMAP) { 838 /* can't fail. */ 839 dcrf->ramdac_set_curcmap(dcrc, cursorp); 840 } 841 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 842 count = ((64 * 2) / NBBY) * cursorp->size.y; 843 TGAWREG(dc, TGA_REG_CCBR, 844 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 845 copyin(cursorp->image, (char *)(dc->dc_vaddr + 846 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 847 count); /* can't fail. */ 848 } 849 return (0); 850 } 851 852 int 853 tga_builtin_get_cursor(dc, cursorp) 854 struct tga_devconfig *dc; 855 struct wsdisplay_cursor *cursorp; 856 { 857 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 858 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 859 int count, error; 860 861 cursorp->which = WSDISPLAY_CURSOR_DOALL & 862 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 863 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 864 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 865 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 866 cursorp->size.x = 64; 867 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 868 869 if (cursorp->image != NULL) { 870 count = (cursorp->size.y * 64 * 2) / NBBY; 871 error = copyout((char *)(dc->dc_vaddr + 872 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 873 cursorp->image, count); 874 if (error) 875 return (error); 876 /* No mask */ 877 } 878 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 879 return (error); 880 } 881 882 int 883 tga_builtin_set_curpos(dc, curposp) 884 struct tga_devconfig *dc; 885 struct wsdisplay_curpos *curposp; 886 { 887 888 TGAWREG(dc, TGA_REG_CXYR, 889 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 890 return (0); 891 } 892 893 int 894 tga_builtin_get_curpos(dc, curposp) 895 struct tga_devconfig *dc; 896 struct wsdisplay_curpos *curposp; 897 { 898 899 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 900 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 901 return (0); 902 } 903 904 int 905 tga_builtin_get_curmax(dc, curposp) 906 struct tga_devconfig *dc; 907 struct wsdisplay_curpos *curposp; 908 { 909 910 curposp->x = curposp->y = 64; 911 return (0); 912 } 913 914 /* 915 * Copy columns (characters) in a row (line). 916 */ 917 static void 918 tga_copycols(id, row, srccol, dstcol, ncols) 919 void *id; 920 int row, srccol, dstcol, ncols; 921 { 922 struct rasops_info *ri = id; 923 int y, srcx, dstx, nx; 924 925 y = ri->ri_font->fontheight * row; 926 srcx = ri->ri_font->fontwidth * srccol; 927 dstx = ri->ri_font->fontwidth * dstcol; 928 nx = ri->ri_font->fontwidth * ncols; 929 930 tga_rop(ri, dstx, y, 931 nx, ri->ri_font->fontheight, RAS_SRC, 932 ri, srcx, y); 933 } 934 935 /* 936 * Copy rows (lines). 937 */ 938 static void 939 tga_copyrows(id, srcrow, dstrow, nrows) 940 void *id; 941 int srcrow, dstrow, nrows; 942 { 943 struct rasops_info *ri = id; 944 int srcy, dsty, ny; 945 946 srcy = ri->ri_font->fontheight * srcrow; 947 dsty = ri->ri_font->fontheight * dstrow; 948 ny = ri->ri_font->fontheight * nrows; 949 950 tga_rop(ri, 0, dsty, 951 ri->ri_emuwidth, ny, RAS_SRC, 952 ri, 0, srcy); 953 } 954 955 /* Do we need the src? */ 956 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 957 958 /* A mapping between our API and the TGA card */ 959 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 960 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 961 }; 962 963 /* 964 * Generic TGA raster op. 965 * This covers all possible raster ops, and 966 * clips the sizes and all of that. 967 */ 968 static int 969 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 970 struct rasops_info *dst; 971 int dx, dy, w, h, rop; 972 struct rasops_info *src; 973 int sx, sy; 974 { 975 if (!dst) 976 return -1; 977 if (needsrc[RAS_GETOP(rop)]) { 978 if (src == NULL) 979 return -1; /* We want a src */ 980 /* Clip against src */ 981 if (sx < 0) { 982 w += sx; 983 sx = 0; 984 } 985 if (sy < 0) { 986 h += sy; 987 sy = 0; 988 } 989 if (sx + w > src->ri_emuwidth) 990 w = src->ri_emuwidth - sx; 991 if (sy + h > src->ri_emuheight) 992 h = src->ri_emuheight - sy; 993 } else { 994 if (src != NULL) 995 return -1; /* We need no src */ 996 } 997 /* Clip against dst. We modify src regardless of using it, 998 * since it really doesn't matter. 999 */ 1000 if (dx < 0) { 1001 w += dx; 1002 sx -= dx; 1003 dx = 0; 1004 } 1005 if (dy < 0) { 1006 h += dy; 1007 sy -= dy; 1008 dy = 0; 1009 } 1010 if (dx + w > dst->ri_emuwidth) 1011 w = dst->ri_emuwidth - dx; 1012 if (dy + h > dst->ri_emuheight) 1013 h = dst->ri_emuheight - dy; 1014 if (w <= 0 || h <= 0) 1015 return 0; /* Vacuously true; */ 1016 if (!src) { 1017 /* XXX Punt! */ 1018 return -1; 1019 } 1020 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1021 } 1022 1023 1024 1025 /* 1026 * Video to Video raster ops. 1027 * This function deals with all raster ops that have a src and dst 1028 * that are on the card. 1029 */ 1030 static int 1031 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1032 struct rasops_info *dst; 1033 int dx, dy, w, h, rop; 1034 struct rasops_info *src; 1035 int sx, sy; 1036 { 1037 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1038 int srcb, dstb, tga_srcb, tga_dstb; 1039 int x, y, wb; 1040 int xstart, xend, xdir; 1041 int ystart, yend, ydir, yinc; 1042 int xleft, lastx, lastleft; 1043 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1044 1045 /* 1046 * I don't yet want to deal with unaligned guys, really. And we don't 1047 * deal with copies from one card to another. 1048 */ 1049 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1050 /* XXX Punt! */ 1051 /* XXX should never happen, since it's only being used to 1052 * XXX copy 8-pixel-wide characters. 1053 */ 1054 return -1; 1055 } 1056 1057 wb = w * (dst->ri_depth / 8); 1058 if (sy >= dy) { 1059 ystart = 0; 1060 yend = h; 1061 ydir = 1; 1062 } else { 1063 ystart = h; 1064 yend = 0; 1065 ydir = -1; 1066 } 1067 if (sx >= dx) { /* moving to the left */ 1068 xstart = 0; 1069 xend = w * (dst->ri_depth / 8) - 4; 1070 xdir = 1; 1071 } else { /* moving to the right */ 1072 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 ); 1073 xend = 0; 1074 xdir = -1; 1075 } 1076 #define XINC4 4 1077 #define XINC64 64 1078 #define XINC256 (64*4) 1079 yinc = ydir * dst->ri_stride; 1080 ystart *= dst->ri_stride; 1081 yend *= dst->ri_stride; 1082 1083 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1084 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1085 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1086 (sx + src->ri_xorigin) * (src->ri_depth/8); 1087 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1088 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1089 1090 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1091 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1092 1093 /* 1094 * we have 3 sizes of pixels to move in X direction: 1095 * 4 * 64 (unrolled TGA ops) 1096 * 64 (single TGA op) 1097 * 4 (CPU, using long word) 1098 */ 1099 1100 if (xdir == 1) { /* move to the left */ 1101 1102 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1103 1104 /* 4*64 byte chunks */ 1105 for (xleft = wb, x = xstart; 1106 x <= xend && xleft >= 4*64; 1107 x += XINC256, xleft -= XINC256) { 1108 1109 /* XXX XXX Eight writes to different addresses should fill 1110 * XXX XXX up the write buffers on 21064 and 21164 chips, 1111 * XXX XXX but later CPUs might have larger write buffers which 1112 * XXX XXX require further unrolling of this loop, or the 1113 * XXX XXX insertion of memory barriers. 1114 */ 1115 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1116 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1117 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1118 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1119 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1120 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1121 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1122 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1123 } 1124 1125 /* 64 byte chunks */ 1126 for ( ; x <= xend && xleft >= 64; 1127 x += XINC64, xleft -= XINC64) { 1128 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1129 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1130 } 1131 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1132 1133 } 1134 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1135 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1136 1137 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1138 /* 4 byte granularity */ 1139 for (x = lastx, xleft = lastleft; 1140 x <= xend && xleft >= 4; 1141 x += XINC4, xleft -= XINC4) { 1142 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1143 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1144 } 1145 } 1146 } 1147 else { /* above move to the left, below move to the right */ 1148 1149 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1150 1151 /* 4*64 byte chunks */ 1152 for (xleft = wb, x = xstart; 1153 x >= xend && xleft >= 4*64; 1154 x -= XINC256, xleft -= XINC256) { 1155 1156 /* XXX XXX Eight writes to different addresses should fill 1157 * XXX XXX up the write buffers on 21064 and 21164 chips, 1158 * XXX XXX but later CPUs might have larger write buffers which 1159 * XXX XXX require further unrolling of this loop, or the 1160 * XXX XXX insertion of memory barriers. 1161 */ 1162 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64); 1163 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64); 1164 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64); 1165 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64); 1166 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64); 1167 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64); 1168 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64); 1169 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64); 1170 } 1171 1172 if (xleft) x += XINC256 - XINC64; 1173 1174 /* 64 byte chunks */ 1175 for ( ; x >= xend && xleft >= 64; 1176 x -= XINC64, xleft -= XINC64) { 1177 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1178 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1179 } 1180 if (xleft) x += XINC64 - XINC4; 1181 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1182 } 1183 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1184 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1185 1186 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1187 /* 4 byte granularity */ 1188 for (x = lastx, xleft = lastleft; 1189 x >= xend && xleft >= 4; 1190 x -= XINC4, xleft -= XINC4) { 1191 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1192 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1193 } 1194 } 1195 } 1196 return 0; 1197 } 1198 1199 1200 void tga_putchar (c, row, col, uc, attr) 1201 void *c; 1202 int row, col; 1203 u_int uc; 1204 long attr; 1205 { 1206 struct rasops_info *ri = c; 1207 struct tga_devconfig *dc = ri->ri_hw; 1208 int fs, height, width; 1209 u_char *fr; 1210 int32_t *rp; 1211 1212 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1213 1214 height = ri->ri_font->fontheight; 1215 width = ri->ri_font->fontwidth; 1216 1217 uc -= ri->ri_font->firstchar; 1218 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1219 fs = ri->ri_font->stride; 1220 1221 /* Set foreground and background color. XXX memoize this somehow? 1222 * The rasops code has already expanded the color entry to 32 bits 1223 * for us, even for 8-bit displays, so we don't have to do anything. 1224 */ 1225 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1226 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1227 1228 /* Set raster operation to "copy"... */ 1229 if (ri->ri_depth == 8) 1230 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1231 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1232 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1233 1234 /* Set which pixels we're drawing (of a possible 32). */ 1235 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1236 1237 /* Set drawing mode to opaque stipple. */ 1238 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1239 1240 /* Insert write barrier before actually sending data */ 1241 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1242 TGAREGWB(dc, TGA_REG_GMOR, 1); 1243 1244 while(height--) { 1245 /* The actual stipple write */ 1246 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1247 1248 fr += fs; 1249 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1250 } 1251 1252 /* Do underline */ 1253 if ((attr & 1) != 0) { 1254 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1255 *rp = 0xffffffff; 1256 } 1257 1258 /* Set grapics mode back to normal. */ 1259 TGAWREG(dc, TGA_REG_GMOR, 0); 1260 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1261 1262 } 1263 1264 static void 1265 tga_eraserows(c, row, num, attr) 1266 void *c; 1267 int row, num; 1268 long attr; 1269 { 1270 struct rasops_info *ri = c; 1271 struct tga_devconfig *dc = ri->ri_hw; 1272 int32_t color, lines, pixels; 1273 int32_t *rp; 1274 1275 color = ri->ri_devcmap[(attr >> 16) & 15]; 1276 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1277 lines = num * ri->ri_font->fontheight; 1278 pixels = ri->ri_emuwidth - 1; 1279 1280 /* Set fill color in block-color registers */ 1281 TGAWREG(dc, TGA_REG_GBCR0, color); 1282 TGAWREG(dc, TGA_REG_GBCR1, color); 1283 if (ri->ri_depth != 8) { 1284 TGAWREG(dc, TGA_REG_GBCR2, color); 1285 TGAWREG(dc, TGA_REG_GBCR3, color); 1286 TGAWREG(dc, TGA_REG_GBCR4, color); 1287 TGAWREG(dc, TGA_REG_GBCR5, color); 1288 TGAWREG(dc, TGA_REG_GBCR6, color); 1289 TGAWREG(dc, TGA_REG_GBCR7, color); 1290 } 1291 1292 /* Set raster operation to "copy"... */ 1293 if (ri->ri_depth == 8) 1294 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1295 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1296 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1297 1298 /* Set which pixels we're drawing (of a possible 32). */ 1299 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1300 1301 /* Set drawing mode to block fill. */ 1302 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1303 1304 /* Insert write barrier before actually sending data */ 1305 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1306 TGAREGWB(dc, TGA_REG_GMOR, 1); 1307 1308 while (lines--) { 1309 *rp = pixels; 1310 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1311 } 1312 1313 /* Set grapics mode back to normal. */ 1314 TGAWREG(dc, TGA_REG_GMOR, 0); 1315 1316 } 1317 1318 static void 1319 tga_erasecols (c, row, col, num, attr) 1320 void *c; 1321 int row, col, num; 1322 long attr; 1323 { 1324 struct rasops_info *ri = c; 1325 struct tga_devconfig *dc = ri->ri_hw; 1326 int32_t color, lines, pixels; 1327 int32_t *rp; 1328 1329 color = ri->ri_devcmap[(attr >> 16) & 15]; 1330 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1331 lines = ri->ri_font->fontheight; 1332 pixels = (num * ri->ri_font->fontwidth) - 1; 1333 1334 /* Set fill color in block-color registers */ 1335 TGAWREG(dc, TGA_REG_GBCR0, color); 1336 TGAWREG(dc, TGA_REG_GBCR1, color); 1337 if (ri->ri_depth != 8) { 1338 TGAWREG(dc, TGA_REG_GBCR2, color); 1339 TGAWREG(dc, TGA_REG_GBCR3, color); 1340 TGAWREG(dc, TGA_REG_GBCR4, color); 1341 TGAWREG(dc, TGA_REG_GBCR5, color); 1342 TGAWREG(dc, TGA_REG_GBCR6, color); 1343 TGAWREG(dc, TGA_REG_GBCR7, color); 1344 } 1345 1346 /* Set raster operation to "copy"... */ 1347 if (ri->ri_depth == 8) 1348 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1349 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1350 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1351 1352 /* Set which pixels we're drawing (of a possible 32). */ 1353 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1354 1355 /* Set drawing mode to block fill. */ 1356 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1357 1358 /* Insert write barrier before actually sending data */ 1359 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1360 TGAREGWB(dc, TGA_REG_GMOR, 1); 1361 1362 while (lines--) { 1363 *rp = pixels; 1364 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1365 } 1366 1367 /* Set grapics mode back to normal. */ 1368 TGAWREG(dc, TGA_REG_GMOR, 0); 1369 } 1370 1371 1372 static void 1373 tga_ramdac_wr(v, btreg, val) 1374 void *v; 1375 u_int btreg; 1376 u_int8_t val; 1377 { 1378 struct tga_devconfig *dc = v; 1379 1380 if (btreg > BT485_REG_MAX) 1381 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1382 1383 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1384 TGAREGWB(dc, TGA_REG_EPDR, 1); 1385 } 1386 1387 static void 1388 tga2_ramdac_wr(v, btreg, val) 1389 void *v; 1390 u_int btreg; 1391 u_int8_t val; 1392 { 1393 struct tga_devconfig *dc = v; 1394 bus_space_handle_t ramdac; 1395 1396 if (btreg > BT485_REG_MAX) 1397 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1398 1399 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1400 (0xe << 12) + (btreg << 8), 4, &ramdac); 1401 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1402 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1403 } 1404 1405 static u_int8_t 1406 tga_bt463_rd(v, btreg) 1407 void *v; 1408 u_int btreg; 1409 { 1410 struct tga_devconfig *dc = v; 1411 tga_reg_t rdval; 1412 1413 /* 1414 * Strobe CE# (high->low->high) since status and data are latched on 1415 * the falling and rising edges (repsectively) of this active-low signal. 1416 */ 1417 1418 TGAREGWB(dc, TGA_REG_EPSR, 1); 1419 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1420 TGAREGWB(dc, TGA_REG_EPSR, 1); 1421 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1422 1423 TGAREGRB(dc, TGA_REG_EPSR, 1); 1424 1425 rdval = TGARREG(dc, TGA_REG_EPDR); 1426 TGAREGWB(dc, TGA_REG_EPSR, 1); 1427 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1428 1429 return (rdval >> 16) & 0xff; 1430 } 1431 1432 static void 1433 tga_bt463_wr(v, btreg, val) 1434 void *v; 1435 u_int btreg; 1436 u_int8_t val; 1437 { 1438 struct tga_devconfig *dc = v; 1439 1440 /* 1441 * In spite of the 21030 documentation, to set the MPU bus bits for 1442 * a write, you set them in the upper bits of EPDR, not EPSR. 1443 */ 1444 1445 /* 1446 * Strobe CE# (high->low->high) since status and data are latched on 1447 * the falling and rising edges of this active-low signal. 1448 */ 1449 1450 TGAREGWB(dc, TGA_REG_EPDR, 1); 1451 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1452 TGAREGWB(dc, TGA_REG_EPDR, 1); 1453 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1454 TGAREGWB(dc, TGA_REG_EPDR, 1); 1455 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1456 1457 } 1458 1459 static u_int8_t 1460 tga_ramdac_rd(v, btreg) 1461 void *v; 1462 u_int btreg; 1463 { 1464 struct tga_devconfig *dc = v; 1465 tga_reg_t rdval; 1466 1467 if (btreg > BT485_REG_MAX) 1468 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1469 1470 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1471 TGAREGWB(dc, TGA_REG_EPSR, 1); 1472 1473 rdval = TGARREG(dc, TGA_REG_EPDR); 1474 return (rdval >> 16) & 0xff; /* XXX */ 1475 } 1476 1477 static u_int8_t 1478 tga2_ramdac_rd(v, btreg) 1479 void *v; 1480 u_int btreg; 1481 { 1482 struct tga_devconfig *dc = v; 1483 bus_space_handle_t ramdac; 1484 u_int8_t retval; 1485 1486 if (btreg > BT485_REG_MAX) 1487 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1488 1489 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1490 (0xe << 12) + (btreg << 8), 4, &ramdac); 1491 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1492 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1493 return retval; 1494 } 1495 1496 #include <dev/ic/decmonitors.c> 1497 void tga2_ics9110_wr __P(( 1498 struct tga_devconfig *dc, 1499 int dotclock 1500 )); 1501 1502 void 1503 tga2_init(dc, m) 1504 struct tga_devconfig *dc; 1505 int m; 1506 { 1507 1508 tga2_ics9110_wr(dc, decmonitors[m].dotclock); 1509 #if 0 1510 TGAWREG(dc, TGA_REG_VHCR, 1511 ((decmonitors[m].hbp / 4) << 21) | 1512 ((decmonitors[m].hsync / 4) << 14) | 1513 (((decmonitors[m].hfp - 4) / 4) << 9) | 1514 ((decmonitors[m].cols + 4) / 4)); 1515 #else 1516 TGAWREG(dc, TGA_REG_VHCR, 1517 ((decmonitors[m].hbp / 4) << 21) | 1518 ((decmonitors[m].hsync / 4) << 14) | 1519 (((decmonitors[m].hfp) / 4) << 9) | 1520 ((decmonitors[m].cols) / 4)); 1521 #endif 1522 TGAWREG(dc, TGA_REG_VVCR, 1523 (decmonitors[m].vbp << 22) | 1524 (decmonitors[m].vsync << 16) | 1525 (decmonitors[m].vfp << 11) | 1526 (decmonitors[m].rows)); 1527 TGAWREG(dc, TGA_REG_VVBR, 1); 1528 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1529 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1530 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1531 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1532 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1533 } 1534 1535 void 1536 tga2_ics9110_wr(dc, dotclock) 1537 struct tga_devconfig *dc; 1538 int dotclock; 1539 { 1540 bus_space_handle_t clock; 1541 u_int32_t valU; 1542 int N, M, R, V, X; 1543 int i; 1544 1545 switch (dotclock) { 1546 case 130808000: 1547 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1548 case 119840000: 1549 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1550 case 108180000: 1551 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1552 case 103994000: 1553 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1554 case 175000000: 1555 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1556 case 75000000: 1557 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1558 case 74000000: 1559 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1560 case 69000000: 1561 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1562 case 65000000: 1563 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1564 case 50000000: 1565 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1566 case 40000000: 1567 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1568 case 31500000: 1569 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1570 case 25175000: 1571 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1572 case 135000000: 1573 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1574 case 110000000: 1575 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1576 case 202500000: 1577 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1578 default: 1579 panic("unrecognized clock rate %d\n", dotclock); 1580 } 1581 1582 /* XXX -- hard coded, bad */ 1583 valU = N | ( M << 7 ) | (V << 14); 1584 valU |= (X << 15) | (R << 17); 1585 valU |= 0x17 << 19; 1586 1587 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1588 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1589 1590 for (i=24; i>0; i--) { 1591 u_int32_t writeval; 1592 1593 writeval = valU & 0x1; 1594 if (i == 1) 1595 writeval |= 0x2; 1596 valU >>= 1; 1597 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1598 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1599 } 1600 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1601 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1602 &clock); /* XXX */ 1603 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1604 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1605 } 1606