1 /* $NetBSD: tga.c,v 1.28 2000/06/30 00:01:22 mjacob Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/ioctl.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/tgareg.h> 46 #include <dev/pci/tgavar.h> 47 #include <dev/ic/bt485reg.h> 48 #include <dev/ic/bt485var.h> 49 #include <dev/ic/bt463reg.h> 50 #include <dev/ic/bt463var.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wscons_raster.h> 54 #include <dev/rasops/rasops.h> 55 #include <dev/wsfont/wsfont.h> 56 #include <uvm/uvm_extern.h> 57 58 #ifdef __alpha__ 59 #include <machine/pte.h> 60 #endif 61 #ifdef __mips__ 62 #include <mips/pte.h> 63 #endif 64 65 int tgamatch __P((struct device *, struct cfdata *, void *)); 66 void tgaattach __P((struct device *, struct device *, void *)); 67 int tgaprint __P((void *, const char *)); 68 69 struct cfattach tga_ca = { 70 sizeof(struct tga_softc), tgamatch, tgaattach, 71 }; 72 73 int tga_identify __P((struct tga_devconfig *)); 74 const struct tga_conf *tga_getconf __P((int)); 75 static void tga_getdevconfig __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 76 pcitag_t tag, struct tga_devconfig *dc)); 77 78 struct tga_devconfig tga_console_dc; 79 80 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 81 paddr_t tga_mmap __P((void *, off_t, int)); 82 static void tga_copyrows __P((void *, int, int, int)); 83 static void tga_copycols __P((void *, int, int, int, int)); 84 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 85 void **, int *, int *, long *)); 86 static void tga_free_screen __P((void *, void *)); 87 static int tga_show_screen __P((void *, void *, int, 88 void (*) (void *, int, int), void *)); 89 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 90 struct rasops_info *, int, int)); 91 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 92 int, struct rasops_info *, int, int )); 93 static void tga_putchar __P((void *c, int row, int col, 94 u_int uc, long attr)); 95 static void tga_eraserows __P((void *, int, int, long)); 96 static void tga_erasecols __P((void *, int, int, int, long)); 97 void tga2_init __P((struct tga_devconfig *, int)); 98 99 static void tga_config_interrupts __P((struct device *)); 100 101 /* RAMDAC interface functions */ 102 static int tga_sched_update __P((void *, void (*)(void *))); 103 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 104 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 105 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 106 static u_int8_t tga_bt463_rd __P((void *, u_int)); 107 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 108 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 109 110 /* Interrupt handler */ 111 static int tga_intr __P((void *)); 112 113 /* The NULL entries will get filled in by rasops_init(). 114 * XXX and the non-NULL ones will be overwritten; reset after calling it. 115 */ 116 struct wsdisplay_emulops tga_emulops = { 117 NULL, 118 NULL, 119 tga_putchar, 120 tga_copycols, 121 tga_erasecols, 122 tga_copyrows, 123 tga_eraserows, 124 NULL, 125 }; 126 127 struct wsscreen_descr tga_stdscreen = { 128 "std", 129 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 130 &tga_emulops, 131 0, 0, 132 WSSCREEN_REVERSE 133 }; 134 135 const struct wsscreen_descr *_tga_scrlist[] = { 136 &tga_stdscreen, 137 /* XXX other formats, graphics screen? */ 138 }; 139 140 struct wsscreen_list tga_screenlist = { 141 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 142 }; 143 144 struct wsdisplay_accessops tga_accessops = { 145 tga_ioctl, 146 tga_mmap, 147 tga_alloc_screen, 148 tga_free_screen, 149 tga_show_screen, 150 0 /* load_font */ 151 }; 152 153 static void tga_blank __P((struct tga_devconfig *)); 154 static void tga_unblank __P((struct tga_devconfig *)); 155 156 int 157 tgamatch(parent, match, aux) 158 struct device *parent; 159 struct cfdata *match; 160 void *aux; 161 { 162 struct pci_attach_args *pa = aux; 163 164 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 165 return (0); 166 167 switch (PCI_PRODUCT(pa->pa_id)) { 168 case PCI_PRODUCT_DEC_21030: 169 case PCI_PRODUCT_DEC_PBXGB: 170 return 10; 171 default: 172 return 0; 173 } 174 return (0); 175 } 176 177 static void 178 tga_getdevconfig(memt, pc, tag, dc) 179 bus_space_tag_t memt; 180 pci_chipset_tag_t pc; 181 pcitag_t tag; 182 struct tga_devconfig *dc; 183 { 184 const struct tga_conf *tgac; 185 struct rasops_info *rip; 186 int cookie; 187 bus_size_t pcisize; 188 int i, flags; 189 190 dc->dc_memt = memt; 191 192 dc->dc_pcitag = tag; 193 194 /* XXX magic number */ 195 if (pci_mapreg_info(pc, tag, 0x10, 196 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 197 &dc->dc_pcipaddr, &pcisize, &flags)) 198 return; 199 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 200 panic("tga memory not prefetchable"); 201 202 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 203 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 204 return; 205 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 206 #ifdef __alpha__ 207 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 208 #endif 209 #ifdef arc 210 bus_space_paddr(memt, dc->dc_memh, &dc->dc_paddr); 211 #endif 212 213 bus_space_subregion(dc->dc_memt, dc->dc_memh, 214 TGA_MEM_CREGS, TGA_CREGS_SIZE, 215 &dc->dc_regs); 216 dc->dc_tga_type = tga_identify(dc); 217 218 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 219 if (tgac == NULL) 220 return; 221 222 #if 0 223 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 224 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 225 panic("tga_getdevconfig: memory size mismatch?"); 226 #endif 227 228 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 229 case 0x01: 230 case 0x02: 231 case 0x03: 232 case 0x04: 233 dc->dc_tga2 = 0; 234 break; 235 case 0x20: 236 case 0x21: 237 case 0x22: 238 dc->dc_tga2 = 1; 239 break; 240 default: 241 panic("tga_getdevconfig: TGA Revision not recognized"); 242 } 243 244 if (dc->dc_tga2) { 245 int monitor; 246 247 monitor = (~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f; 248 tga2_init(dc, monitor); 249 } 250 251 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 252 case 0: 253 dc->dc_wid = 8192; 254 break; 255 256 case 1: 257 dc->dc_wid = 8196; 258 break; 259 260 default: 261 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 262 break; 263 } 264 265 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 266 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 267 268 /* XXX this seems to be what DEC does */ 269 TGAWREG(dc, TGA_REG_CCBR, 0); 270 TGAWREG(dc, TGA_REG_VVBR, 1); 271 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 272 1 * tgac->tgac_vvbr_units; 273 dc->dc_blanked = 1; 274 tga_unblank(dc); 275 276 /* 277 * Set all bits in the pixel mask, to enable writes to all pixels. 278 * It seems that the console firmware clears some of them 279 * under some circumstances, which causes cute vertical stripes. 280 */ 281 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 282 283 /* clear the screen */ 284 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 285 *(u_int32_t *)(dc->dc_videobase + i) = 0; 286 287 /* Initialize rasops descriptor */ 288 rip = &dc->dc_rinfo; 289 rip->ri_flg = RI_CENTER; 290 rip->ri_depth = tgac->tgac_phys_depth; 291 rip->ri_bits = (void *)dc->dc_videobase; 292 rip->ri_width = dc->dc_wid; 293 rip->ri_height = dc->dc_ht; 294 rip->ri_stride = dc->dc_rowbytes; 295 rip->ri_hw = dc; 296 297 if (tgac->tgac_phys_depth == 32) { 298 rip->ri_rnum = 8; 299 rip->ri_gnum = 8; 300 rip->ri_bnum = 8; 301 rip->ri_rpos = 16; 302 rip->ri_gpos = 8; 303 rip->ri_bpos = 0; 304 } 305 306 wsfont_init(); 307 /* prefer 8 pixel wide font */ 308 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0) 309 cookie = wsfont_find(NULL, 0, 0, 0); 310 if (cookie <= 0) { 311 printf("tga: no appropriate fonts.\n"); 312 return; 313 } 314 315 /* the accelerated tga_putchar() needs LSbit left */ 316 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font, 317 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 318 printf("tga: couldn't lock font\n"); 319 return; 320 } 321 dc->dc_rinfo.ri_wsfcookie = cookie; 322 323 rasops_init(rip, 34, 80); 324 325 /* add our accelerated functions */ 326 /* XXX shouldn't have to do this; rasops should leave non-NULL 327 * XXX entries alone. 328 */ 329 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 330 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 331 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 332 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 333 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 334 335 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 336 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 337 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 338 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 339 340 341 dc->dc_intrenabled = 0; 342 } 343 344 void 345 tgaattach(parent, self, aux) 346 struct device *parent, *self; 347 void *aux; 348 { 349 struct pci_attach_args *pa = aux; 350 struct tga_softc *sc = (struct tga_softc *)self; 351 struct wsemuldisplaydev_attach_args aa; 352 pci_intr_handle_t intrh; 353 const char *intrstr; 354 u_int8_t rev; 355 int console; 356 357 #if defined(__alpha__) || defined(arc) 358 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 359 #else 360 console = 0; 361 #endif 362 if (console) { 363 sc->sc_dc = &tga_console_dc; 364 sc->nscreens = 1; 365 } else { 366 sc->sc_dc = (struct tga_devconfig *) 367 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK); 368 bzero(sc->sc_dc, sizeof(struct tga_devconfig)); 369 tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, 370 sc->sc_dc); 371 } 372 if (sc->sc_dc->dc_vaddr == NULL) { 373 printf(": couldn't map memory space; punt!\n"); 374 return; 375 } 376 377 /* XXX say what's going on. */ 378 intrstr = NULL; 379 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 380 pa->pa_intrline, &intrh)) { 381 printf(": couldn't map interrupt"); 382 return; 383 } 384 intrstr = pci_intr_string(pa->pa_pc, intrh); 385 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 386 sc->sc_dc); 387 if (sc->sc_intr == NULL) { 388 printf(": couldn't establish interrupt"); 389 if (intrstr != NULL) 390 printf("at %s", intrstr); 391 printf("\n"); 392 return; 393 } 394 395 rev = PCI_REVISION(pa->pa_class); 396 switch (rev) { 397 case 0x1: 398 case 0x2: 399 case 0x3: 400 printf(": DC21030 step %c", 'A' + rev - 1); 401 break; 402 case 0x20: 403 printf(": TGA2 abstract software model"); 404 break; 405 case 0x21: 406 case 0x22: 407 printf(": TGA2 pass %d", rev - 0x20); 408 break; 409 410 default: 411 printf("unknown stepping (0x%x)", rev); 412 break; 413 } 414 printf(", "); 415 416 /* 417 * Get RAMDAC function vectors and call the RAMDAC functions 418 * to allocate its private storage and pass that back to us. 419 */ 420 421 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 422 if (!sc->sc_dc->dc_tga2) { 423 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 424 sc->sc_dc->dc_ramdac_cookie = 425 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 426 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 427 else 428 sc->sc_dc->dc_ramdac_cookie = 429 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 430 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 431 } else { 432 sc->sc_dc->dc_ramdac_cookie = 433 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 434 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 435 } 436 437 /* 438 * Initialize the RAMDAC. Initialization includes disabling 439 * cursor, setting a sane colormap, etc. 440 */ 441 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 442 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 443 444 if (sc->sc_dc->dc_tgaconf == NULL) { 445 printf("unknown board configuration\n"); 446 return; 447 } 448 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 449 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 450 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 451 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 452 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 453 454 if (intrstr != NULL) 455 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 456 intrstr); 457 458 aa.console = console; 459 aa.scrdata = &tga_screenlist; 460 aa.accessops = &tga_accessops; 461 aa.accesscookie = sc; 462 463 config_found(self, &aa, wsemuldisplaydevprint); 464 465 config_interrupts(self, tga_config_interrupts); 466 } 467 468 static void 469 tga_config_interrupts (d) 470 struct device *d; 471 { 472 struct tga_softc *sc = (struct tga_softc *)d; 473 sc->sc_dc->dc_intrenabled = 1; 474 } 475 476 477 int 478 tga_ioctl(v, cmd, data, flag, p) 479 void *v; 480 u_long cmd; 481 caddr_t data; 482 int flag; 483 struct proc *p; 484 { 485 struct tga_softc *sc = v; 486 struct tga_devconfig *dc = sc->sc_dc; 487 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 488 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 489 490 switch (cmd) { 491 case WSDISPLAYIO_GTYPE: 492 *(u_int *)data = WSDISPLAY_TYPE_TGA; 493 return (0); 494 495 case WSDISPLAYIO_GINFO: 496 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 497 wsd_fbip->height = sc->sc_dc->dc_ht; 498 wsd_fbip->width = sc->sc_dc->dc_wid; 499 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 500 wsd_fbip->cmsize = 256; /* XXX ??? */ 501 #undef wsd_fbip 502 return (0); 503 504 case WSDISPLAYIO_GETCMAP: 505 return (*dcrf->ramdac_get_cmap)(dcrc, 506 (struct wsdisplay_cmap *)data); 507 508 case WSDISPLAYIO_PUTCMAP: 509 return (*dcrf->ramdac_set_cmap)(dcrc, 510 (struct wsdisplay_cmap *)data); 511 512 case WSDISPLAYIO_SVIDEO: 513 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 514 tga_blank(sc->sc_dc); 515 else 516 tga_unblank(sc->sc_dc); 517 return (0); 518 519 case WSDISPLAYIO_GVIDEO: 520 *(u_int *)data = dc->dc_blanked ? 521 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 522 return (0); 523 524 case WSDISPLAYIO_GCURPOS: 525 return (*dcrf->ramdac_get_curpos)(dcrc, 526 (struct wsdisplay_curpos *)data); 527 528 case WSDISPLAYIO_SCURPOS: 529 return (*dcrf->ramdac_set_curpos)(dcrc, 530 (struct wsdisplay_curpos *)data); 531 532 case WSDISPLAYIO_GCURMAX: 533 return (*dcrf->ramdac_get_curmax)(dcrc, 534 (struct wsdisplay_curpos *)data); 535 536 case WSDISPLAYIO_GCURSOR: 537 return (*dcrf->ramdac_get_cursor)(dcrc, 538 (struct wsdisplay_cursor *)data); 539 540 case WSDISPLAYIO_SCURSOR: 541 return (*dcrf->ramdac_set_cursor)(dcrc, 542 (struct wsdisplay_cursor *)data); 543 } 544 return (-1); 545 } 546 547 static int 548 tga_sched_update(v, f) 549 void *v; 550 void (*f) __P((void *)); 551 { 552 struct tga_devconfig *dc = v; 553 554 if (dc->dc_intrenabled) { 555 /* Arrange for f to be called at the next end-of-frame interrupt */ 556 dc->dc_ramdac_intr = f; 557 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 558 } else { 559 /* Spin until the end-of-frame, then call f */ 560 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 561 TGAREGWB(dc, TGA_REG_SISR, 1); 562 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 563 ; 564 f(dc->dc_ramdac_cookie); 565 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 566 TGAREGWB(dc, TGA_REG_SISR, 1); 567 } 568 569 return 0; 570 } 571 572 static int 573 tga_intr(v) 574 void *v; 575 { 576 struct tga_devconfig *dc = v; 577 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 578 579 u_int32_t reg; 580 581 reg = TGARREG(dc, TGA_REG_SISR); 582 if (( reg & 0x00010001) != 0x00010001) { 583 /* Odd. We never set any of the other interrupt enables. */ 584 if ((reg & 0x1f) != 0) { 585 /* Clear the mysterious pending interrupts. */ 586 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 587 TGAREGWB(dc, TGA_REG_SISR, 1); 588 /* This was our interrupt, even if we're puzzled as to why 589 * we got it. Don't make the interrupt handler think it 590 * was a stray. 591 */ 592 return -1; 593 } else { 594 return 0; 595 } 596 } 597 dc->dc_ramdac_intr(dcrc); 598 dc->dc_ramdac_intr = NULL; 599 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 600 TGAREGWB(dc, TGA_REG_SISR, 1); 601 return (1); 602 } 603 604 paddr_t 605 tga_mmap(v, offset, prot) 606 void *v; 607 off_t offset; 608 int prot; 609 { 610 611 /* XXX NEW MAPPING CODE... */ 612 613 #if defined(__alpha__) 614 struct tga_softc *sc = v; 615 616 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 617 return -1; 618 return alpha_btop(sc->sc_dc->dc_paddr + offset); 619 #elif defined(__mips__) 620 struct tga_softc *sc = v; 621 622 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 623 return -1; 624 return mips_btop(sc->sc_dc->dc_paddr + offset); 625 #else 626 return (-1); 627 #endif 628 } 629 630 static int 631 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 632 void *v; 633 const struct wsscreen_descr *type; 634 void **cookiep; 635 int *curxp, *curyp; 636 long *attrp; 637 { 638 struct tga_softc *sc = v; 639 long defattr; 640 641 if (sc->nscreens > 0) 642 return (ENOMEM); 643 644 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 645 *curxp = 0; 646 *curyp = 0; 647 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 648 0, 0, 0, &defattr); 649 *attrp = defattr; 650 sc->nscreens++; 651 return (0); 652 } 653 654 static void 655 tga_free_screen(v, cookie) 656 void *v; 657 void *cookie; 658 { 659 struct tga_softc *sc = v; 660 661 if (sc->sc_dc == &tga_console_dc) 662 panic("tga_free_screen: console"); 663 664 sc->nscreens--; 665 } 666 667 static int 668 tga_show_screen(v, cookie, waitok, cb, cbarg) 669 void *v; 670 void *cookie; 671 int waitok; 672 void (*cb) __P((void *, int, int)); 673 void *cbarg; 674 { 675 676 return (0); 677 } 678 679 int 680 tga_cnattach(iot, memt, pc, bus, device, function) 681 bus_space_tag_t iot, memt; 682 pci_chipset_tag_t pc; 683 int bus, device, function; 684 { 685 struct tga_devconfig *dcp = &tga_console_dc; 686 long defattr; 687 688 tga_getdevconfig(memt, pc, 689 pci_make_tag(pc, bus, device, function), dcp); 690 691 /* sanity checks */ 692 if (dcp->dc_vaddr == NULL) 693 panic("tga_console(%d, %d): couldn't map memory space", 694 device, function); 695 if (dcp->dc_tgaconf == NULL) 696 panic("tga_console(%d, %d): unknown board configuration", 697 device, function); 698 699 /* 700 * Initialize the RAMDAC but DO NOT allocate any private storage. 701 * Initialization includes disabling cursor, setting a sane 702 * colormap, etc. It will be reinitialized in tgaattach(). 703 */ 704 if (dcp->dc_tga2) 705 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 706 tga2_ramdac_rd); 707 else { 708 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 709 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 710 tga_ramdac_rd); 711 else { 712 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 713 tga_bt463_rd); 714 } 715 } 716 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 717 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 718 719 return(0); 720 } 721 722 /* 723 * Functions to blank and unblank the display. 724 */ 725 static void 726 tga_blank(dc) 727 struct tga_devconfig *dc; 728 { 729 730 if (!dc->dc_blanked) { 731 dc->dc_blanked = 1; 732 /* XXX */ 733 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 734 } 735 } 736 737 static void 738 tga_unblank(dc) 739 struct tga_devconfig *dc; 740 { 741 742 if (dc->dc_blanked) { 743 dc->dc_blanked = 0; 744 /* XXX */ 745 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 746 } 747 } 748 749 /* 750 * Functions to manipulate the built-in cursor handing hardware. 751 */ 752 int 753 tga_builtin_set_cursor(dc, cursorp) 754 struct tga_devconfig *dc; 755 struct wsdisplay_cursor *cursorp; 756 { 757 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 758 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 759 int count, error, v; 760 761 v = cursorp->which; 762 if (v & WSDISPLAY_CURSOR_DOCMAP) { 763 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 764 if (error) 765 return (error); 766 } 767 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 768 if ((u_int)cursorp->size.x != 64 || 769 (u_int)cursorp->size.y > 64) 770 return (EINVAL); 771 /* The cursor is 2 bits deep, and there is no mask */ 772 count = (cursorp->size.y * 64 * 2) / NBBY; 773 if (!uvm_useracc(cursorp->image, count, B_READ)) 774 return (EFAULT); 775 } 776 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 777 return EINVAL; 778 779 /* parameters are OK; do it */ 780 if (v & WSDISPLAY_CURSOR_DOCUR) { 781 if (cursorp->enable) 782 /* XXX */ 783 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 784 else 785 /* XXX */ 786 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 787 } 788 if (v & WSDISPLAY_CURSOR_DOPOS) { 789 TGAWREG(dc, TGA_REG_CXYR, 790 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 791 } 792 if (v & WSDISPLAY_CURSOR_DOCMAP) { 793 /* can't fail. */ 794 dcrf->ramdac_set_curcmap(dcrc, cursorp); 795 } 796 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 797 count = ((64 * 2) / NBBY) * cursorp->size.y; 798 TGAWREG(dc, TGA_REG_CCBR, 799 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 800 copyin(cursorp->image, (char *)(dc->dc_vaddr + 801 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 802 count); /* can't fail. */ 803 } 804 return (0); 805 } 806 807 int 808 tga_builtin_get_cursor(dc, cursorp) 809 struct tga_devconfig *dc; 810 struct wsdisplay_cursor *cursorp; 811 { 812 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 813 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 814 int count, error; 815 816 cursorp->which = WSDISPLAY_CURSOR_DOALL & 817 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 818 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 819 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 820 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 821 cursorp->size.x = 64; 822 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 823 824 if (cursorp->image != NULL) { 825 count = (cursorp->size.y * 64 * 2) / NBBY; 826 error = copyout((char *)(dc->dc_vaddr + 827 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 828 cursorp->image, count); 829 if (error) 830 return (error); 831 /* No mask */ 832 } 833 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 834 return (error); 835 } 836 837 int 838 tga_builtin_set_curpos(dc, curposp) 839 struct tga_devconfig *dc; 840 struct wsdisplay_curpos *curposp; 841 { 842 843 TGAWREG(dc, TGA_REG_CXYR, 844 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 845 return (0); 846 } 847 848 int 849 tga_builtin_get_curpos(dc, curposp) 850 struct tga_devconfig *dc; 851 struct wsdisplay_curpos *curposp; 852 { 853 854 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 855 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 856 return (0); 857 } 858 859 int 860 tga_builtin_get_curmax(dc, curposp) 861 struct tga_devconfig *dc; 862 struct wsdisplay_curpos *curposp; 863 { 864 865 curposp->x = curposp->y = 64; 866 return (0); 867 } 868 869 /* 870 * Copy columns (characters) in a row (line). 871 */ 872 static void 873 tga_copycols(id, row, srccol, dstcol, ncols) 874 void *id; 875 int row, srccol, dstcol, ncols; 876 { 877 struct rasops_info *ri = id; 878 int y, srcx, dstx, nx; 879 880 y = ri->ri_font->fontheight * row; 881 srcx = ri->ri_font->fontwidth * srccol; 882 dstx = ri->ri_font->fontwidth * dstcol; 883 nx = ri->ri_font->fontwidth * ncols; 884 885 tga_rop(ri, dstx, y, 886 nx, ri->ri_font->fontheight, RAS_SRC, 887 ri, srcx, y); 888 } 889 890 /* 891 * Copy rows (lines). 892 */ 893 static void 894 tga_copyrows(id, srcrow, dstrow, nrows) 895 void *id; 896 int srcrow, dstrow, nrows; 897 { 898 struct rasops_info *ri = id; 899 int srcy, dsty, ny; 900 901 srcy = ri->ri_font->fontheight * srcrow; 902 dsty = ri->ri_font->fontheight * dstrow; 903 ny = ri->ri_font->fontheight * nrows; 904 905 tga_rop(ri, 0, dsty, 906 ri->ri_emuwidth, ny, RAS_SRC, 907 ri, 0, srcy); 908 } 909 910 /* Do we need the src? */ 911 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 912 913 /* A mapping between our API and the TGA card */ 914 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 915 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 916 }; 917 918 /* 919 * Generic TGA raster op. 920 * This covers all possible raster ops, and 921 * clips the sizes and all of that. 922 */ 923 static int 924 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 925 struct rasops_info *dst; 926 int dx, dy, w, h, rop; 927 struct rasops_info *src; 928 int sx, sy; 929 { 930 if (!dst) 931 return -1; 932 if (needsrc[RAS_GETOP(rop)]) { 933 if (src == NULL) 934 return -1; /* We want a src */ 935 /* Clip against src */ 936 if (sx < 0) { 937 w += sx; 938 sx = 0; 939 } 940 if (sy < 0) { 941 h += sy; 942 sy = 0; 943 } 944 if (sx + w > src->ri_emuwidth) 945 w = src->ri_emuwidth - sx; 946 if (sy + h > src->ri_emuheight) 947 h = src->ri_emuheight - sy; 948 } else { 949 if (src != NULL) 950 return -1; /* We need no src */ 951 } 952 /* Clip against dst. We modify src regardless of using it, 953 * since it really doesn't matter. 954 */ 955 if (dx < 0) { 956 w += dx; 957 sx -= dx; 958 dx = 0; 959 } 960 if (dy < 0) { 961 h += dy; 962 sy -= dy; 963 dy = 0; 964 } 965 if (dx + w > dst->ri_emuwidth) 966 w = dst->ri_emuwidth - dx; 967 if (dy + h > dst->ri_emuheight) 968 h = dst->ri_emuheight - dy; 969 if (w <= 0 || h <= 0) 970 return 0; /* Vacuously true; */ 971 if (!src) { 972 /* XXX Punt! */ 973 return -1; 974 } 975 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 976 } 977 978 979 980 /* 981 * Video to Video raster ops. 982 * This function deals with all raster ops that have a src and dst 983 * that are on the card. 984 */ 985 static int 986 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 987 struct rasops_info *dst; 988 int dx, dy, w, h, rop; 989 struct rasops_info *src; 990 int sx, sy; 991 { 992 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 993 int srcb, dstb; 994 int x, y; 995 int xstart, xend, xdir, xinc; 996 int ystart, yend, ydir, yinc; 997 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 998 999 /* 1000 * I don't yet want to deal with unaligned guys, really. And we don't 1001 * deal with copies from one card to another. 1002 */ 1003 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1004 /* XXX Punt! */ 1005 /* XXX should never happen, since it's only being used to 1006 * XXX copy 8-pixel-wide characters. 1007 */ 1008 return -1; 1009 } 1010 1011 if (sy >= dy) { 1012 ystart = 0; 1013 yend = h; 1014 ydir = 1; 1015 } else { 1016 ystart = h; 1017 yend = 0; 1018 ydir = -1; 1019 } 1020 if (sx >= dx) { 1021 xstart = 0; 1022 xend = w * (dst->ri_depth / 8); 1023 xdir = 1; 1024 } else { 1025 xstart = w * (dst->ri_depth / 8); 1026 xend = 0; 1027 xdir = -1; 1028 } 1029 xinc = xdir * 4 * 64; 1030 yinc = ydir * dst->ri_stride; 1031 ystart *= dst->ri_stride; 1032 yend *= dst->ri_stride; 1033 srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1034 (sx + src->ri_xorigin) * (src->ri_depth/8); 1035 dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1036 (dx + dst->ri_xorigin ) * (dst->ri_depth/8); 1037 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1038 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1039 for (y = ystart; (ydir * y) < (ydir * yend); y += yinc) { 1040 for (x = xstart; (xdir * x) < (xdir * xend); x += xinc) { 1041 /* XXX XXX Eight writes to different addresses should fill 1042 * XXX XXX up the write buffers on 21064 and 21164 chips, 1043 * XXX XXX but later CPUs might have larger write buffers which 1044 * XXX XXX require further unrolling of this loop, or the 1045 * XXX XXX insertion of memory barriers. 1046 */ 1047 TGAWALREG(dc, TGA_REG_GCSR, 0, srcb + y + x + 3 * 64); 1048 TGAWALREG(dc, TGA_REG_GCDR, 0, dstb + y + x + 3 * 64); 1049 TGAWALREG(dc, TGA_REG_GCSR, 1, srcb + y + x + 2 * 64); 1050 TGAWALREG(dc, TGA_REG_GCDR, 1, dstb + y + x + 2 * 64); 1051 TGAWALREG(dc, TGA_REG_GCSR, 2, srcb + y + x + 1 * 64); 1052 TGAWALREG(dc, TGA_REG_GCDR, 2, dstb + y + x + 1 * 64); 1053 TGAWALREG(dc, TGA_REG_GCSR, 3, srcb + y + x + 0 * 64); 1054 TGAWALREG(dc, TGA_REG_GCDR, 3, dstb + y + x + 0 * 64); 1055 } 1056 } 1057 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1058 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1059 return 0; 1060 } 1061 1062 1063 void tga_putchar (c, row, col, uc, attr) 1064 void *c; 1065 int row, col; 1066 u_int uc; 1067 long attr; 1068 { 1069 struct rasops_info *ri = c; 1070 struct tga_devconfig *dc = ri->ri_hw; 1071 int fs, height, width; 1072 u_char *fr; 1073 int32_t *rp; 1074 1075 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1076 1077 height = ri->ri_font->fontheight; 1078 width = ri->ri_font->fontwidth; 1079 1080 uc -= ri->ri_font->firstchar; 1081 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1082 fs = ri->ri_font->stride; 1083 1084 /* Set foreground and background color. XXX memoize this somehow? 1085 * The rasops code has already expanded the color entry to 32 bits 1086 * for us, even for 8-bit displays, so we don't have to do anything. 1087 */ 1088 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1089 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1090 1091 /* Set raster operation to "copy"... */ 1092 if (ri->ri_depth == 8) 1093 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1094 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1095 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1096 1097 /* Set which pixels we're drawing (of a possible 32). */ 1098 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1099 1100 /* Set drawing mode to opaque stipple. */ 1101 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1102 1103 /* Insert write barrier before actually sending data */ 1104 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1105 TGAREGWB(dc, TGA_REG_GMOR, 1); 1106 1107 while(height--) { 1108 /* The actual stipple write */ 1109 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1110 1111 fr += fs; 1112 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1113 } 1114 1115 /* Do underline */ 1116 if ((attr & 1) != 0) { 1117 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1118 *rp = 0xffffffff; 1119 } 1120 1121 /* Set grapics mode back to normal. */ 1122 TGAWREG(dc, TGA_REG_GMOR, 0); 1123 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1124 1125 } 1126 1127 static void 1128 tga_eraserows(c, row, num, attr) 1129 void *c; 1130 int row, num; 1131 long attr; 1132 { 1133 struct rasops_info *ri = c; 1134 struct tga_devconfig *dc = ri->ri_hw; 1135 int32_t color, lines, pixels; 1136 int32_t *rp; 1137 1138 color = ri->ri_devcmap[(attr >> 16) & 15]; 1139 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1140 lines = num * ri->ri_font->fontheight; 1141 pixels = ri->ri_emuwidth - 1; 1142 1143 /* Set fill color in block-color registers */ 1144 TGAWREG(dc, TGA_REG_GBCR0, color); 1145 TGAWREG(dc, TGA_REG_GBCR1, color); 1146 if (ri->ri_depth != 8) { 1147 TGAWREG(dc, TGA_REG_GBCR2, color); 1148 TGAWREG(dc, TGA_REG_GBCR3, color); 1149 TGAWREG(dc, TGA_REG_GBCR4, color); 1150 TGAWREG(dc, TGA_REG_GBCR5, color); 1151 TGAWREG(dc, TGA_REG_GBCR6, color); 1152 TGAWREG(dc, TGA_REG_GBCR7, color); 1153 } 1154 1155 /* Set raster operation to "copy"... */ 1156 if (ri->ri_depth == 8) 1157 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1158 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1159 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1160 1161 /* Set which pixels we're drawing (of a possible 32). */ 1162 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1163 1164 /* Set drawing mode to block fill. */ 1165 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1166 1167 /* Insert write barrier before actually sending data */ 1168 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1169 TGAREGWB(dc, TGA_REG_GMOR, 1); 1170 1171 while (lines--) { 1172 *rp = pixels; 1173 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1174 } 1175 1176 /* Set grapics mode back to normal. */ 1177 TGAWREG(dc, TGA_REG_GMOR, 0); 1178 1179 } 1180 1181 static void 1182 tga_erasecols (c, row, col, num, attr) 1183 void *c; 1184 int row, col, num; 1185 long attr; 1186 { 1187 struct rasops_info *ri = c; 1188 struct tga_devconfig *dc = ri->ri_hw; 1189 int32_t color, lines, pixels; 1190 int32_t *rp; 1191 1192 color = ri->ri_devcmap[(attr >> 16) & 15]; 1193 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1194 lines = ri->ri_font->fontheight; 1195 pixels = (num * ri->ri_font->fontwidth) - 1; 1196 1197 /* Set fill color in block-color registers */ 1198 TGAWREG(dc, TGA_REG_GBCR0, color); 1199 TGAWREG(dc, TGA_REG_GBCR1, color); 1200 if (ri->ri_depth != 8) { 1201 TGAWREG(dc, TGA_REG_GBCR2, color); 1202 TGAWREG(dc, TGA_REG_GBCR3, color); 1203 TGAWREG(dc, TGA_REG_GBCR4, color); 1204 TGAWREG(dc, TGA_REG_GBCR5, color); 1205 TGAWREG(dc, TGA_REG_GBCR6, color); 1206 TGAWREG(dc, TGA_REG_GBCR7, color); 1207 } 1208 1209 /* Set raster operation to "copy"... */ 1210 if (ri->ri_depth == 8) 1211 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1212 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1213 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1214 1215 /* Set which pixels we're drawing (of a possible 32). */ 1216 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1217 1218 /* Set drawing mode to block fill. */ 1219 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1220 1221 /* Insert write barrier before actually sending data */ 1222 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1223 TGAREGWB(dc, TGA_REG_GMOR, 1); 1224 1225 while (lines--) { 1226 *rp = pixels; 1227 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1228 } 1229 1230 /* Set grapics mode back to normal. */ 1231 TGAWREG(dc, TGA_REG_GMOR, 0); 1232 } 1233 1234 1235 static void 1236 tga_ramdac_wr(v, btreg, val) 1237 void *v; 1238 u_int btreg; 1239 u_int8_t val; 1240 { 1241 struct tga_devconfig *dc = v; 1242 1243 if (btreg > BT485_REG_MAX) 1244 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1245 1246 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1247 TGAREGWB(dc, TGA_REG_EPDR, 1); 1248 } 1249 1250 static void 1251 tga2_ramdac_wr(v, btreg, val) 1252 void *v; 1253 u_int btreg; 1254 u_int8_t val; 1255 { 1256 struct tga_devconfig *dc = v; 1257 bus_space_handle_t ramdac; 1258 1259 if (btreg > BT485_REG_MAX) 1260 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1261 1262 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1263 (0xe << 12) + (btreg << 8), 4, &ramdac); 1264 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1265 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1266 } 1267 1268 static u_int8_t 1269 tga_bt463_rd(v, btreg) 1270 void *v; 1271 u_int btreg; 1272 { 1273 struct tga_devconfig *dc = v; 1274 tga_reg_t rdval; 1275 1276 /* 1277 * Strobe CE# (high->low->high) since status and data are latched on 1278 * the falling and rising edges (repsectively) of this active-low signal. 1279 */ 1280 1281 TGAREGWB(dc, TGA_REG_EPSR, 1); 1282 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1283 TGAREGWB(dc, TGA_REG_EPSR, 1); 1284 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1285 1286 TGAREGRB(dc, TGA_REG_EPSR, 1); 1287 1288 rdval = TGARREG(dc, TGA_REG_EPDR); 1289 TGAREGWB(dc, TGA_REG_EPSR, 1); 1290 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1291 1292 return (rdval >> 16) & 0xff; 1293 } 1294 1295 static void 1296 tga_bt463_wr(v, btreg, val) 1297 void *v; 1298 u_int btreg; 1299 u_int8_t val; 1300 { 1301 struct tga_devconfig *dc = v; 1302 1303 /* 1304 * In spite of the 21030 documentation, to set the MPU bus bits for 1305 * a write, you set them in the upper bits of EPDR, not EPSR. 1306 */ 1307 1308 /* 1309 * Strobe CE# (high->low->high) since status and data are latched on 1310 * the falling and rising edges of this active-low signal. 1311 */ 1312 1313 TGAREGWB(dc, TGA_REG_EPDR, 1); 1314 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1315 TGAREGWB(dc, TGA_REG_EPDR, 1); 1316 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1317 TGAREGWB(dc, TGA_REG_EPDR, 1); 1318 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1319 1320 } 1321 1322 static u_int8_t 1323 tga_ramdac_rd(v, btreg) 1324 void *v; 1325 u_int btreg; 1326 { 1327 struct tga_devconfig *dc = v; 1328 tga_reg_t rdval; 1329 1330 if (btreg > BT485_REG_MAX) 1331 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1332 1333 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1334 TGAREGWB(dc, TGA_REG_EPSR, 1); 1335 1336 rdval = TGARREG(dc, TGA_REG_EPDR); 1337 return (rdval >> 16) & 0xff; /* XXX */ 1338 } 1339 1340 static u_int8_t 1341 tga2_ramdac_rd(v, btreg) 1342 void *v; 1343 u_int btreg; 1344 { 1345 struct tga_devconfig *dc = v; 1346 bus_space_handle_t ramdac; 1347 u_int8_t retval; 1348 1349 if (btreg > BT485_REG_MAX) 1350 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1351 1352 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1353 (0xe << 12) + (btreg << 8), 4, &ramdac); 1354 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1355 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1356 return retval; 1357 } 1358 1359 #include <dev/ic/decmonitors.c> 1360 void tga2_ics9110_wr __P(( 1361 struct tga_devconfig *dc, 1362 int dotclock 1363 )); 1364 1365 void 1366 tga2_init(dc, m) 1367 struct tga_devconfig *dc; 1368 int m; 1369 { 1370 1371 tga2_ics9110_wr(dc, decmonitors[m].dotclock); 1372 #if 0 1373 TGAWREG(dc, TGA_REG_VHCR, 1374 ((decmonitors[m].hbp / 4) << 21) | 1375 ((decmonitors[m].hsync / 4) << 14) | 1376 (((decmonitors[m].hfp - 4) / 4) << 9) | 1377 ((decmonitors[m].cols + 4) / 4)); 1378 #else 1379 TGAWREG(dc, TGA_REG_VHCR, 1380 ((decmonitors[m].hbp / 4) << 21) | 1381 ((decmonitors[m].hsync / 4) << 14) | 1382 (((decmonitors[m].hfp) / 4) << 9) | 1383 ((decmonitors[m].cols) / 4)); 1384 #endif 1385 TGAWREG(dc, TGA_REG_VVCR, 1386 (decmonitors[m].vbp << 22) | 1387 (decmonitors[m].vsync << 16) | 1388 (decmonitors[m].vfp << 11) | 1389 (decmonitors[m].rows)); 1390 TGAWREG(dc, TGA_REG_VVBR, 1); 1391 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1392 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1393 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1394 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1395 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1396 } 1397 1398 void 1399 tga2_ics9110_wr(dc, dotclock) 1400 struct tga_devconfig *dc; 1401 int dotclock; 1402 { 1403 bus_space_handle_t clock; 1404 u_int32_t valU; 1405 int N, M, R, V, X; 1406 int i; 1407 1408 switch (dotclock) { 1409 case 130808000: 1410 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1411 case 119840000: 1412 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1413 case 108180000: 1414 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1415 case 103994000: 1416 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1417 case 175000000: 1418 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1419 case 75000000: 1420 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1421 case 74000000: 1422 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1423 case 69000000: 1424 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1425 case 65000000: 1426 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1427 case 50000000: 1428 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1429 case 40000000: 1430 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1431 case 31500000: 1432 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1433 case 25175000: 1434 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1435 case 135000000: 1436 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1437 case 110000000: 1438 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1439 case 202500000: 1440 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1441 default: 1442 panic("unrecognized clock rate %d\n", dotclock); 1443 } 1444 1445 /* XXX -- hard coded, bad */ 1446 valU = N | ( M << 7 ) | (V << 14); 1447 valU |= (X << 15) | (R << 17); 1448 valU |= 0x17 << 19; 1449 1450 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1451 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1452 1453 for (i=24; i>0; i--) { 1454 u_int32_t writeval; 1455 1456 writeval = valU & 0x1; 1457 if (i == 1) 1458 writeval |= 0x2; 1459 valU >>= 1; 1460 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1461 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1462 } 1463 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1464 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1465 &clock); /* XXX */ 1466 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1467 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1468 } 1469