1 /* $NetBSD: tga.c,v 1.80 2010/11/13 13:52:08 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.80 2010/11/13 13:52:08 uebayasi Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 int tgamatch(device_t, cfdata_t, void *); 62 void tgaattach(device_t, device_t, void *); 63 int tgaprint(void *, const char *); 64 65 CFATTACH_DECL_NEW(tga, sizeof(struct tga_softc), 66 tgamatch, tgaattach, NULL, NULL); 67 68 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 69 pcitag_t tag, struct tga_devconfig *dc); 70 71 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 72 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 73 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 74 unsigned int tga_getdotclock(struct tga_devconfig *dc); 75 76 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 77 paddr_t tga_mmap(void *, void *, off_t, int); 78 static void tga_copyrows(void *, int, int, int); 79 static void tga_copycols(void *, int, int, int, int); 80 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 81 void **, int *, int *, long *); 82 static void tga_free_screen(void *, void *); 83 static int tga_show_screen(void *, void *, int, 84 void (*) (void *, int, int), void *); 85 static int tga_rop(struct rasops_info *, int, int, int, int, int, 86 struct rasops_info *, int, int); 87 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 88 int, struct rasops_info *, int, int); 89 static void tga_putchar(void *c, int row, int col, u_int uc, long attr); 90 static void tga_eraserows(void *, int, int, long); 91 static void tga_erasecols(void *, int, int, int, long); 92 void tga2_init(struct tga_devconfig *); 93 94 static void tga_config_interrupts(device_t); 95 96 /* RAMDAC interface functions */ 97 static int tga_sched_update(void *, void (*)(void *)); 98 static void tga_ramdac_wr(void *, u_int, uint8_t); 99 static uint8_t tga_ramdac_rd(void *, u_int); 100 static void tga_bt463_wr(void *, u_int, uint8_t); 101 static uint8_t tga_bt463_rd(void *, u_int); 102 static void tga2_ramdac_wr(void *, u_int, uint8_t); 103 static uint8_t tga2_ramdac_rd(void *, u_int); 104 105 /* Interrupt handler */ 106 static int tga_intr(void *); 107 108 struct tga_devconfig tga_console_dc; 109 110 /* The NULL entries will get filled in by rasops_init(). 111 * XXX and the non-NULL ones will be overwritten; reset after calling it. 112 */ 113 struct wsdisplay_emulops tga_emulops = { 114 NULL, 115 NULL, 116 tga_putchar, 117 tga_copycols, 118 tga_erasecols, 119 tga_copyrows, 120 tga_eraserows, 121 NULL, 122 NULL, 123 }; 124 125 struct wsscreen_descr tga_stdscreen = { 126 "std", 127 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 128 &tga_emulops, 129 0, 0, 130 WSSCREEN_REVERSE, 131 NULL, 132 }; 133 134 const struct wsscreen_descr *_tga_scrlist[] = { 135 &tga_stdscreen, 136 /* XXX other formats, graphics screen? */ 137 }; 138 139 struct wsscreen_list tga_screenlist = { 140 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 141 }; 142 143 struct wsdisplay_accessops tga_accessops = { 144 tga_ioctl, 145 tga_mmap, 146 tga_alloc_screen, 147 tga_free_screen, 148 tga_show_screen, 149 NULL, /* load_font */ 150 NULL, 151 NULL, 152 }; 153 154 static void tga_blank(struct tga_devconfig *); 155 static void tga_unblank(struct tga_devconfig *); 156 157 int 158 tga_cnmatch(bus_space_tag_t iot, bus_space_tag_t memt, 159 pci_chipset_tag_t pc, pcitag_t tag) 160 { 161 162 return tga_matchcommon(memt, pc, tag); 163 } 164 165 int 166 tgamatch(device_t parent, cfdata_t match, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 170 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 171 return (0); 172 173 switch (PCI_PRODUCT(pa->pa_id)) { 174 case PCI_PRODUCT_DEC_21030: 175 case PCI_PRODUCT_DEC_PBXGB: 176 break; 177 default: 178 return 0; 179 } 180 181 #if defined(__alpha__) || defined(arc) 182 /* short-circuit the following test, as we 183 * already have the memory mapped and hence 184 * cannot perform it---and we are the console 185 * anyway. 186 */ 187 if (pa->pa_tag == tga_console_dc.dc_pcitag) 188 return 10; 189 #endif 190 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 191 } 192 193 static int 194 tga_matchcommon(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 195 { 196 struct tga_devconfig tmp_dc; 197 struct tga_devconfig *dc = &tmp_dc; 198 bus_size_t pcisize; 199 200 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 201 dc->dc_tga_type = tga_identify(dc); 202 203 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 204 bus_space_unmap(memt, dc->dc_memh, pcisize); 205 if (dc->dc_tgaconf) 206 return 10; 207 return 0; 208 } 209 210 static void 211 tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 212 bus_size_t *pcisize, struct tga_devconfig *dc) 213 { 214 int flags; 215 216 dc->dc_memt = memt; 217 dc->dc_tgaconf = NULL; 218 219 /* XXX magic number */ 220 if (pci_mapreg_info(pc, tag, 0x10, 221 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 222 &dc->dc_pcipaddr, pcisize, &flags)) 223 panic("tga_mapaddrs: pci_mapreg_info() failed"); 224 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 225 panic("tga memory not prefetchable"); 226 227 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 228 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 229 panic("tga_mapaddrs: could not map TGA address space"); 230 dc->dc_vaddr = (vaddr_t)bus_space_vaddr(memt, dc->dc_memh); 231 232 bus_space_subregion(dc->dc_memt, dc->dc_memh, 233 TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs); 234 } 235 236 static void 237 tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 238 struct tga_devconfig *dc) 239 { 240 const struct tga_conf *tgac; 241 struct rasops_info *rip; 242 int cookie; 243 bus_size_t pcisize; 244 int i; 245 246 dc->dc_pc = pc; 247 dc->dc_pcitag = tag; 248 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 249 dc->dc_tga_type = tga_identify(dc); 250 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 251 #if 0 252 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 253 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 254 panic("tga_init: memory size mismatch?"); 255 #endif 256 257 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 258 case 0x01: 259 case 0x02: 260 case 0x03: 261 case 0x04: 262 dc->dc_tga2 = 0; 263 break; 264 case 0x20: 265 case 0x21: 266 case 0x22: 267 dc->dc_tga2 = 1; 268 break; 269 default: 270 panic("tga_init: TGA Revision not recognized"); 271 } 272 273 if (dc->dc_tga2) 274 tga2_init(dc); 275 276 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 277 case 0: 278 dc->dc_wid = 8192; 279 break; 280 281 case 1: 282 dc->dc_wid = 8196; 283 break; 284 285 default: 286 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 287 break; 288 } 289 290 /* 291 * XXX XXX Turning off "odd" shouldn't be necessary, 292 * XXX XXX but I can't make X work with the weird size. 293 */ 294 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 295 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 296 TGAWREG(dc, TGA_REG_VHCR, 297 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 298 dc->dc_wid -= 4; 299 } 300 301 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 302 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 303 304 /* XXX this seems to be what DEC does */ 305 TGAWREG(dc, TGA_REG_CCBR, 0); 306 TGAWREG(dc, TGA_REG_VVBR, 1); 307 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 308 1 * tgac->tgac_vvbr_units; 309 dc->dc_blanked = 1; 310 tga_unblank(dc); 311 312 /* 313 * Set all bits in the pixel mask, to enable writes to all pixels. 314 * It seems that the console firmware clears some of them 315 * under some circumstances, which causes cute vertical stripes. 316 */ 317 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 318 319 /* clear the screen */ 320 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(uint32_t)) 321 *(uint32_t *)(dc->dc_videobase + i) = 0; 322 323 /* Initialize rasops descriptor */ 324 rip = &dc->dc_rinfo; 325 rip->ri_flg = RI_CENTER; 326 rip->ri_depth = tgac->tgac_phys_depth; 327 rip->ri_bits = (void *)dc->dc_videobase; 328 rip->ri_width = dc->dc_wid; 329 rip->ri_height = dc->dc_ht; 330 rip->ri_stride = dc->dc_rowbytes; 331 rip->ri_hw = dc; 332 if (dc == &tga_console_dc) 333 rip->ri_flg |= RI_NO_AUTO; 334 335 if (tgac->tgac_phys_depth == 32) { 336 rip->ri_rnum = 8; 337 rip->ri_gnum = 8; 338 rip->ri_bnum = 8; 339 rip->ri_rpos = 16; 340 rip->ri_gpos = 8; 341 rip->ri_bpos = 0; 342 } 343 344 wsfont_init(); 345 /* prefer 8 pixel wide font */ 346 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 347 WSDISPLAY_FONTORDER_L2R); 348 if (cookie <= 0) 349 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 350 WSDISPLAY_FONTORDER_L2R); 351 if (cookie <= 0) { 352 printf("tga: no appropriate fonts.\n"); 353 return; 354 } 355 356 /* the accelerated tga_putchar() needs LSbit left */ 357 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 358 printf("tga: couldn't lock font\n"); 359 return; 360 } 361 dc->dc_rinfo.ri_wsfcookie = cookie; 362 363 rasops_init(rip, 34, 80); 364 365 /* add our accelerated functions */ 366 /* XXX shouldn't have to do this; rasops should leave non-NULL 367 * XXX entries alone. 368 */ 369 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 370 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 371 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 372 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 373 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 374 375 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 376 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 377 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 378 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 379 380 381 dc->dc_intrenabled = 0; 382 } 383 384 void 385 tgaattach(device_t parent, device_t self, void *aux) 386 { 387 struct pci_attach_args *pa = aux; 388 struct tga_softc *sc = device_private(self); 389 struct tga_devconfig *dc; 390 struct wsemuldisplaydev_attach_args aa; 391 pci_intr_handle_t intrh; 392 const char *intrstr; 393 uint8_t rev; 394 int console; 395 396 sc->sc_dev = self; 397 398 #if defined(__alpha__) || defined(arc) 399 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 400 #else 401 console = 0; 402 #endif 403 if (console) { 404 sc->sc_dc = &tga_console_dc; 405 sc->sc_dc->dc_rinfo.ri_flg &= ~RI_NO_AUTO; 406 sc->nscreens = 1; 407 } else { 408 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 409 M_WAITOK|M_ZERO); 410 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 411 } 412 if (sc->sc_dc->dc_vaddr == 0) { 413 aprint_error(": couldn't map memory space; punt!\n"); 414 return; 415 } 416 417 /* XXX say what's going on. */ 418 intrstr = NULL; 419 if (pci_intr_map(pa, &intrh)) { 420 aprint_error(": couldn't map interrupt"); 421 return; 422 } 423 intrstr = pci_intr_string(pa->pa_pc, intrh); 424 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 425 sc->sc_dc); 426 if (sc->sc_intr == NULL) { 427 aprint_error(": couldn't establish interrupt"); 428 if (intrstr != NULL) 429 aprint_error("at %s", intrstr); 430 aprint_error("\n"); 431 return; 432 } 433 434 rev = PCI_REVISION(pa->pa_class); 435 switch (rev) { 436 case 0x1: 437 case 0x2: 438 case 0x3: 439 aprint_normal(": DC21030 step %c", 'A' + rev - 1); 440 break; 441 case 0x20: 442 aprint_normal(": TGA2 abstract software model"); 443 break; 444 case 0x21: 445 case 0x22: 446 aprint_normal(": TGA2 pass %d", rev - 0x20); 447 break; 448 449 default: 450 aprint_normal("unknown stepping (0x%x)", rev); 451 break; 452 } 453 aprint_normal(", "); 454 455 /* 456 * Get RAMDAC function vectors and call the RAMDAC functions 457 * to allocate its private storage and pass that back to us. 458 */ 459 460 dc = sc->sc_dc; 461 dc->dc_ramdac_funcs = dc->dc_tgaconf->ramdac_funcs(); 462 if (!dc->dc_tga2) { 463 if (dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 464 dc->dc_ramdac_cookie = 465 dc->dc_ramdac_funcs->ramdac_register(dc, 466 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 467 else 468 dc->dc_ramdac_cookie = 469 dc->dc_ramdac_funcs->ramdac_register(dc, 470 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 471 } else { 472 dc->dc_ramdac_cookie = dc->dc_ramdac_funcs->ramdac_register(dc, 473 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 474 475 /* XXX this is a bit of a hack, setting the dotclock here */ 476 if (dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 477 (*dc->dc_ramdac_funcs->ramdac_set_dotclock) 478 (dc->dc_ramdac_cookie, tga_getdotclock(dc)); 479 } 480 481 /* 482 * Initialize the RAMDAC. Initialization includes disabling 483 * cursor, setting a sane colormap, etc. We presume that we've 484 * filled in the necessary dot clock for PowerStorm 4d20. 485 */ 486 (*dc->dc_ramdac_funcs->ramdac_init)(dc->dc_ramdac_cookie); 487 TGAWREG(dc, TGA_REG_SISR, 0x00000001); /* XXX */ 488 489 if (dc->dc_tgaconf == NULL) { 490 aprint_error("unknown board configuration\n"); 491 return; 492 } 493 aprint_normal("board type %s\n", dc->dc_tgaconf->tgac_name); 494 aprint_normal_dev(self, "%d x %d, %dbpp, %s RAMDAC\n", 495 dc->dc_wid, dc->dc_ht, 496 dc->dc_tgaconf->tgac_phys_depth, 497 dc->dc_ramdac_funcs->ramdac_name); 498 499 if (intrstr != NULL) 500 aprint_normal_dev(self, "interrupting at %s\n", 501 intrstr); 502 503 aa.console = console; 504 aa.scrdata = &tga_screenlist; 505 aa.accessops = &tga_accessops; 506 aa.accesscookie = sc; 507 508 config_found(self, &aa, wsemuldisplaydevprint); 509 510 config_interrupts(self, tga_config_interrupts); 511 } 512 513 static void 514 tga_config_interrupts(device_t self) 515 { 516 struct tga_softc *sc; 517 518 sc = device_private(self); 519 sc->sc_dc->dc_intrenabled = 1; 520 } 521 522 int 523 tga_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 524 { 525 struct tga_softc *sc = v; 526 struct tga_devconfig *dc = sc->sc_dc; 527 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 528 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 529 530 switch (cmd) { 531 case WSDISPLAYIO_GTYPE: 532 *(u_int *)data = WSDISPLAY_TYPE_TGA; 533 return 0; 534 535 case WSDISPLAYIO_GINFO: 536 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 537 wsd_fbip->height = sc->sc_dc->dc_ht; 538 wsd_fbip->width = sc->sc_dc->dc_wid; 539 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 540 #if 0 541 wsd_fbip->cmsize = 256; /* XXX ??? */ 542 #else 543 wsd_fbip->cmsize = 1024; /* XXX ??? */ 544 #endif 545 #undef wsd_fbip 546 return 0; 547 548 case WSDISPLAYIO_GETCMAP: 549 return (*dcrf->ramdac_get_cmap)(dcrc, 550 (struct wsdisplay_cmap *)data); 551 552 case WSDISPLAYIO_PUTCMAP: 553 return (*dcrf->ramdac_set_cmap)(dcrc, 554 (struct wsdisplay_cmap *)data); 555 556 case WSDISPLAYIO_SVIDEO: 557 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 558 tga_blank(sc->sc_dc); 559 else 560 tga_unblank(sc->sc_dc); 561 return 0; 562 563 case WSDISPLAYIO_GVIDEO: 564 *(u_int *)data = dc->dc_blanked ? 565 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 566 return 0; 567 568 case WSDISPLAYIO_GCURPOS: 569 return (*dcrf->ramdac_get_curpos)(dcrc, 570 (struct wsdisplay_curpos *)data); 571 572 case WSDISPLAYIO_SCURPOS: 573 return (*dcrf->ramdac_set_curpos)(dcrc, 574 (struct wsdisplay_curpos *)data); 575 576 case WSDISPLAYIO_GCURMAX: 577 return (*dcrf->ramdac_get_curmax)(dcrc, 578 (struct wsdisplay_curpos *)data); 579 580 case WSDISPLAYIO_GCURSOR: 581 return (*dcrf->ramdac_get_cursor)(dcrc, 582 (struct wsdisplay_cursor *)data); 583 584 case WSDISPLAYIO_SCURSOR: 585 return (*dcrf->ramdac_set_cursor)(dcrc, 586 (struct wsdisplay_cursor *)data); 587 588 case WSDISPLAYIO_LINEBYTES: 589 *(u_int *)data = dc->dc_rowbytes; 590 return 0; 591 592 /* PCI config read/write passthrough. */ 593 case PCI_IOC_CFGREAD: 594 case PCI_IOC_CFGWRITE: 595 return pci_devioctl(dc->dc_pc, dc->dc_pcitag, 596 cmd, data, flag, l); 597 } 598 return EPASSTHROUGH; 599 } 600 601 static int 602 tga_sched_update(void *v, void (*f)(void *)) 603 { 604 struct tga_devconfig *dc = v; 605 606 if (dc->dc_intrenabled) { 607 /* 608 * Arrange for f to be called at the next end-of-frame 609 * interrupt. 610 */ 611 dc->dc_ramdac_intr = f; 612 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 613 } else { 614 /* Spin until the end-of-frame, then call f */ 615 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 616 TGAREGWB(dc, TGA_REG_SISR, 1); 617 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 618 continue; 619 f(dc->dc_ramdac_cookie); 620 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 621 TGAREGWB(dc, TGA_REG_SISR, 1); 622 } 623 624 return 0; 625 } 626 627 static int 628 tga_intr(void *v) 629 { 630 struct tga_devconfig *dc = v; 631 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 632 633 uint32_t reg; 634 635 reg = TGARREG(dc, TGA_REG_SISR); 636 if (( reg & 0x00010001) != 0x00010001) { 637 /* Odd. We never set any of the other interrupt enables. */ 638 if ((reg & 0x1f) != 0) { 639 /* Clear the mysterious pending interrupts. */ 640 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 641 TGAREGWB(dc, TGA_REG_SISR, 1); 642 /* 643 * This was our interrupt, even if we're puzzled 644 * as to why we got it. Don't make the interrupt 645 * handler think it was a stray. 646 */ 647 return -1; 648 } else { 649 return 0; 650 } 651 } 652 /* if we have something to do, do it */ 653 if (dc->dc_ramdac_intr) { 654 dc->dc_ramdac_intr(dcrc); 655 dc->dc_ramdac_intr = NULL; 656 } 657 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 658 TGAREGWB(dc, TGA_REG_SISR, 1); 659 return 1; 660 } 661 662 paddr_t 663 tga_mmap(void *v, void *vs, off_t offset, int prot) 664 { 665 struct tga_softc *sc = v; 666 667 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 668 return -1; 669 670 return bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 671 offset, prot, BUS_SPACE_MAP_LINEAR); 672 } 673 674 static int 675 tga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 676 int *curxp, int *curyp, long *attrp) 677 { 678 struct tga_softc *sc = v; 679 long defattr; 680 681 if (sc->nscreens > 0) 682 return ENOMEM; 683 684 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 685 *curxp = 0; 686 *curyp = 0; 687 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 688 0, 0, 0, &defattr); 689 *attrp = defattr; 690 sc->nscreens++; 691 return 0; 692 } 693 694 static void 695 tga_free_screen(void *v, void *cookie) 696 { 697 struct tga_softc *sc = v; 698 699 if (sc->sc_dc == &tga_console_dc) 700 panic("tga_free_screen: console"); 701 702 sc->nscreens--; 703 } 704 705 static int 706 tga_show_screen(void *v, void *cookie, int waitok, 707 void (*cb)(void *, int, int), void *cbarg) 708 { 709 710 return 0; 711 } 712 713 int 714 tga_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 715 pci_chipset_tag_t pc, int bus, int device, int function) 716 { 717 struct tga_devconfig *dcp = &tga_console_dc; 718 long defattr; 719 720 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 721 722 /* sanity checks */ 723 if (dcp->dc_vaddr == 0) 724 panic("tga_console(%d, %d): couldn't map memory space", 725 device, function); 726 if (dcp->dc_tgaconf == NULL) 727 panic("tga_console(%d, %d): unknown board configuration", 728 device, function); 729 730 /* 731 * Initialize the RAMDAC but DO NOT allocate any private storage. 732 * Initialization includes disabling cursor, setting a sane 733 * colormap, etc. It will be reinitialized in tgaattach(). 734 */ 735 if (dcp->dc_tga2) { 736 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 737 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 738 tga2_ramdac_rd); 739 else 740 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 741 tga2_ramdac_rd, tga_getdotclock(dcp)); 742 } else { 743 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 744 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 745 tga_ramdac_rd); 746 else { 747 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 748 tga_bt463_rd); 749 } 750 } 751 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 752 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 753 754 return 0; 755 } 756 757 /* 758 * Functions to blank and unblank the display. 759 */ 760 static void 761 tga_blank(struct tga_devconfig *dc) 762 { 763 764 if (!dc->dc_blanked) { 765 dc->dc_blanked = 1; 766 /* XXX */ 767 TGAWREG(dc, TGA_REG_VVVR, 768 TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 769 } 770 } 771 772 static void 773 tga_unblank(struct tga_devconfig *dc) 774 { 775 776 if (dc->dc_blanked) { 777 dc->dc_blanked = 0; 778 /* XXX */ 779 TGAWREG(dc, TGA_REG_VVVR, 780 TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 781 } 782 } 783 784 /* 785 * Functions to manipulate the built-in cursor handing hardware. 786 */ 787 int 788 tga_builtin_set_cursor(struct tga_devconfig *dc, 789 struct wsdisplay_cursor *cursorp) 790 { 791 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 792 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 793 uint8_t image[512]; 794 u_int count, v; 795 int error; 796 797 v = cursorp->which; 798 if (v & WSDISPLAY_CURSOR_DOCMAP) { 799 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 800 if (error) 801 return error; 802 } 803 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 804 if ((u_int)cursorp->size.x != 64 || 805 (u_int)cursorp->size.y > 64) 806 return EINVAL; 807 /* The cursor is 2 bits deep, and there is no mask */ 808 count = (cursorp->size.y * 64 * 2) / NBBY; 809 error = copyin(cursorp->image, image, count); 810 if (error) 811 return error; 812 } 813 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 814 return EINVAL; 815 816 /* parameters are OK; do it */ 817 if (v & WSDISPLAY_CURSOR_DOCUR) { 818 if (cursorp->enable) 819 /* XXX */ 820 TGAWREG(dc, TGA_REG_VVVR, 821 TGARREG(dc, TGA_REG_VVVR) | 0x04); 822 else 823 /* XXX */ 824 TGAWREG(dc, TGA_REG_VVVR, 825 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 826 } 827 if (v & WSDISPLAY_CURSOR_DOPOS) { 828 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 829 (cursorp->pos.x & 0xfff)); 830 } 831 if (v & WSDISPLAY_CURSOR_DOCMAP) { 832 dcrf->ramdac_set_curcmap(dcrc, cursorp); 833 } 834 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 835 count = ((64 * 2) / NBBY) * cursorp->size.y; 836 TGAWREG(dc, TGA_REG_CCBR, 837 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 838 (cursorp->size.y << 10)); 839 memcpy((void *)(dc->dc_vaddr + 840 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 841 image, count); 842 } 843 return 0; 844 } 845 846 int 847 tga_builtin_get_cursor(struct tga_devconfig *dc, 848 struct wsdisplay_cursor *cursorp) 849 { 850 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 851 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 852 int count, error; 853 854 cursorp->which = WSDISPLAY_CURSOR_DOALL & 855 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 856 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 857 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 858 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 859 cursorp->size.x = 64; 860 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 861 862 if (cursorp->image != NULL) { 863 count = (cursorp->size.y * 64 * 2) / NBBY; 864 error = copyout((char *)(dc->dc_vaddr + 865 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 866 cursorp->image, count); 867 if (error) 868 return error; 869 /* No mask */ 870 } 871 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 872 return error; 873 } 874 875 int 876 tga_builtin_set_curpos(struct tga_devconfig *dc, 877 struct wsdisplay_curpos *curposp) 878 { 879 880 TGAWREG(dc, TGA_REG_CXYR, 881 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 882 return 0; 883 } 884 885 int 886 tga_builtin_get_curpos(struct tga_devconfig *dc, 887 struct wsdisplay_curpos *curposp) 888 { 889 890 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 891 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 892 return 0; 893 } 894 895 int 896 tga_builtin_get_curmax(struct tga_devconfig *dc, 897 struct wsdisplay_curpos *curposp) 898 { 899 900 curposp->x = curposp->y = 64; 901 return 0; 902 } 903 904 /* 905 * Copy columns (characters) in a row (line). 906 */ 907 static void 908 tga_copycols(void *id, int row, int srccol, int dstcol, int ncols) 909 { 910 struct rasops_info *ri = id; 911 int y, srcx, dstx, nx; 912 913 y = ri->ri_font->fontheight * row; 914 srcx = ri->ri_font->fontwidth * srccol; 915 dstx = ri->ri_font->fontwidth * dstcol; 916 nx = ri->ri_font->fontwidth * ncols; 917 918 tga_rop(ri, dstx, y, 919 nx, ri->ri_font->fontheight, RAS_SRC, 920 ri, srcx, y); 921 } 922 923 /* 924 * Copy rows (lines). 925 */ 926 static void 927 tga_copyrows(void *id, int srcrow, int dstrow, int nrows) 928 { 929 struct rasops_info *ri = id; 930 int srcy, dsty, ny; 931 932 srcy = ri->ri_font->fontheight * srcrow; 933 dsty = ri->ri_font->fontheight * dstrow; 934 ny = ri->ri_font->fontheight * nrows; 935 936 tga_rop(ri, 0, dsty, 937 ri->ri_emuwidth, ny, RAS_SRC, 938 ri, 0, srcy); 939 } 940 941 /* Do we need the src? */ 942 static const int needsrc[16] = 943 { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 944 945 /* A mapping between our API and the TGA card */ 946 static const int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 947 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 948 }; 949 950 /* 951 * Generic TGA raster op. 952 * This covers all possible raster ops, and 953 * clips the sizes and all of that. 954 */ 955 static int 956 tga_rop(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 957 struct rasops_info *src, int sx, int sy) 958 { 959 960 if (dst == NULL) 961 return -1; 962 if (needsrc[RAS_GETOP(rop)]) { 963 if (src == NULL) 964 return -1; /* We want a src */ 965 /* Clip against src */ 966 if (sx < 0) { 967 w += sx; 968 sx = 0; 969 } 970 if (sy < 0) { 971 h += sy; 972 sy = 0; 973 } 974 if (sx + w > src->ri_emuwidth) 975 w = src->ri_emuwidth - sx; 976 if (sy + h > src->ri_emuheight) 977 h = src->ri_emuheight - sy; 978 } else { 979 if (src != NULL) 980 return -1; /* We need no src */ 981 } 982 /* Clip against dst. We modify src regardless of using it, 983 * since it really doesn't matter. 984 */ 985 if (dx < 0) { 986 w += dx; 987 sx -= dx; 988 dx = 0; 989 } 990 if (dy < 0) { 991 h += dy; 992 sy -= dy; 993 dy = 0; 994 } 995 if (dx + w > dst->ri_emuwidth) 996 w = dst->ri_emuwidth - dx; 997 if (dy + h > dst->ri_emuheight) 998 h = dst->ri_emuheight - dy; 999 if (w <= 0 || h <= 0) 1000 return 0; /* Vacuously true; */ 1001 if (src == NULL) { 1002 /* XXX Punt! */ 1003 return -1; 1004 } 1005 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1006 } 1007 1008 1009 1010 /* 1011 * Video to Video raster ops. 1012 * This function deals with all raster ops that have a src and dst 1013 * that are on the card. 1014 */ 1015 static int 1016 tga_rop_vtov(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 1017 struct rasops_info *src, int sx, int sy) 1018 { 1019 struct tga_devconfig *dc = dst->ri_hw; 1020 int srcb, dstb, tga_srcb, tga_dstb; 1021 int x, y, wb; 1022 int xstart, xend, xdir; 1023 int ystart, yend, ydir, yinc; 1024 int xleft, lastx, lastleft; 1025 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1026 1027 /* 1028 * I don't yet want to deal with unaligned guys, really. And we don't 1029 * deal with copies from one card to another. 1030 */ 1031 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1032 /* XXX Punt! */ 1033 /* XXX should never happen, since it's only being used to 1034 * XXX copy 8-pixel-wide characters. 1035 */ 1036 return -1; 1037 } 1038 1039 srcb = sy * src->ri_stride + sx * (src->ri_depth / 8); 1040 dstb = dy * dst->ri_stride + dx * (dst->ri_depth / 8); 1041 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1042 (sx + src->ri_xorigin) * (src->ri_depth / 8); 1043 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1044 (dx + dst->ri_xorigin) * (dst->ri_depth / 8); 1045 1046 if (sy >= dy) { 1047 ystart = 0; 1048 yend = (h - 1) * dst->ri_stride; 1049 ydir = 1; 1050 } else { 1051 ystart = (h - 1) * dst->ri_stride; 1052 yend = 0; 1053 ydir = -1; 1054 } 1055 yinc = ydir * dst->ri_stride; 1056 1057 wb = w * (dst->ri_depth / 8); 1058 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1059 xstart = 0; 1060 xend = wb; 1061 xdir = 1; 1062 } else { /* copy backwards */ 1063 xstart = wb; 1064 xend = 0; 1065 xdir = -1; 1066 } 1067 1068 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1069 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1070 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1071 1072 /* 1073 * we have 3 sizes of pixels to move in X direction: 1074 * 4 * 64 (unrolled TGA ops) 1075 * 64 (single TGA op) 1076 * 4 (CPU, using long word) 1077 */ 1078 1079 if (xdir == 1) { /* move to the left */ 1080 1081 if (wb & ~63) 1082 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1083 /* 4 * 64 byte chunks */ 1084 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1085 x += 4 * 64, xleft -= 4 * 64) { 1086 1087 /* 1088 * XXX XXX Eight writes to different addresses 1089 * XXX XXX should fill up the write buffers on 1090 * XXX XXX 21064 and 21164 chips, but later 1091 * XXX XXX CPUs might have larger write buffers 1092 * XXX XXX which require further unrolling of 1093 * XXX XXX this loop, or the insertion of 1094 * XXX XXX memory barriers. 1095 */ 1096 TGAWALREG(dc, TGA_REG_GCSR, 0, 1097 tga_srcb + y + x + 0 * 64); 1098 TGAWALREG(dc, TGA_REG_GCDR, 0, 1099 tga_dstb + y + x + 0 * 64); 1100 TGAWALREG(dc, TGA_REG_GCSR, 1, 1101 tga_srcb + y + x + 1 * 64); 1102 TGAWALREG(dc, TGA_REG_GCDR, 1, 1103 tga_dstb + y + x + 1 * 64); 1104 TGAWALREG(dc, TGA_REG_GCSR, 2, 1105 tga_srcb + y + x + 2 * 64); 1106 TGAWALREG(dc, TGA_REG_GCDR, 2, 1107 tga_dstb + y + x + 2 * 64); 1108 TGAWALREG(dc, TGA_REG_GCSR, 3, 1109 tga_srcb + y + x + 3 * 64); 1110 TGAWALREG(dc, TGA_REG_GCDR, 3, 1111 tga_dstb + y + x + 3 * 64); 1112 } 1113 1114 /* 64 byte chunks */ 1115 for (; xleft >= 64; x += 64, xleft -= 64) { 1116 TGAWALREG(dc, TGA_REG_GCSR, 0, 1117 tga_srcb + y + x + 0 * 64); 1118 TGAWALREG(dc, TGA_REG_GCDR, 0, 1119 tga_dstb + y + x + 0 * 64); 1120 } 1121 } 1122 1123 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1124 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1125 1126 lastleft = wb & 63; 1127 if (lastleft) { 1128 lastx = xstart + (wb & ~63); 1129 for (y = ystart; (ydir * y) <= (ydir * yend); 1130 y += yinc) { 1131 /* 4 byte granularity */ 1132 for (x = lastx, xleft = lastleft; xleft >= 4; 1133 x += 4, xleft -= 4) { 1134 *(uint32_t *)(dst->ri_bits + dstb + 1135 y + x + 0 * 4) = 1136 *(uint32_t *)(dst->ri_bits + srcb + 1137 y + x + 0 * 4); 1138 } 1139 } 1140 } 1141 } else { /* above move to the left, below move to the right */ 1142 1143 if (wb & ~63) 1144 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1145 /* 4 * 64 byte chunks */ 1146 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1147 x -= 4 * 64, xleft -= 4 * 64) { 1148 1149 /* 1150 * XXX XXX Eight writes to different addresses 1151 * XXX XXX should fill up the write buffers on 1152 * XXX XXX 21064 and 21164 chips, but later 1153 * XXX XXX CPUs might have larger write buffers 1154 * XXX XXX which require further unrolling of 1155 * XXX XXX this loop, or the insertion of 1156 * XXX XXX memory barriers. 1157 */ 1158 TGAWALREG(dc, TGA_REG_GCSR, 0, 1159 tga_srcb + y + x - 1 * 64); 1160 TGAWALREG(dc, TGA_REG_GCDR, 0, 1161 tga_dstb + y + x - 1 * 64); 1162 TGAWALREG(dc, TGA_REG_GCSR, 1, 1163 tga_srcb + y + x - 2 * 64); 1164 TGAWALREG(dc, TGA_REG_GCDR, 1, 1165 tga_dstb + y + x - 2 * 64); 1166 TGAWALREG(dc, TGA_REG_GCSR, 2, 1167 tga_srcb + y + x - 3 * 64); 1168 TGAWALREG(dc, TGA_REG_GCDR, 2, 1169 tga_dstb + y + x - 3 * 64); 1170 TGAWALREG(dc, TGA_REG_GCSR, 3, 1171 tga_srcb + y + x - 4 * 64); 1172 TGAWALREG(dc, TGA_REG_GCDR, 3, 1173 tga_dstb + y + x - 4 * 64); 1174 } 1175 1176 /* 64 byte chunks */ 1177 for (; xleft >= 64; x -= 64, xleft -= 64) { 1178 TGAWALREG(dc, TGA_REG_GCSR, 0, 1179 tga_srcb + y + x - 1 * 64); 1180 TGAWALREG(dc, TGA_REG_GCDR, 0, 1181 tga_dstb + y + x - 1 * 64); 1182 } 1183 } 1184 1185 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1186 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1187 1188 lastleft = wb & 63; 1189 if (lastleft) { 1190 lastx = xstart - (wb & ~63); 1191 for (y = ystart; (ydir * y) <= (ydir * yend); 1192 y += yinc) { 1193 /* 4 byte granularity */ 1194 for (x = lastx, xleft = lastleft; xleft >= 4; 1195 x -= 4, xleft -= 4) { 1196 *(uint32_t *)(dst->ri_bits + dstb + 1197 y + x - 1 * 4) = 1198 *(uint32_t *)(dst->ri_bits + srcb + 1199 y + x - 1 * 4); 1200 } 1201 } 1202 } 1203 } 1204 return 0; 1205 } 1206 1207 1208 void tga_putchar(void *c, int row, int col, u_int uc, long attr) 1209 { 1210 struct rasops_info *ri = c; 1211 struct tga_devconfig *dc = ri->ri_hw; 1212 int fs, height, width; 1213 uint8_t *fr; 1214 int32_t *rp; 1215 1216 rp = (int32_t *)(ri->ri_bits + 1217 row * ri->ri_yscale + col * ri->ri_xscale); 1218 1219 height = ri->ri_font->fontheight; 1220 width = ri->ri_font->fontwidth; 1221 1222 uc -= ri->ri_font->firstchar; 1223 fr = (uint8_t *)ri->ri_font->data + uc * ri->ri_fontscale; 1224 fs = ri->ri_font->stride; 1225 1226 /* Set foreground and background color. XXX memoize this somehow? 1227 * The rasops code has already expanded the color entry to 32 bits 1228 * for us, even for 8-bit displays, so we don't have to do anything. 1229 */ 1230 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1231 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1232 1233 /* Set raster operation to "copy"... */ 1234 if (ri->ri_depth == 8) 1235 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1236 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1237 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1238 1239 /* Set which pixels we're drawing (of a possible 32). */ 1240 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1241 1242 /* Set drawing mode to opaque stipple. */ 1243 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1244 1245 /* Insert write barrier before actually sending data */ 1246 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1247 TGAREGWB(dc, TGA_REG_GMOR, 1); 1248 1249 while (height--) { 1250 /* The actual stipple write */ 1251 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1252 1253 fr += fs; 1254 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1255 } 1256 1257 /* Do underline */ 1258 if ((attr & 1) != 0) { 1259 rp = (int32_t *)((uint8_t *)rp - (ri->ri_stride << 1)); 1260 *rp = 0xffffffff; 1261 } 1262 1263 /* Set grapics mode back to normal. */ 1264 TGAWREG(dc, TGA_REG_GMOR, 0); 1265 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1266 } 1267 1268 static void 1269 tga_eraserows(void *c, int row, int num, long attr) 1270 { 1271 struct rasops_info *ri = c; 1272 struct tga_devconfig *dc = ri->ri_hw; 1273 int32_t color, lines, pixels; 1274 int32_t *rp; 1275 1276 color = ri->ri_devcmap[(attr >> 16) & 15]; 1277 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1278 lines = num * ri->ri_font->fontheight; 1279 pixels = ri->ri_emuwidth - 1; 1280 1281 /* Set fill color in block-color registers */ 1282 TGAWREG(dc, TGA_REG_GBCR0, color); 1283 TGAWREG(dc, TGA_REG_GBCR1, color); 1284 if (ri->ri_depth != 8) { 1285 TGAWREG(dc, TGA_REG_GBCR2, color); 1286 TGAWREG(dc, TGA_REG_GBCR3, color); 1287 TGAWREG(dc, TGA_REG_GBCR4, color); 1288 TGAWREG(dc, TGA_REG_GBCR5, color); 1289 TGAWREG(dc, TGA_REG_GBCR6, color); 1290 TGAWREG(dc, TGA_REG_GBCR7, color); 1291 } 1292 1293 /* Set raster operation to "copy"... */ 1294 if (ri->ri_depth == 8) 1295 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1296 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1297 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1298 1299 /* Set which pixels we're drawing (of a possible 32). */ 1300 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1301 1302 /* Set drawing mode to block fill. */ 1303 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1304 1305 /* Insert write barrier before actually sending data */ 1306 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1307 TGAREGWB(dc, TGA_REG_GMOR, 1); 1308 1309 while (lines--) { 1310 *rp = pixels; 1311 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1312 } 1313 1314 /* Set grapics mode back to normal. */ 1315 TGAWREG(dc, TGA_REG_GMOR, 0); 1316 } 1317 1318 static void 1319 tga_erasecols (void *c, int row, int col, int num, long attr) 1320 { 1321 struct rasops_info *ri = c; 1322 struct tga_devconfig *dc = ri->ri_hw; 1323 int32_t color, lines, pixels; 1324 int32_t *rp; 1325 1326 color = ri->ri_devcmap[(attr >> 16) & 15]; 1327 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1328 lines = ri->ri_font->fontheight; 1329 pixels = (num * ri->ri_font->fontwidth) - 1; 1330 1331 /* Set fill color in block-color registers */ 1332 TGAWREG(dc, TGA_REG_GBCR0, color); 1333 TGAWREG(dc, TGA_REG_GBCR1, color); 1334 if (ri->ri_depth != 8) { 1335 TGAWREG(dc, TGA_REG_GBCR2, color); 1336 TGAWREG(dc, TGA_REG_GBCR3, color); 1337 TGAWREG(dc, TGA_REG_GBCR4, color); 1338 TGAWREG(dc, TGA_REG_GBCR5, color); 1339 TGAWREG(dc, TGA_REG_GBCR6, color); 1340 TGAWREG(dc, TGA_REG_GBCR7, color); 1341 } 1342 1343 /* Set raster operation to "copy"... */ 1344 if (ri->ri_depth == 8) 1345 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1346 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1347 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1348 1349 /* Set which pixels we're drawing (of a possible 32). */ 1350 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1351 1352 /* Set drawing mode to block fill. */ 1353 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1354 1355 /* Insert write barrier before actually sending data */ 1356 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1357 TGAREGWB(dc, TGA_REG_GMOR, 1); 1358 1359 while (lines--) { 1360 *rp = pixels; 1361 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1362 } 1363 1364 /* Set grapics mode back to normal. */ 1365 TGAWREG(dc, TGA_REG_GMOR, 0); 1366 } 1367 1368 1369 static void 1370 tga_ramdac_wr(void *v, u_int btreg, uint8_t val) 1371 { 1372 struct tga_devconfig *dc = v; 1373 1374 if (btreg > BT485_REG_MAX) 1375 panic("tga_ramdac_wr: reg %d out of range", btreg); 1376 1377 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1378 TGAREGWB(dc, TGA_REG_EPDR, 1); 1379 } 1380 1381 static void 1382 tga2_ramdac_wr(void *v, u_int btreg, uint8_t val) 1383 { 1384 struct tga_devconfig *dc = v; 1385 bus_space_handle_t ramdac; 1386 1387 if (btreg > BT485_REG_MAX) 1388 panic("tga_ramdac_wr: reg %d out of range", btreg); 1389 1390 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1391 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1392 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1393 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1394 } 1395 1396 static uint8_t 1397 tga_bt463_rd(void *v, u_int btreg) 1398 { 1399 struct tga_devconfig *dc = v; 1400 tga_reg_t rdval; 1401 1402 /* 1403 * Strobe CE# (high->low->high) since status and data are latched on 1404 * the falling and rising edges (repsectively) of this active-low 1405 * signal. 1406 */ 1407 1408 TGAREGWB(dc, TGA_REG_EPSR, 1); 1409 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1410 TGAREGWB(dc, TGA_REG_EPSR, 1); 1411 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1412 1413 TGAREGRB(dc, TGA_REG_EPSR, 1); 1414 1415 rdval = TGARREG(dc, TGA_REG_EPDR); 1416 TGAREGWB(dc, TGA_REG_EPSR, 1); 1417 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1418 1419 return (rdval >> 16) & 0xff; 1420 } 1421 1422 static void 1423 tga_bt463_wr(void *v, u_int btreg, uint8_t val) 1424 { 1425 struct tga_devconfig *dc = v; 1426 1427 /* 1428 * In spite of the 21030 documentation, to set the MPU bus bits for 1429 * a write, you set them in the upper bits of EPDR, not EPSR. 1430 */ 1431 1432 /* 1433 * Strobe CE# (high->low->high) since status and data are latched on 1434 * the falling and rising edges of this active-low signal. 1435 */ 1436 1437 TGAREGWB(dc, TGA_REG_EPDR, 1); 1438 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1439 TGAREGWB(dc, TGA_REG_EPDR, 1); 1440 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1441 TGAREGWB(dc, TGA_REG_EPDR, 1); 1442 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1443 } 1444 1445 static uint8_t 1446 tga_ramdac_rd(void *v, u_int btreg) 1447 { 1448 struct tga_devconfig *dc = v; 1449 tga_reg_t rdval; 1450 1451 if (btreg > BT485_REG_MAX) 1452 panic("tga_ramdac_rd: reg %d out of range", btreg); 1453 1454 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1455 TGAREGWB(dc, TGA_REG_EPSR, 1); 1456 1457 rdval = TGARREG(dc, TGA_REG_EPDR); 1458 return (rdval >> 16) & 0xff; /* XXX */ 1459 } 1460 1461 static uint8_t 1462 tga2_ramdac_rd(void *v, u_int btreg) 1463 { 1464 struct tga_devconfig *dc = v; 1465 bus_space_handle_t ramdac; 1466 uint8_t retval; 1467 1468 if (btreg > BT485_REG_MAX) 1469 panic("tga_ramdac_rd: reg %d out of range", btreg); 1470 1471 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1472 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1473 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1474 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1475 return retval; 1476 } 1477 1478 #include <dev/ic/decmonitors.c> 1479 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1480 1481 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1482 1483 void 1484 tga2_init(struct tga_devconfig *dc) 1485 { 1486 struct monitor *m = tga_getmonitor(dc); 1487 1488 /* Deal with the dot clocks. 1489 */ 1490 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1491 /* 1492 * Set this up as a reference clock for the 1493 * ibm561's PLL. 1494 */ 1495 tga2_ics9110_wr(dc, 14300000); 1496 /* 1497 * XXX Can't set up the dotclock properly, until such time 1498 * as the RAMDAC is configured. 1499 */ 1500 } else { 1501 /* otherwise the ics9110 is our clock. */ 1502 tga2_ics9110_wr(dc, m->dotclock); 1503 } 1504 #if 0 1505 TGAWREG(dc, TGA_REG_VHCR, 1506 ((m->hbp / 4) << 21) | 1507 ((m->hsync / 4) << 14) | 1508 (((m->hfp - 4) / 4) << 9) | 1509 ((m->cols + 4) / 4)); 1510 #else 1511 TGAWREG(dc, TGA_REG_VHCR, 1512 ((m->hbp / 4) << 21) | 1513 ((m->hsync / 4) << 14) | 1514 (((m->hfp) / 4) << 9) | 1515 ((m->cols) / 4)); 1516 #endif 1517 TGAWREG(dc, TGA_REG_VVCR, 1518 (m->vbp << 22) | 1519 (m->vsync << 16) | 1520 (m->vfp << 11) | 1521 (m->rows)); 1522 TGAWREG(dc, TGA_REG_VVBR, 1); 1523 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1524 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1525 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1526 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1527 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1528 } 1529 1530 void 1531 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock) 1532 { 1533 bus_space_handle_t clock; 1534 uint32_t valU; 1535 int N, M, R, V, X; 1536 int i; 1537 1538 switch (dotclock) { 1539 case 130808000: 1540 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1541 case 119840000: 1542 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1543 case 108180000: 1544 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1545 case 103994000: 1546 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1547 case 175000000: 1548 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1549 case 75000000: 1550 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1551 case 74000000: 1552 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1553 case 69000000: 1554 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1555 case 65000000: 1556 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1557 case 50000000: 1558 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1559 case 40000000: 1560 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1561 case 31500000: 1562 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1563 case 25175000: 1564 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1565 case 135000000: 1566 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1567 case 110000000: 1568 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1569 case 202500000: 1570 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1571 case 14300000: /* this one is just a ref clock */ 1572 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1573 default: 1574 panic("unrecognized clock rate %d", dotclock); 1575 } 1576 1577 /* XXX -- hard coded, bad */ 1578 valU = N | ( M << 7 ) | (V << 14); 1579 valU |= (X << 15) | (R << 17); 1580 valU |= 0x17 << 19; 1581 1582 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1583 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1584 1585 for (i = 24; i > 0; i--) { 1586 uint32_t writeval; 1587 1588 writeval = valU & 0x1; 1589 if (i == 1) 1590 writeval |= 0x2; 1591 valU >>= 1; 1592 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1593 bus_space_barrier(dc->dc_memt, clock, 0, 4, 1594 BUS_SPACE_BARRIER_WRITE); 1595 } 1596 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1597 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1598 &clock); /* XXX */ 1599 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1600 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1601 } 1602 1603 struct monitor * 1604 tga_getmonitor(struct tga_devconfig *dc) 1605 { 1606 1607 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1608 } 1609 1610 unsigned int 1611 tga_getdotclock(struct tga_devconfig *dc) 1612 { 1613 1614 return tga_getmonitor(dc)->dotclock; 1615 } 1616