1 /* $NetBSD: tga.c,v 1.69 2009/01/07 01:31:01 ahoka Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.69 2009/01/07 01:31:01 ahoka Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <uvm/uvm_extern.h> 62 63 int tgamatch(struct device *, struct cfdata *, void *); 64 void tgaattach(struct device *, struct device *, void *); 65 int tgaprint(void *, const char *); 66 67 CFATTACH_DECL(tga, sizeof(struct tga_softc), 68 tgamatch, tgaattach, NULL, NULL); 69 70 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 71 pcitag_t tag, struct tga_devconfig *dc); 72 73 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 74 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 75 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 76 unsigned tga_getdotclock(struct tga_devconfig *dc); 77 78 struct tga_devconfig tga_console_dc; 79 80 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 81 paddr_t tga_mmap(void *, void *, off_t, int); 82 static void tga_copyrows(void *, int, int, int); 83 static void tga_copycols(void *, int, int, int, int); 84 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 85 void **, int *, int *, long *); 86 static void tga_free_screen(void *, void *); 87 static int tga_show_screen(void *, void *, int, 88 void (*) (void *, int, int), void *); 89 static int tga_rop(struct rasops_info *, int, int, int, int, int, 90 struct rasops_info *, int, int); 91 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 92 int, struct rasops_info *, int, int); 93 static void tga_putchar(void *c, int row, int col, 94 u_int uc, long attr); 95 static void tga_eraserows(void *, int, int, long); 96 static void tga_erasecols(void *, int, int, int, long); 97 void tga2_init(struct tga_devconfig *); 98 99 static void tga_config_interrupts(struct device *); 100 101 /* RAMDAC interface functions */ 102 static int tga_sched_update(void *, void (*)(void *)); 103 static void tga_ramdac_wr(void *, u_int, u_int8_t); 104 static u_int8_t tga_ramdac_rd(void *, u_int); 105 static void tga_bt463_wr(void *, u_int, u_int8_t); 106 static u_int8_t tga_bt463_rd(void *, u_int); 107 static void tga2_ramdac_wr(void *, u_int, u_int8_t); 108 static u_int8_t tga2_ramdac_rd(void *, u_int); 109 110 /* Interrupt handler */ 111 static int tga_intr(void *); 112 113 /* The NULL entries will get filled in by rasops_init(). 114 * XXX and the non-NULL ones will be overwritten; reset after calling it. 115 */ 116 struct wsdisplay_emulops tga_emulops = { 117 NULL, 118 NULL, 119 tga_putchar, 120 tga_copycols, 121 tga_erasecols, 122 tga_copyrows, 123 tga_eraserows, 124 NULL, 125 NULL, 126 }; 127 128 struct wsscreen_descr tga_stdscreen = { 129 "std", 130 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 131 &tga_emulops, 132 0, 0, 133 WSSCREEN_REVERSE, 134 NULL, 135 }; 136 137 const struct wsscreen_descr *_tga_scrlist[] = { 138 &tga_stdscreen, 139 /* XXX other formats, graphics screen? */ 140 }; 141 142 struct wsscreen_list tga_screenlist = { 143 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 144 }; 145 146 struct wsdisplay_accessops tga_accessops = { 147 tga_ioctl, 148 tga_mmap, 149 tga_alloc_screen, 150 tga_free_screen, 151 tga_show_screen, 152 NULL, /* load_font */ 153 NULL, 154 NULL, 155 }; 156 157 static void tga_blank(struct tga_devconfig *); 158 static void tga_unblank(struct tga_devconfig *); 159 160 int 161 tga_cnmatch(iot, memt, pc, tag) 162 bus_space_tag_t iot, memt; 163 pci_chipset_tag_t pc; 164 pcitag_t tag; 165 { 166 return tga_matchcommon(memt, pc, tag); 167 } 168 169 int 170 tgamatch(parent, match, aux) 171 struct device *parent; 172 struct cfdata *match; 173 void *aux; 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 178 return (0); 179 180 switch (PCI_PRODUCT(pa->pa_id)) { 181 case PCI_PRODUCT_DEC_21030: 182 case PCI_PRODUCT_DEC_PBXGB: 183 break; 184 default: 185 return 0; 186 } 187 188 #if defined(__alpha__) || defined(arc) 189 /* short-circuit the following test, as we 190 * already have the memory mapped and hence 191 * cannot perform it---and we are the console 192 * anyway. 193 */ 194 if (pa->pa_tag == tga_console_dc.dc_pcitag) 195 return 10; 196 #endif 197 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 198 } 199 200 static int 201 tga_matchcommon(memt, pc, tag) 202 bus_space_tag_t memt; 203 pci_chipset_tag_t pc; 204 pcitag_t tag; 205 { 206 struct tga_devconfig tmp_dc; 207 struct tga_devconfig *dc = &tmp_dc; 208 bus_size_t pcisize; 209 210 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 211 dc->dc_tga_type = tga_identify(dc); 212 213 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 214 bus_space_unmap(memt, dc->dc_memh, pcisize); 215 if (dc->dc_tgaconf) 216 return 10; 217 return 0; 218 } 219 220 static void 221 tga_mapaddrs(memt, pc, tag, pcisize, dc) 222 bus_space_tag_t memt; 223 pci_chipset_tag_t pc; 224 pcitag_t tag; 225 bus_size_t *pcisize; 226 struct tga_devconfig *dc; 227 { 228 int flags; 229 230 dc->dc_memt = memt; 231 dc->dc_tgaconf = NULL; 232 233 /* XXX magic number */ 234 if (pci_mapreg_info(pc, tag, 0x10, 235 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 236 &dc->dc_pcipaddr, pcisize, &flags)) 237 panic("tga_mapaddrs: pci_mapreg_info() failed"); 238 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 239 panic("tga memory not prefetchable"); 240 241 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 242 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 243 panic("tga_mapaddrs: could not map TGA address space"); 244 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 245 246 bus_space_subregion(dc->dc_memt, dc->dc_memh, 247 TGA_MEM_CREGS, TGA_CREGS_SIZE, 248 &dc->dc_regs); 249 } 250 251 static void 252 tga_init(memt, pc, tag, dc) 253 bus_space_tag_t memt; 254 pci_chipset_tag_t pc; 255 pcitag_t tag; 256 struct tga_devconfig *dc; 257 { 258 const struct tga_conf *tgac; 259 struct rasops_info *rip; 260 int cookie; 261 bus_size_t pcisize; 262 int i; 263 264 dc->dc_pc = pc; 265 dc->dc_pcitag = tag; 266 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 267 dc->dc_tga_type = tga_identify(dc); 268 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 269 #if 0 270 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 271 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 272 panic("tga_init: memory size mismatch?"); 273 #endif 274 275 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 276 case 0x01: 277 case 0x02: 278 case 0x03: 279 case 0x04: 280 dc->dc_tga2 = 0; 281 break; 282 case 0x20: 283 case 0x21: 284 case 0x22: 285 dc->dc_tga2 = 1; 286 break; 287 default: 288 panic("tga_init: TGA Revision not recognized"); 289 } 290 291 if (dc->dc_tga2) 292 tga2_init(dc); 293 294 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 295 case 0: 296 dc->dc_wid = 8192; 297 break; 298 299 case 1: 300 dc->dc_wid = 8196; 301 break; 302 303 default: 304 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 305 break; 306 } 307 308 /* 309 * XXX XXX Turning off "odd" shouldn't be necessary, 310 * XXX XXX but I can't make X work with the weird size. 311 */ 312 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 313 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 314 TGAWREG(dc, TGA_REG_VHCR, 315 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 316 dc->dc_wid -= 4; 317 } 318 319 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 320 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 321 322 /* XXX this seems to be what DEC does */ 323 TGAWREG(dc, TGA_REG_CCBR, 0); 324 TGAWREG(dc, TGA_REG_VVBR, 1); 325 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 326 1 * tgac->tgac_vvbr_units; 327 dc->dc_blanked = 1; 328 tga_unblank(dc); 329 330 /* 331 * Set all bits in the pixel mask, to enable writes to all pixels. 332 * It seems that the console firmware clears some of them 333 * under some circumstances, which causes cute vertical stripes. 334 */ 335 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 336 337 /* clear the screen */ 338 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 339 *(u_int32_t *)(dc->dc_videobase + i) = 0; 340 341 /* Initialize rasops descriptor */ 342 rip = &dc->dc_rinfo; 343 rip->ri_flg = RI_CENTER; 344 rip->ri_depth = tgac->tgac_phys_depth; 345 rip->ri_bits = (void *)dc->dc_videobase; 346 rip->ri_width = dc->dc_wid; 347 rip->ri_height = dc->dc_ht; 348 rip->ri_stride = dc->dc_rowbytes; 349 rip->ri_hw = dc; 350 351 if (tgac->tgac_phys_depth == 32) { 352 rip->ri_rnum = 8; 353 rip->ri_gnum = 8; 354 rip->ri_bnum = 8; 355 rip->ri_rpos = 16; 356 rip->ri_gpos = 8; 357 rip->ri_bpos = 0; 358 } 359 360 wsfont_init(); 361 /* prefer 8 pixel wide font */ 362 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 363 WSDISPLAY_FONTORDER_L2R); 364 if (cookie <= 0) 365 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 366 WSDISPLAY_FONTORDER_L2R); 367 if (cookie <= 0) { 368 printf("tga: no appropriate fonts.\n"); 369 return; 370 } 371 372 /* the accelerated tga_putchar() needs LSbit left */ 373 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 374 printf("tga: couldn't lock font\n"); 375 return; 376 } 377 dc->dc_rinfo.ri_wsfcookie = cookie; 378 379 rasops_init(rip, 34, 80); 380 381 /* add our accelerated functions */ 382 /* XXX shouldn't have to do this; rasops should leave non-NULL 383 * XXX entries alone. 384 */ 385 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 386 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 387 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 388 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 389 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 390 391 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 392 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 393 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 394 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 395 396 397 dc->dc_intrenabled = 0; 398 } 399 400 void 401 tgaattach(parent, self, aux) 402 struct device *parent, *self; 403 void *aux; 404 { 405 struct pci_attach_args *pa = aux; 406 struct tga_softc *sc = (struct tga_softc *)self; 407 struct wsemuldisplaydev_attach_args aa; 408 pci_intr_handle_t intrh; 409 const char *intrstr; 410 u_int8_t rev; 411 int console; 412 413 #if defined(__alpha__) || defined(arc) 414 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 415 #else 416 console = 0; 417 #endif 418 if (console) { 419 sc->sc_dc = &tga_console_dc; 420 sc->nscreens = 1; 421 } else { 422 sc->sc_dc = (struct tga_devconfig *) 423 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 424 M_WAITOK|M_ZERO); 425 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 426 } 427 if (sc->sc_dc->dc_vaddr == 0) { 428 printf(": couldn't map memory space; punt!\n"); 429 return; 430 } 431 432 /* XXX say what's going on. */ 433 intrstr = NULL; 434 if (pci_intr_map(pa, &intrh)) { 435 printf(": couldn't map interrupt"); 436 return; 437 } 438 intrstr = pci_intr_string(pa->pa_pc, intrh); 439 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 440 sc->sc_dc); 441 if (sc->sc_intr == NULL) { 442 printf(": couldn't establish interrupt"); 443 if (intrstr != NULL) 444 printf("at %s", intrstr); 445 printf("\n"); 446 return; 447 } 448 449 rev = PCI_REVISION(pa->pa_class); 450 switch (rev) { 451 case 0x1: 452 case 0x2: 453 case 0x3: 454 printf(": DC21030 step %c", 'A' + rev - 1); 455 break; 456 case 0x20: 457 printf(": TGA2 abstract software model"); 458 break; 459 case 0x21: 460 case 0x22: 461 printf(": TGA2 pass %d", rev - 0x20); 462 break; 463 464 default: 465 printf("unknown stepping (0x%x)", rev); 466 break; 467 } 468 printf(", "); 469 470 /* 471 * Get RAMDAC function vectors and call the RAMDAC functions 472 * to allocate its private storage and pass that back to us. 473 */ 474 475 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 476 if (!sc->sc_dc->dc_tga2) { 477 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 478 sc->sc_dc->dc_ramdac_cookie = 479 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 480 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 481 else 482 sc->sc_dc->dc_ramdac_cookie = 483 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 484 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 485 } else { 486 sc->sc_dc->dc_ramdac_cookie = 487 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 488 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 489 490 /* XXX this is a bit of a hack, setting the dotclock here */ 491 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 492 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 493 (sc->sc_dc->dc_ramdac_cookie, 494 tga_getdotclock(sc->sc_dc)); 495 } 496 497 /* 498 * Initialize the RAMDAC. Initialization includes disabling 499 * cursor, setting a sane colormap, etc. We presume that we've 500 * filled in the necessary dot clock for PowerStorm 4d20. 501 */ 502 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 503 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 504 505 if (sc->sc_dc->dc_tgaconf == NULL) { 506 printf("unknown board configuration\n"); 507 return; 508 } 509 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 510 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", device_xname(&sc->sc_dev), 511 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 512 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 513 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 514 515 if (intrstr != NULL) 516 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), 517 intrstr); 518 519 aa.console = console; 520 aa.scrdata = &tga_screenlist; 521 aa.accessops = &tga_accessops; 522 aa.accesscookie = sc; 523 524 config_found(self, &aa, wsemuldisplaydevprint); 525 526 config_interrupts(self, tga_config_interrupts); 527 } 528 529 static void 530 tga_config_interrupts (d) 531 struct device *d; 532 { 533 struct tga_softc *sc = (struct tga_softc *)d; 534 sc->sc_dc->dc_intrenabled = 1; 535 } 536 537 int 538 tga_ioctl(v, vs, cmd, data, flag, l) 539 void *v; 540 void *vs; 541 u_long cmd; 542 void *data; 543 int flag; 544 struct lwp *l; 545 { 546 struct tga_softc *sc = v; 547 struct tga_devconfig *dc = sc->sc_dc; 548 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 549 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 550 551 switch (cmd) { 552 case WSDISPLAYIO_GTYPE: 553 *(u_int *)data = WSDISPLAY_TYPE_TGA; 554 return (0); 555 556 case WSDISPLAYIO_GINFO: 557 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 558 wsd_fbip->height = sc->sc_dc->dc_ht; 559 wsd_fbip->width = sc->sc_dc->dc_wid; 560 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 561 #if 0 562 wsd_fbip->cmsize = 256; /* XXX ??? */ 563 #else 564 wsd_fbip->cmsize = 1024; /* XXX ??? */ 565 #endif 566 #undef wsd_fbip 567 return (0); 568 569 case WSDISPLAYIO_GETCMAP: 570 return (*dcrf->ramdac_get_cmap)(dcrc, 571 (struct wsdisplay_cmap *)data); 572 573 case WSDISPLAYIO_PUTCMAP: 574 return (*dcrf->ramdac_set_cmap)(dcrc, 575 (struct wsdisplay_cmap *)data); 576 577 case WSDISPLAYIO_SVIDEO: 578 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 579 tga_blank(sc->sc_dc); 580 else 581 tga_unblank(sc->sc_dc); 582 return (0); 583 584 case WSDISPLAYIO_GVIDEO: 585 *(u_int *)data = dc->dc_blanked ? 586 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 587 return (0); 588 589 case WSDISPLAYIO_GCURPOS: 590 return (*dcrf->ramdac_get_curpos)(dcrc, 591 (struct wsdisplay_curpos *)data); 592 593 case WSDISPLAYIO_SCURPOS: 594 return (*dcrf->ramdac_set_curpos)(dcrc, 595 (struct wsdisplay_curpos *)data); 596 597 case WSDISPLAYIO_GCURMAX: 598 return (*dcrf->ramdac_get_curmax)(dcrc, 599 (struct wsdisplay_curpos *)data); 600 601 case WSDISPLAYIO_GCURSOR: 602 return (*dcrf->ramdac_get_cursor)(dcrc, 603 (struct wsdisplay_cursor *)data); 604 605 case WSDISPLAYIO_SCURSOR: 606 return (*dcrf->ramdac_set_cursor)(dcrc, 607 (struct wsdisplay_cursor *)data); 608 609 case WSDISPLAYIO_LINEBYTES: 610 *(u_int *)data = dc->dc_rowbytes; 611 return (0); 612 613 /* PCI config read/write passthrough. */ 614 case PCI_IOC_CFGREAD: 615 case PCI_IOC_CFGWRITE: 616 return (pci_devioctl(dc->dc_pc, dc->dc_pcitag, 617 cmd, data, flag, l)); 618 } 619 return (EPASSTHROUGH); 620 } 621 622 static int 623 tga_sched_update(v, f) 624 void *v; 625 void (*f)(void *); 626 { 627 struct tga_devconfig *dc = v; 628 629 if (dc->dc_intrenabled) { 630 /* Arrange for f to be called at the next end-of-frame interrupt */ 631 dc->dc_ramdac_intr = f; 632 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 633 } else { 634 /* Spin until the end-of-frame, then call f */ 635 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 636 TGAREGWB(dc, TGA_REG_SISR, 1); 637 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 638 ; 639 f(dc->dc_ramdac_cookie); 640 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 641 TGAREGWB(dc, TGA_REG_SISR, 1); 642 } 643 644 return 0; 645 } 646 647 static int 648 tga_intr(v) 649 void *v; 650 { 651 struct tga_devconfig *dc = v; 652 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 653 654 u_int32_t reg; 655 656 reg = TGARREG(dc, TGA_REG_SISR); 657 if (( reg & 0x00010001) != 0x00010001) { 658 /* Odd. We never set any of the other interrupt enables. */ 659 if ((reg & 0x1f) != 0) { 660 /* Clear the mysterious pending interrupts. */ 661 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 662 TGAREGWB(dc, TGA_REG_SISR, 1); 663 /* This was our interrupt, even if we're puzzled as to why 664 * we got it. Don't make the interrupt handler think it 665 * was a stray. 666 */ 667 return -1; 668 } else { 669 return 0; 670 } 671 } 672 /* if we have something to do, do it */ 673 if (dc->dc_ramdac_intr) { 674 dc->dc_ramdac_intr(dcrc); 675 dc->dc_ramdac_intr = NULL; 676 } 677 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 678 TGAREGWB(dc, TGA_REG_SISR, 1); 679 return (1); 680 } 681 682 paddr_t 683 tga_mmap(v, vs, offset, prot) 684 void *v; 685 void *vs; 686 off_t offset; 687 int prot; 688 { 689 struct tga_softc *sc = v; 690 691 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 692 return -1; 693 694 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 695 offset, prot, BUS_SPACE_MAP_LINEAR)); 696 } 697 698 static int 699 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 700 void *v; 701 const struct wsscreen_descr *type; 702 void **cookiep; 703 int *curxp, *curyp; 704 long *attrp; 705 { 706 struct tga_softc *sc = v; 707 long defattr; 708 709 if (sc->nscreens > 0) 710 return (ENOMEM); 711 712 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 713 *curxp = 0; 714 *curyp = 0; 715 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 716 0, 0, 0, &defattr); 717 *attrp = defattr; 718 sc->nscreens++; 719 return (0); 720 } 721 722 static void 723 tga_free_screen(v, cookie) 724 void *v; 725 void *cookie; 726 { 727 struct tga_softc *sc = v; 728 729 if (sc->sc_dc == &tga_console_dc) 730 panic("tga_free_screen: console"); 731 732 sc->nscreens--; 733 } 734 735 static int 736 tga_show_screen(v, cookie, waitok, cb, cbarg) 737 void *v; 738 void *cookie; 739 int waitok; 740 void (*cb)(void *, int, int); 741 void *cbarg; 742 { 743 744 return (0); 745 } 746 747 int 748 tga_cnattach(iot, memt, pc, bus, device, function) 749 bus_space_tag_t iot, memt; 750 pci_chipset_tag_t pc; 751 int bus, device, function; 752 { 753 struct tga_devconfig *dcp = &tga_console_dc; 754 long defattr; 755 756 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 757 758 /* sanity checks */ 759 if (dcp->dc_vaddr == 0) 760 panic("tga_console(%d, %d): couldn't map memory space", 761 device, function); 762 if (dcp->dc_tgaconf == NULL) 763 panic("tga_console(%d, %d): unknown board configuration", 764 device, function); 765 766 /* 767 * Initialize the RAMDAC but DO NOT allocate any private storage. 768 * Initialization includes disabling cursor, setting a sane 769 * colormap, etc. It will be reinitialized in tgaattach(). 770 */ 771 if (dcp->dc_tga2) { 772 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 773 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 774 tga2_ramdac_rd); 775 else 776 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 777 tga2_ramdac_rd, tga_getdotclock(dcp)); 778 } else { 779 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 780 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 781 tga_ramdac_rd); 782 else { 783 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 784 tga_bt463_rd); 785 } 786 } 787 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 788 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 789 790 return(0); 791 } 792 793 /* 794 * Functions to blank and unblank the display. 795 */ 796 static void 797 tga_blank(dc) 798 struct tga_devconfig *dc; 799 { 800 801 if (!dc->dc_blanked) { 802 dc->dc_blanked = 1; 803 /* XXX */ 804 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 805 } 806 } 807 808 static void 809 tga_unblank(dc) 810 struct tga_devconfig *dc; 811 { 812 813 if (dc->dc_blanked) { 814 dc->dc_blanked = 0; 815 /* XXX */ 816 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 817 } 818 } 819 820 /* 821 * Functions to manipulate the built-in cursor handing hardware. 822 */ 823 int 824 tga_builtin_set_cursor(dc, cursorp) 825 struct tga_devconfig *dc; 826 struct wsdisplay_cursor *cursorp; 827 { 828 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 829 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 830 u_char image[512]; 831 u_int count, v; 832 int error; 833 834 v = cursorp->which; 835 if (v & WSDISPLAY_CURSOR_DOCMAP) { 836 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 837 if (error) 838 return (error); 839 } 840 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 841 if ((u_int)cursorp->size.x != 64 || 842 (u_int)cursorp->size.y > 64) 843 return (EINVAL); 844 /* The cursor is 2 bits deep, and there is no mask */ 845 count = (cursorp->size.y * 64 * 2) / NBBY; 846 error = copyin(cursorp->image, image, count); 847 if (error) 848 return error; 849 } 850 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 851 return EINVAL; 852 853 /* parameters are OK; do it */ 854 if (v & WSDISPLAY_CURSOR_DOCUR) { 855 if (cursorp->enable) 856 /* XXX */ 857 TGAWREG(dc, TGA_REG_VVVR, 858 TGARREG(dc, TGA_REG_VVVR) | 0x04); 859 else 860 /* XXX */ 861 TGAWREG(dc, TGA_REG_VVVR, 862 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 863 } 864 if (v & WSDISPLAY_CURSOR_DOPOS) { 865 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 866 (cursorp->pos.x & 0xfff)); 867 } 868 if (v & WSDISPLAY_CURSOR_DOCMAP) { 869 dcrf->ramdac_set_curcmap(dcrc, cursorp); 870 } 871 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 872 count = ((64 * 2) / NBBY) * cursorp->size.y; 873 TGAWREG(dc, TGA_REG_CCBR, 874 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 875 (cursorp->size.y << 10)); 876 memcpy((char *)(dc->dc_vaddr + 877 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 878 image, count); 879 } 880 return (0); 881 } 882 883 int 884 tga_builtin_get_cursor(dc, cursorp) 885 struct tga_devconfig *dc; 886 struct wsdisplay_cursor *cursorp; 887 { 888 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 889 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 890 int count, error; 891 892 cursorp->which = WSDISPLAY_CURSOR_DOALL & 893 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 894 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 895 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 896 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 897 cursorp->size.x = 64; 898 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 899 900 if (cursorp->image != NULL) { 901 count = (cursorp->size.y * 64 * 2) / NBBY; 902 error = copyout((char *)(dc->dc_vaddr + 903 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 904 cursorp->image, count); 905 if (error) 906 return (error); 907 /* No mask */ 908 } 909 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 910 return (error); 911 } 912 913 int 914 tga_builtin_set_curpos(dc, curposp) 915 struct tga_devconfig *dc; 916 struct wsdisplay_curpos *curposp; 917 { 918 919 TGAWREG(dc, TGA_REG_CXYR, 920 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 921 return (0); 922 } 923 924 int 925 tga_builtin_get_curpos(dc, curposp) 926 struct tga_devconfig *dc; 927 struct wsdisplay_curpos *curposp; 928 { 929 930 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 931 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 932 return (0); 933 } 934 935 int 936 tga_builtin_get_curmax(dc, curposp) 937 struct tga_devconfig *dc; 938 struct wsdisplay_curpos *curposp; 939 { 940 941 curposp->x = curposp->y = 64; 942 return (0); 943 } 944 945 /* 946 * Copy columns (characters) in a row (line). 947 */ 948 static void 949 tga_copycols(id, row, srccol, dstcol, ncols) 950 void *id; 951 int row, srccol, dstcol, ncols; 952 { 953 struct rasops_info *ri = id; 954 int y, srcx, dstx, nx; 955 956 y = ri->ri_font->fontheight * row; 957 srcx = ri->ri_font->fontwidth * srccol; 958 dstx = ri->ri_font->fontwidth * dstcol; 959 nx = ri->ri_font->fontwidth * ncols; 960 961 tga_rop(ri, dstx, y, 962 nx, ri->ri_font->fontheight, RAS_SRC, 963 ri, srcx, y); 964 } 965 966 /* 967 * Copy rows (lines). 968 */ 969 static void 970 tga_copyrows(id, srcrow, dstrow, nrows) 971 void *id; 972 int srcrow, dstrow, nrows; 973 { 974 struct rasops_info *ri = id; 975 int srcy, dsty, ny; 976 977 srcy = ri->ri_font->fontheight * srcrow; 978 dsty = ri->ri_font->fontheight * dstrow; 979 ny = ri->ri_font->fontheight * nrows; 980 981 tga_rop(ri, 0, dsty, 982 ri->ri_emuwidth, ny, RAS_SRC, 983 ri, 0, srcy); 984 } 985 986 /* Do we need the src? */ 987 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 988 989 /* A mapping between our API and the TGA card */ 990 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 991 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 992 }; 993 994 /* 995 * Generic TGA raster op. 996 * This covers all possible raster ops, and 997 * clips the sizes and all of that. 998 */ 999 static int 1000 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 1001 struct rasops_info *dst; 1002 int dx, dy, w, h, rop; 1003 struct rasops_info *src; 1004 int sx, sy; 1005 { 1006 if (!dst) 1007 return -1; 1008 if (needsrc[RAS_GETOP(rop)]) { 1009 if (src == NULL) 1010 return -1; /* We want a src */ 1011 /* Clip against src */ 1012 if (sx < 0) { 1013 w += sx; 1014 sx = 0; 1015 } 1016 if (sy < 0) { 1017 h += sy; 1018 sy = 0; 1019 } 1020 if (sx + w > src->ri_emuwidth) 1021 w = src->ri_emuwidth - sx; 1022 if (sy + h > src->ri_emuheight) 1023 h = src->ri_emuheight - sy; 1024 } else { 1025 if (src != NULL) 1026 return -1; /* We need no src */ 1027 } 1028 /* Clip against dst. We modify src regardless of using it, 1029 * since it really doesn't matter. 1030 */ 1031 if (dx < 0) { 1032 w += dx; 1033 sx -= dx; 1034 dx = 0; 1035 } 1036 if (dy < 0) { 1037 h += dy; 1038 sy -= dy; 1039 dy = 0; 1040 } 1041 if (dx + w > dst->ri_emuwidth) 1042 w = dst->ri_emuwidth - dx; 1043 if (dy + h > dst->ri_emuheight) 1044 h = dst->ri_emuheight - dy; 1045 if (w <= 0 || h <= 0) 1046 return 0; /* Vacuously true; */ 1047 if (!src) { 1048 /* XXX Punt! */ 1049 return -1; 1050 } 1051 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1052 } 1053 1054 1055 1056 /* 1057 * Video to Video raster ops. 1058 * This function deals with all raster ops that have a src and dst 1059 * that are on the card. 1060 */ 1061 static int 1062 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1063 struct rasops_info *dst; 1064 int dx, dy, w, h, rop; 1065 struct rasops_info *src; 1066 int sx, sy; 1067 { 1068 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1069 int srcb, dstb, tga_srcb, tga_dstb; 1070 int x, y, wb; 1071 int xstart, xend, xdir; 1072 int ystart, yend, ydir, yinc; 1073 int xleft, lastx, lastleft; 1074 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1075 1076 /* 1077 * I don't yet want to deal with unaligned guys, really. And we don't 1078 * deal with copies from one card to another. 1079 */ 1080 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1081 /* XXX Punt! */ 1082 /* XXX should never happen, since it's only being used to 1083 * XXX copy 8-pixel-wide characters. 1084 */ 1085 return -1; 1086 } 1087 1088 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1089 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1090 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1091 (sx + src->ri_xorigin) * (src->ri_depth/8); 1092 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1093 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1094 1095 if (sy >= dy) { 1096 ystart = 0; 1097 yend = (h - 1) * dst->ri_stride; 1098 ydir = 1; 1099 } else { 1100 ystart = (h - 1) * dst->ri_stride; 1101 yend = 0; 1102 ydir = -1; 1103 } 1104 yinc = ydir * dst->ri_stride; 1105 1106 wb = w * (dst->ri_depth / 8); 1107 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1108 xstart = 0; 1109 xend = wb; 1110 xdir = 1; 1111 } else { /* copy backwards */ 1112 xstart = wb; 1113 xend = 0; 1114 xdir = -1; 1115 } 1116 1117 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1118 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1119 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1120 1121 /* 1122 * we have 3 sizes of pixels to move in X direction: 1123 * 4 * 64 (unrolled TGA ops) 1124 * 64 (single TGA op) 1125 * 4 (CPU, using long word) 1126 */ 1127 1128 if (xdir == 1) { /* move to the left */ 1129 1130 if (wb & ~63) 1131 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1132 /* 4*64 byte chunks */ 1133 for (xleft = wb, x = xstart; xleft >= 4*64; 1134 x += 4*64, xleft -= 4*64) { 1135 1136 /* XXX XXX Eight writes to different addresses should fill 1137 * XXX XXX up the write buffers on 21064 and 21164 chips, 1138 * XXX XXX but later CPUs might have larger write buffers which 1139 * XXX XXX require further unrolling of this loop, or the 1140 * XXX XXX insertion of memory barriers. 1141 */ 1142 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1143 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1144 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1145 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1146 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1147 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1148 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1149 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1150 } 1151 1152 /* 64 byte chunks */ 1153 for (; xleft >= 64; x += 64, xleft -= 64) { 1154 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1155 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1156 } 1157 } 1158 1159 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1160 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1161 1162 lastleft = wb & 63; 1163 if (lastleft) { 1164 lastx = xstart + (wb & ~63); 1165 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1166 /* 4 byte granularity */ 1167 for (x = lastx, xleft = lastleft; xleft >= 4; 1168 x += 4, xleft -= 4) { 1169 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1170 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1171 } 1172 } 1173 } 1174 } 1175 else { /* above move to the left, below move to the right */ 1176 1177 if (wb & ~63) 1178 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1179 /* 4*64 byte chunks */ 1180 for (xleft = wb, x = xstart; xleft >= 4*64; 1181 x -= 4*64, xleft -= 4*64) { 1182 1183 /* XXX XXX Eight writes to different addresses should fill 1184 * XXX XXX up the write buffers on 21064 and 21164 chips, 1185 * XXX XXX but later CPUs might have larger write buffers which 1186 * XXX XXX require further unrolling of this loop, or the 1187 * XXX XXX insertion of memory barriers. 1188 */ 1189 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1190 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1191 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1192 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1193 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1194 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1195 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1196 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1197 } 1198 1199 /* 64 byte chunks */ 1200 for (; xleft >= 64; x -= 64, xleft -= 64) { 1201 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1202 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1203 } 1204 } 1205 1206 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1207 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1208 1209 lastleft = wb & 63; 1210 if (lastleft) { 1211 lastx = xstart - (wb & ~63); 1212 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1213 /* 4 byte granularity */ 1214 for (x = lastx, xleft = lastleft; xleft >= 4; 1215 x -= 4, xleft -= 4) { 1216 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1217 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1218 } 1219 } 1220 } 1221 } 1222 return 0; 1223 } 1224 1225 1226 void tga_putchar (c, row, col, uc, attr) 1227 void *c; 1228 int row, col; 1229 u_int uc; 1230 long attr; 1231 { 1232 struct rasops_info *ri = c; 1233 struct tga_devconfig *dc = ri->ri_hw; 1234 int fs, height, width; 1235 u_char *fr; 1236 int32_t *rp; 1237 1238 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1239 1240 height = ri->ri_font->fontheight; 1241 width = ri->ri_font->fontwidth; 1242 1243 uc -= ri->ri_font->firstchar; 1244 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1245 fs = ri->ri_font->stride; 1246 1247 /* Set foreground and background color. XXX memoize this somehow? 1248 * The rasops code has already expanded the color entry to 32 bits 1249 * for us, even for 8-bit displays, so we don't have to do anything. 1250 */ 1251 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1252 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1253 1254 /* Set raster operation to "copy"... */ 1255 if (ri->ri_depth == 8) 1256 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1257 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1258 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1259 1260 /* Set which pixels we're drawing (of a possible 32). */ 1261 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1262 1263 /* Set drawing mode to opaque stipple. */ 1264 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1265 1266 /* Insert write barrier before actually sending data */ 1267 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1268 TGAREGWB(dc, TGA_REG_GMOR, 1); 1269 1270 while(height--) { 1271 /* The actual stipple write */ 1272 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1273 1274 fr += fs; 1275 rp = (int32_t *)((char *)rp + ri->ri_stride); 1276 } 1277 1278 /* Do underline */ 1279 if ((attr & 1) != 0) { 1280 rp = (int32_t *)((char *)rp - (ri->ri_stride << 1)); 1281 *rp = 0xffffffff; 1282 } 1283 1284 /* Set grapics mode back to normal. */ 1285 TGAWREG(dc, TGA_REG_GMOR, 0); 1286 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1287 1288 } 1289 1290 static void 1291 tga_eraserows(c, row, num, attr) 1292 void *c; 1293 int row, num; 1294 long attr; 1295 { 1296 struct rasops_info *ri = c; 1297 struct tga_devconfig *dc = ri->ri_hw; 1298 int32_t color, lines, pixels; 1299 int32_t *rp; 1300 1301 color = ri->ri_devcmap[(attr >> 16) & 15]; 1302 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1303 lines = num * ri->ri_font->fontheight; 1304 pixels = ri->ri_emuwidth - 1; 1305 1306 /* Set fill color in block-color registers */ 1307 TGAWREG(dc, TGA_REG_GBCR0, color); 1308 TGAWREG(dc, TGA_REG_GBCR1, color); 1309 if (ri->ri_depth != 8) { 1310 TGAWREG(dc, TGA_REG_GBCR2, color); 1311 TGAWREG(dc, TGA_REG_GBCR3, color); 1312 TGAWREG(dc, TGA_REG_GBCR4, color); 1313 TGAWREG(dc, TGA_REG_GBCR5, color); 1314 TGAWREG(dc, TGA_REG_GBCR6, color); 1315 TGAWREG(dc, TGA_REG_GBCR7, color); 1316 } 1317 1318 /* Set raster operation to "copy"... */ 1319 if (ri->ri_depth == 8) 1320 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1321 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1322 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1323 1324 /* Set which pixels we're drawing (of a possible 32). */ 1325 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1326 1327 /* Set drawing mode to block fill. */ 1328 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1329 1330 /* Insert write barrier before actually sending data */ 1331 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1332 TGAREGWB(dc, TGA_REG_GMOR, 1); 1333 1334 while (lines--) { 1335 *rp = pixels; 1336 rp = (int32_t *)((char *)rp + ri->ri_stride); 1337 } 1338 1339 /* Set grapics mode back to normal. */ 1340 TGAWREG(dc, TGA_REG_GMOR, 0); 1341 1342 } 1343 1344 static void 1345 tga_erasecols (c, row, col, num, attr) 1346 void *c; 1347 int row, col, num; 1348 long attr; 1349 { 1350 struct rasops_info *ri = c; 1351 struct tga_devconfig *dc = ri->ri_hw; 1352 int32_t color, lines, pixels; 1353 int32_t *rp; 1354 1355 color = ri->ri_devcmap[(attr >> 16) & 15]; 1356 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1357 lines = ri->ri_font->fontheight; 1358 pixels = (num * ri->ri_font->fontwidth) - 1; 1359 1360 /* Set fill color in block-color registers */ 1361 TGAWREG(dc, TGA_REG_GBCR0, color); 1362 TGAWREG(dc, TGA_REG_GBCR1, color); 1363 if (ri->ri_depth != 8) { 1364 TGAWREG(dc, TGA_REG_GBCR2, color); 1365 TGAWREG(dc, TGA_REG_GBCR3, color); 1366 TGAWREG(dc, TGA_REG_GBCR4, color); 1367 TGAWREG(dc, TGA_REG_GBCR5, color); 1368 TGAWREG(dc, TGA_REG_GBCR6, color); 1369 TGAWREG(dc, TGA_REG_GBCR7, color); 1370 } 1371 1372 /* Set raster operation to "copy"... */ 1373 if (ri->ri_depth == 8) 1374 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1375 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1376 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1377 1378 /* Set which pixels we're drawing (of a possible 32). */ 1379 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1380 1381 /* Set drawing mode to block fill. */ 1382 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1383 1384 /* Insert write barrier before actually sending data */ 1385 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1386 TGAREGWB(dc, TGA_REG_GMOR, 1); 1387 1388 while (lines--) { 1389 *rp = pixels; 1390 rp = (int32_t *)((char *)rp + ri->ri_stride); 1391 } 1392 1393 /* Set grapics mode back to normal. */ 1394 TGAWREG(dc, TGA_REG_GMOR, 0); 1395 } 1396 1397 1398 static void 1399 tga_ramdac_wr(v, btreg, val) 1400 void *v; 1401 u_int btreg; 1402 u_int8_t val; 1403 { 1404 struct tga_devconfig *dc = v; 1405 1406 if (btreg > BT485_REG_MAX) 1407 panic("tga_ramdac_wr: reg %d out of range", btreg); 1408 1409 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1410 TGAREGWB(dc, TGA_REG_EPDR, 1); 1411 } 1412 1413 static void 1414 tga2_ramdac_wr(v, btreg, val) 1415 void *v; 1416 u_int btreg; 1417 u_int8_t val; 1418 { 1419 struct tga_devconfig *dc = v; 1420 bus_space_handle_t ramdac; 1421 1422 if (btreg > BT485_REG_MAX) 1423 panic("tga_ramdac_wr: reg %d out of range", btreg); 1424 1425 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1426 (0xe << 12) + (btreg << 8), 4, &ramdac); 1427 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1428 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1429 } 1430 1431 static u_int8_t 1432 tga_bt463_rd(v, btreg) 1433 void *v; 1434 u_int btreg; 1435 { 1436 struct tga_devconfig *dc = v; 1437 tga_reg_t rdval; 1438 1439 /* 1440 * Strobe CE# (high->low->high) since status and data are latched on 1441 * the falling and rising edges (repsectively) of this active-low signal. 1442 */ 1443 1444 TGAREGWB(dc, TGA_REG_EPSR, 1); 1445 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1446 TGAREGWB(dc, TGA_REG_EPSR, 1); 1447 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1448 1449 TGAREGRB(dc, TGA_REG_EPSR, 1); 1450 1451 rdval = TGARREG(dc, TGA_REG_EPDR); 1452 TGAREGWB(dc, TGA_REG_EPSR, 1); 1453 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1454 1455 return (rdval >> 16) & 0xff; 1456 } 1457 1458 static void 1459 tga_bt463_wr(v, btreg, val) 1460 void *v; 1461 u_int btreg; 1462 u_int8_t val; 1463 { 1464 struct tga_devconfig *dc = v; 1465 1466 /* 1467 * In spite of the 21030 documentation, to set the MPU bus bits for 1468 * a write, you set them in the upper bits of EPDR, not EPSR. 1469 */ 1470 1471 /* 1472 * Strobe CE# (high->low->high) since status and data are latched on 1473 * the falling and rising edges of this active-low signal. 1474 */ 1475 1476 TGAREGWB(dc, TGA_REG_EPDR, 1); 1477 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1478 TGAREGWB(dc, TGA_REG_EPDR, 1); 1479 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1480 TGAREGWB(dc, TGA_REG_EPDR, 1); 1481 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1482 1483 } 1484 1485 static u_int8_t 1486 tga_ramdac_rd(v, btreg) 1487 void *v; 1488 u_int btreg; 1489 { 1490 struct tga_devconfig *dc = v; 1491 tga_reg_t rdval; 1492 1493 if (btreg > BT485_REG_MAX) 1494 panic("tga_ramdac_rd: reg %d out of range", btreg); 1495 1496 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1497 TGAREGWB(dc, TGA_REG_EPSR, 1); 1498 1499 rdval = TGARREG(dc, TGA_REG_EPDR); 1500 return (rdval >> 16) & 0xff; /* XXX */ 1501 } 1502 1503 static u_int8_t 1504 tga2_ramdac_rd(v, btreg) 1505 void *v; 1506 u_int btreg; 1507 { 1508 struct tga_devconfig *dc = v; 1509 bus_space_handle_t ramdac; 1510 u_int8_t retval; 1511 1512 if (btreg > BT485_REG_MAX) 1513 panic("tga_ramdac_rd: reg %d out of range", btreg); 1514 1515 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1516 (0xe << 12) + (btreg << 8), 4, &ramdac); 1517 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1518 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1519 return retval; 1520 } 1521 1522 #include <dev/ic/decmonitors.c> 1523 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1524 1525 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1526 1527 void 1528 tga2_init(dc) 1529 struct tga_devconfig *dc; 1530 { 1531 struct monitor *m = tga_getmonitor(dc); 1532 1533 /* Deal with the dot clocks. 1534 */ 1535 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1536 /* Set this up as a reference clock for the 1537 * ibm561's PLL. 1538 */ 1539 tga2_ics9110_wr(dc, 14300000); 1540 /* XXX Can't set up the dotclock properly, until such time 1541 * as the RAMDAC is configured. 1542 */ 1543 } else { 1544 /* otherwise the ics9110 is our clock. */ 1545 tga2_ics9110_wr(dc, m->dotclock); 1546 } 1547 #if 0 1548 TGAWREG(dc, TGA_REG_VHCR, 1549 ((m->hbp / 4) << 21) | 1550 ((m->hsync / 4) << 14) | 1551 (((m->hfp - 4) / 4) << 9) | 1552 ((m->cols + 4) / 4)); 1553 #else 1554 TGAWREG(dc, TGA_REG_VHCR, 1555 ((m->hbp / 4) << 21) | 1556 ((m->hsync / 4) << 14) | 1557 (((m->hfp) / 4) << 9) | 1558 ((m->cols) / 4)); 1559 #endif 1560 TGAWREG(dc, TGA_REG_VVCR, 1561 (m->vbp << 22) | 1562 (m->vsync << 16) | 1563 (m->vfp << 11) | 1564 (m->rows)); 1565 TGAWREG(dc, TGA_REG_VVBR, 1); 1566 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1567 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1568 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1569 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1570 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1571 } 1572 1573 void 1574 tga2_ics9110_wr(dc, dotclock) 1575 struct tga_devconfig *dc; 1576 int dotclock; 1577 { 1578 bus_space_handle_t clock; 1579 u_int32_t valU; 1580 int N, M, R, V, X; 1581 int i; 1582 1583 switch (dotclock) { 1584 case 130808000: 1585 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1586 case 119840000: 1587 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1588 case 108180000: 1589 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1590 case 103994000: 1591 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1592 case 175000000: 1593 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1594 case 75000000: 1595 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1596 case 74000000: 1597 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1598 case 69000000: 1599 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1600 case 65000000: 1601 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1602 case 50000000: 1603 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1604 case 40000000: 1605 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1606 case 31500000: 1607 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1608 case 25175000: 1609 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1610 case 135000000: 1611 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1612 case 110000000: 1613 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1614 case 202500000: 1615 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1616 case 14300000: /* this one is just a ref clock */ 1617 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1618 default: 1619 panic("unrecognized clock rate %d", dotclock); 1620 } 1621 1622 /* XXX -- hard coded, bad */ 1623 valU = N | ( M << 7 ) | (V << 14); 1624 valU |= (X << 15) | (R << 17); 1625 valU |= 0x17 << 19; 1626 1627 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1628 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1629 1630 for (i=24; i>0; i--) { 1631 u_int32_t writeval; 1632 1633 writeval = valU & 0x1; 1634 if (i == 1) 1635 writeval |= 0x2; 1636 valU >>= 1; 1637 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1638 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1639 } 1640 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1641 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1642 &clock); /* XXX */ 1643 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1644 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1645 } 1646 1647 struct monitor * 1648 tga_getmonitor(dc) 1649 struct tga_devconfig *dc; 1650 { 1651 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1652 } 1653 1654 unsigned 1655 tga_getdotclock(dc) 1656 struct tga_devconfig *dc; 1657 { 1658 return tga_getmonitor(dc)->dotclock; 1659 } 1660