1 /* $NetBSD: tga.c,v 1.35 2001/08/05 18:07:54 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/ioctl.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/tgareg.h> 46 #include <dev/pci/tgavar.h> 47 #include <dev/ic/bt485reg.h> 48 #include <dev/ic/bt485var.h> 49 #include <dev/ic/bt463reg.h> 50 #include <dev/ic/bt463var.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wscons_raster.h> 54 #include <dev/rasops/rasops.h> 55 #include <dev/wsfont/wsfont.h> 56 #include <uvm/uvm_extern.h> 57 58 #ifdef __alpha__ 59 #include <machine/pte.h> 60 #endif 61 #ifdef __mips__ 62 #include <mips/pte.h> 63 #endif 64 65 int tgamatch __P((struct device *, struct cfdata *, void *)); 66 void tgaattach __P((struct device *, struct device *, void *)); 67 int tgaprint __P((void *, const char *)); 68 69 struct cfattach tga_ca = { 70 sizeof(struct tga_softc), tgamatch, tgaattach, 71 }; 72 73 int tga_identify __P((struct tga_devconfig *)); 74 const struct tga_conf *tga_getconf __P((int)); 75 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 76 pcitag_t tag, struct tga_devconfig *dc)); 77 78 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 79 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 80 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 81 82 struct tga_devconfig tga_console_dc; 83 84 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 85 paddr_t tga_mmap __P((void *, off_t, int)); 86 static void tga_copyrows __P((void *, int, int, int)); 87 static void tga_copycols __P((void *, int, int, int, int)); 88 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 89 void **, int *, int *, long *)); 90 static void tga_free_screen __P((void *, void *)); 91 static int tga_show_screen __P((void *, void *, int, 92 void (*) (void *, int, int), void *)); 93 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 94 struct rasops_info *, int, int)); 95 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 96 int, struct rasops_info *, int, int )); 97 static void tga_putchar __P((void *c, int row, int col, 98 u_int uc, long attr)); 99 static void tga_eraserows __P((void *, int, int, long)); 100 static void tga_erasecols __P((void *, int, int, int, long)); 101 void tga2_init __P((struct tga_devconfig *, int)); 102 103 static void tga_config_interrupts __P((struct device *)); 104 105 /* RAMDAC interface functions */ 106 static int tga_sched_update __P((void *, void (*)(void *))); 107 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 108 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 109 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 110 static u_int8_t tga_bt463_rd __P((void *, u_int)); 111 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 112 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 113 114 /* Interrupt handler */ 115 static int tga_intr __P((void *)); 116 117 /* The NULL entries will get filled in by rasops_init(). 118 * XXX and the non-NULL ones will be overwritten; reset after calling it. 119 */ 120 struct wsdisplay_emulops tga_emulops = { 121 NULL, 122 NULL, 123 tga_putchar, 124 tga_copycols, 125 tga_erasecols, 126 tga_copyrows, 127 tga_eraserows, 128 NULL, 129 }; 130 131 struct wsscreen_descr tga_stdscreen = { 132 "std", 133 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 134 &tga_emulops, 135 0, 0, 136 WSSCREEN_REVERSE 137 }; 138 139 const struct wsscreen_descr *_tga_scrlist[] = { 140 &tga_stdscreen, 141 /* XXX other formats, graphics screen? */ 142 }; 143 144 struct wsscreen_list tga_screenlist = { 145 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 146 }; 147 148 struct wsdisplay_accessops tga_accessops = { 149 tga_ioctl, 150 tga_mmap, 151 tga_alloc_screen, 152 tga_free_screen, 153 tga_show_screen, 154 0 /* load_font */ 155 }; 156 157 static void tga_blank __P((struct tga_devconfig *)); 158 static void tga_unblank __P((struct tga_devconfig *)); 159 160 int 161 tga_cnmatch(iot, memt, pc, tag) 162 bus_space_tag_t iot, memt; 163 pci_chipset_tag_t pc; 164 pcitag_t tag; 165 { 166 return tga_matchcommon(memt, pc, tag); 167 } 168 169 int 170 tgamatch(parent, match, aux) 171 struct device *parent; 172 struct cfdata *match; 173 void *aux; 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 178 return (0); 179 180 switch (PCI_PRODUCT(pa->pa_id)) { 181 case PCI_PRODUCT_DEC_21030: 182 case PCI_PRODUCT_DEC_PBXGB: 183 break; 184 default: 185 return 0; 186 } 187 188 /* short-circuit the following test, as we 189 * already have the memory mapped and hence 190 * cannot perform it---and we are the console 191 * anyway. 192 */ 193 if (pa->pa_tag == tga_console_dc.dc_pcitag) 194 return 10; 195 196 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 197 } 198 199 static int 200 tga_matchcommon(memt, pc, tag) 201 bus_space_tag_t memt; 202 pci_chipset_tag_t pc; 203 pcitag_t tag; 204 { 205 struct tga_devconfig tmp_dc; 206 struct tga_devconfig *dc = &tmp_dc; 207 bus_size_t pcisize; 208 209 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 210 dc->dc_tga_type = tga_identify(dc); 211 212 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 213 bus_space_unmap(memt, dc->dc_memh, pcisize); 214 if (dc->dc_tgaconf) 215 return 10; 216 return 0; 217 } 218 219 static void 220 tga_mapaddrs(memt, pc, tag, pcisize, dc) 221 bus_space_tag_t memt; 222 pci_chipset_tag_t pc; 223 pcitag_t tag; 224 bus_size_t *pcisize; 225 struct tga_devconfig *dc; 226 { 227 int flags; 228 229 dc->dc_memt = memt; 230 dc->dc_tgaconf = NULL; 231 232 /* XXX magic number */ 233 if (pci_mapreg_info(pc, tag, 0x10, 234 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 235 &dc->dc_pcipaddr, pcisize, &flags)) 236 panic("tga_mapaddrs: pci_mapreg_info() failed"); 237 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 238 panic("tga memory not prefetchable"); 239 240 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 241 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 242 panic("tga_mapaddrs: could not map TGA address space"); 243 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 244 #ifdef __alpha__ 245 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 246 #endif 247 #ifdef arc 248 bus_space_paddr(memt, dc->dc_memh, &dc->dc_paddr); 249 #endif 250 251 bus_space_subregion(dc->dc_memt, dc->dc_memh, 252 TGA_MEM_CREGS, TGA_CREGS_SIZE, 253 &dc->dc_regs); 254 } 255 256 static void 257 tga_init(memt, pc, tag, dc) 258 bus_space_tag_t memt; 259 pci_chipset_tag_t pc; 260 pcitag_t tag; 261 struct tga_devconfig *dc; 262 { 263 const struct tga_conf *tgac; 264 struct rasops_info *rip; 265 int cookie; 266 bus_size_t pcisize; 267 int i; 268 269 dc->dc_pcitag = tag; 270 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 271 dc->dc_tga_type = tga_identify(dc); 272 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 273 #if 0 274 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 275 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 276 panic("tga_init: memory size mismatch?"); 277 #endif 278 279 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 280 case 0x01: 281 case 0x02: 282 case 0x03: 283 case 0x04: 284 dc->dc_tga2 = 0; 285 break; 286 case 0x20: 287 case 0x21: 288 case 0x22: 289 dc->dc_tga2 = 1; 290 break; 291 default: 292 panic("tga_init: TGA Revision not recognized"); 293 } 294 295 if (dc->dc_tga2) { 296 int monitor; 297 298 monitor = (~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f; 299 tga2_init(dc, monitor); 300 } 301 302 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 303 case 0: 304 dc->dc_wid = 8192; 305 break; 306 307 case 1: 308 dc->dc_wid = 8196; 309 break; 310 311 default: 312 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 313 break; 314 } 315 316 /* 317 * XXX XXX Turning off "odd" shouldn't be necessary, 318 * XXX XXX but I can't make X work with the weird size. 319 */ 320 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 321 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 322 TGAWREG(dc, TGA_REG_VHCR, 323 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 324 dc->dc_wid -= 4; 325 } 326 327 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 328 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 329 330 /* XXX this seems to be what DEC does */ 331 TGAWREG(dc, TGA_REG_CCBR, 0); 332 TGAWREG(dc, TGA_REG_VVBR, 1); 333 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 334 1 * tgac->tgac_vvbr_units; 335 dc->dc_blanked = 1; 336 tga_unblank(dc); 337 338 /* 339 * Set all bits in the pixel mask, to enable writes to all pixels. 340 * It seems that the console firmware clears some of them 341 * under some circumstances, which causes cute vertical stripes. 342 */ 343 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 344 345 /* clear the screen */ 346 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 347 *(u_int32_t *)(dc->dc_videobase + i) = 0; 348 349 /* Initialize rasops descriptor */ 350 rip = &dc->dc_rinfo; 351 rip->ri_flg = RI_CENTER; 352 rip->ri_depth = tgac->tgac_phys_depth; 353 rip->ri_bits = (void *)dc->dc_videobase; 354 rip->ri_width = dc->dc_wid; 355 rip->ri_height = dc->dc_ht; 356 rip->ri_stride = dc->dc_rowbytes; 357 rip->ri_hw = dc; 358 359 if (tgac->tgac_phys_depth == 32) { 360 rip->ri_rnum = 8; 361 rip->ri_gnum = 8; 362 rip->ri_bnum = 8; 363 rip->ri_rpos = 16; 364 rip->ri_gpos = 8; 365 rip->ri_bpos = 0; 366 } 367 368 wsfont_init(); 369 /* prefer 8 pixel wide font */ 370 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0) 371 cookie = wsfont_find(NULL, 0, 0, 0); 372 if (cookie <= 0) { 373 printf("tga: no appropriate fonts.\n"); 374 return; 375 } 376 377 /* the accelerated tga_putchar() needs LSbit left */ 378 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font, 379 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 380 printf("tga: couldn't lock font\n"); 381 return; 382 } 383 dc->dc_rinfo.ri_wsfcookie = cookie; 384 385 rasops_init(rip, 34, 80); 386 387 /* add our accelerated functions */ 388 /* XXX shouldn't have to do this; rasops should leave non-NULL 389 * XXX entries alone. 390 */ 391 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 392 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 393 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 394 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 395 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 396 397 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 398 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 399 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 400 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 401 402 403 dc->dc_intrenabled = 0; 404 } 405 406 void 407 tgaattach(parent, self, aux) 408 struct device *parent, *self; 409 void *aux; 410 { 411 struct pci_attach_args *pa = aux; 412 struct tga_softc *sc = (struct tga_softc *)self; 413 struct wsemuldisplaydev_attach_args aa; 414 pci_intr_handle_t intrh; 415 const char *intrstr; 416 u_int8_t rev; 417 int console; 418 419 #if defined(__alpha__) || defined(arc) 420 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 421 #else 422 console = 0; 423 #endif 424 if (console) { 425 sc->sc_dc = &tga_console_dc; 426 sc->nscreens = 1; 427 } else { 428 sc->sc_dc = (struct tga_devconfig *) 429 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK); 430 memset(sc->sc_dc, 0, sizeof(struct tga_devconfig)); 431 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 432 } 433 if (sc->sc_dc->dc_vaddr == NULL) { 434 printf(": couldn't map memory space; punt!\n"); 435 return; 436 } 437 438 /* XXX say what's going on. */ 439 intrstr = NULL; 440 if (pci_intr_map(pa, &intrh)) { 441 printf(": couldn't map interrupt"); 442 return; 443 } 444 intrstr = pci_intr_string(pa->pa_pc, intrh); 445 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 446 sc->sc_dc); 447 if (sc->sc_intr == NULL) { 448 printf(": couldn't establish interrupt"); 449 if (intrstr != NULL) 450 printf("at %s", intrstr); 451 printf("\n"); 452 return; 453 } 454 455 rev = PCI_REVISION(pa->pa_class); 456 switch (rev) { 457 case 0x1: 458 case 0x2: 459 case 0x3: 460 printf(": DC21030 step %c", 'A' + rev - 1); 461 break; 462 case 0x20: 463 printf(": TGA2 abstract software model"); 464 break; 465 case 0x21: 466 case 0x22: 467 printf(": TGA2 pass %d", rev - 0x20); 468 break; 469 470 default: 471 printf("unknown stepping (0x%x)", rev); 472 break; 473 } 474 printf(", "); 475 476 /* 477 * Get RAMDAC function vectors and call the RAMDAC functions 478 * to allocate its private storage and pass that back to us. 479 */ 480 481 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 482 if (!sc->sc_dc->dc_tga2) { 483 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 484 sc->sc_dc->dc_ramdac_cookie = 485 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 486 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 487 else 488 sc->sc_dc->dc_ramdac_cookie = 489 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 490 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 491 } else { 492 sc->sc_dc->dc_ramdac_cookie = 493 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 494 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 495 } 496 497 /* 498 * Initialize the RAMDAC. Initialization includes disabling 499 * cursor, setting a sane colormap, etc. 500 */ 501 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 502 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 503 504 if (sc->sc_dc->dc_tgaconf == NULL) { 505 printf("unknown board configuration\n"); 506 return; 507 } 508 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 509 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 510 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 511 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 512 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 513 514 if (intrstr != NULL) 515 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 516 intrstr); 517 518 aa.console = console; 519 aa.scrdata = &tga_screenlist; 520 aa.accessops = &tga_accessops; 521 aa.accesscookie = sc; 522 523 config_found(self, &aa, wsemuldisplaydevprint); 524 525 config_interrupts(self, tga_config_interrupts); 526 } 527 528 static void 529 tga_config_interrupts (d) 530 struct device *d; 531 { 532 struct tga_softc *sc = (struct tga_softc *)d; 533 sc->sc_dc->dc_intrenabled = 1; 534 } 535 536 int 537 tga_ioctl(v, cmd, data, flag, p) 538 void *v; 539 u_long cmd; 540 caddr_t data; 541 int flag; 542 struct proc *p; 543 { 544 struct tga_softc *sc = v; 545 struct tga_devconfig *dc = sc->sc_dc; 546 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 547 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 548 549 switch (cmd) { 550 case WSDISPLAYIO_GTYPE: 551 *(u_int *)data = WSDISPLAY_TYPE_TGA; 552 return (0); 553 554 case WSDISPLAYIO_GINFO: 555 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 556 wsd_fbip->height = sc->sc_dc->dc_ht; 557 wsd_fbip->width = sc->sc_dc->dc_wid; 558 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 559 wsd_fbip->cmsize = 256; /* XXX ??? */ 560 #undef wsd_fbip 561 return (0); 562 563 case WSDISPLAYIO_GETCMAP: 564 return (*dcrf->ramdac_get_cmap)(dcrc, 565 (struct wsdisplay_cmap *)data); 566 567 case WSDISPLAYIO_PUTCMAP: 568 return (*dcrf->ramdac_set_cmap)(dcrc, 569 (struct wsdisplay_cmap *)data); 570 571 case WSDISPLAYIO_SVIDEO: 572 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 573 tga_blank(sc->sc_dc); 574 else 575 tga_unblank(sc->sc_dc); 576 return (0); 577 578 case WSDISPLAYIO_GVIDEO: 579 *(u_int *)data = dc->dc_blanked ? 580 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 581 return (0); 582 583 case WSDISPLAYIO_GCURPOS: 584 return (*dcrf->ramdac_get_curpos)(dcrc, 585 (struct wsdisplay_curpos *)data); 586 587 case WSDISPLAYIO_SCURPOS: 588 return (*dcrf->ramdac_set_curpos)(dcrc, 589 (struct wsdisplay_curpos *)data); 590 591 case WSDISPLAYIO_GCURMAX: 592 return (*dcrf->ramdac_get_curmax)(dcrc, 593 (struct wsdisplay_curpos *)data); 594 595 case WSDISPLAYIO_GCURSOR: 596 return (*dcrf->ramdac_get_cursor)(dcrc, 597 (struct wsdisplay_cursor *)data); 598 599 case WSDISPLAYIO_SCURSOR: 600 return (*dcrf->ramdac_set_cursor)(dcrc, 601 (struct wsdisplay_cursor *)data); 602 } 603 return (-1); 604 } 605 606 static int 607 tga_sched_update(v, f) 608 void *v; 609 void (*f) __P((void *)); 610 { 611 struct tga_devconfig *dc = v; 612 613 if (dc->dc_intrenabled) { 614 /* Arrange for f to be called at the next end-of-frame interrupt */ 615 dc->dc_ramdac_intr = f; 616 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 617 } else { 618 /* Spin until the end-of-frame, then call f */ 619 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 620 TGAREGWB(dc, TGA_REG_SISR, 1); 621 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 622 ; 623 f(dc->dc_ramdac_cookie); 624 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 625 TGAREGWB(dc, TGA_REG_SISR, 1); 626 } 627 628 return 0; 629 } 630 631 static int 632 tga_intr(v) 633 void *v; 634 { 635 struct tga_devconfig *dc = v; 636 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 637 638 u_int32_t reg; 639 640 reg = TGARREG(dc, TGA_REG_SISR); 641 if (( reg & 0x00010001) != 0x00010001) { 642 /* Odd. We never set any of the other interrupt enables. */ 643 if ((reg & 0x1f) != 0) { 644 /* Clear the mysterious pending interrupts. */ 645 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 646 TGAREGWB(dc, TGA_REG_SISR, 1); 647 /* This was our interrupt, even if we're puzzled as to why 648 * we got it. Don't make the interrupt handler think it 649 * was a stray. 650 */ 651 return -1; 652 } else { 653 return 0; 654 } 655 } 656 /* if we have something to do, do it */ 657 if (dc->dc_ramdac_intr) { 658 dc->dc_ramdac_intr(dcrc); 659 dc->dc_ramdac_intr = NULL; 660 } 661 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 662 TGAREGWB(dc, TGA_REG_SISR, 1); 663 return (1); 664 } 665 666 paddr_t 667 tga_mmap(v, offset, prot) 668 void *v; 669 off_t offset; 670 int prot; 671 { 672 673 /* XXX NEW MAPPING CODE... */ 674 675 #if defined(__alpha__) 676 struct tga_softc *sc = v; 677 678 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 679 return -1; 680 return alpha_btop(sc->sc_dc->dc_paddr + offset); 681 #elif defined(__mips__) 682 struct tga_softc *sc = v; 683 684 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 685 return -1; 686 return mips_btop(sc->sc_dc->dc_paddr + offset); 687 #else 688 return (-1); 689 #endif 690 } 691 692 static int 693 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 694 void *v; 695 const struct wsscreen_descr *type; 696 void **cookiep; 697 int *curxp, *curyp; 698 long *attrp; 699 { 700 struct tga_softc *sc = v; 701 long defattr; 702 703 if (sc->nscreens > 0) 704 return (ENOMEM); 705 706 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 707 *curxp = 0; 708 *curyp = 0; 709 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 710 0, 0, 0, &defattr); 711 *attrp = defattr; 712 sc->nscreens++; 713 return (0); 714 } 715 716 static void 717 tga_free_screen(v, cookie) 718 void *v; 719 void *cookie; 720 { 721 struct tga_softc *sc = v; 722 723 if (sc->sc_dc == &tga_console_dc) 724 panic("tga_free_screen: console"); 725 726 sc->nscreens--; 727 } 728 729 static int 730 tga_show_screen(v, cookie, waitok, cb, cbarg) 731 void *v; 732 void *cookie; 733 int waitok; 734 void (*cb) __P((void *, int, int)); 735 void *cbarg; 736 { 737 738 return (0); 739 } 740 741 int 742 tga_cnattach(iot, memt, pc, bus, device, function) 743 bus_space_tag_t iot, memt; 744 pci_chipset_tag_t pc; 745 int bus, device, function; 746 { 747 struct tga_devconfig *dcp = &tga_console_dc; 748 long defattr; 749 750 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 751 752 /* sanity checks */ 753 if (dcp->dc_vaddr == NULL) 754 panic("tga_console(%d, %d): couldn't map memory space", 755 device, function); 756 if (dcp->dc_tgaconf == NULL) 757 panic("tga_console(%d, %d): unknown board configuration", 758 device, function); 759 760 /* 761 * Initialize the RAMDAC but DO NOT allocate any private storage. 762 * Initialization includes disabling cursor, setting a sane 763 * colormap, etc. It will be reinitialized in tgaattach(). 764 */ 765 if (dcp->dc_tga2) 766 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 767 tga2_ramdac_rd); 768 else { 769 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 770 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 771 tga_ramdac_rd); 772 else { 773 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 774 tga_bt463_rd); 775 } 776 } 777 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 778 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 779 780 return(0); 781 } 782 783 /* 784 * Functions to blank and unblank the display. 785 */ 786 static void 787 tga_blank(dc) 788 struct tga_devconfig *dc; 789 { 790 791 if (!dc->dc_blanked) { 792 dc->dc_blanked = 1; 793 /* XXX */ 794 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 795 } 796 } 797 798 static void 799 tga_unblank(dc) 800 struct tga_devconfig *dc; 801 { 802 803 if (dc->dc_blanked) { 804 dc->dc_blanked = 0; 805 /* XXX */ 806 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 807 } 808 } 809 810 /* 811 * Functions to manipulate the built-in cursor handing hardware. 812 */ 813 int 814 tga_builtin_set_cursor(dc, cursorp) 815 struct tga_devconfig *dc; 816 struct wsdisplay_cursor *cursorp; 817 { 818 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 819 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 820 u_int count, v; 821 int error; 822 823 v = cursorp->which; 824 if (v & WSDISPLAY_CURSOR_DOCMAP) { 825 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 826 if (error) 827 return (error); 828 } 829 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 830 if ((u_int)cursorp->size.x != 64 || 831 (u_int)cursorp->size.y > 64) 832 return (EINVAL); 833 /* The cursor is 2 bits deep, and there is no mask */ 834 count = (cursorp->size.y * 64 * 2) / NBBY; 835 if (!uvm_useracc(cursorp->image, count, B_READ)) 836 return (EFAULT); 837 } 838 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 839 return EINVAL; 840 841 /* parameters are OK; do it */ 842 if (v & WSDISPLAY_CURSOR_DOCUR) { 843 if (cursorp->enable) 844 /* XXX */ 845 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 846 else 847 /* XXX */ 848 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 849 } 850 if (v & WSDISPLAY_CURSOR_DOPOS) { 851 TGAWREG(dc, TGA_REG_CXYR, 852 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 853 } 854 if (v & WSDISPLAY_CURSOR_DOCMAP) { 855 /* can't fail. */ 856 dcrf->ramdac_set_curcmap(dcrc, cursorp); 857 } 858 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 859 count = ((64 * 2) / NBBY) * cursorp->size.y; 860 TGAWREG(dc, TGA_REG_CCBR, 861 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 862 copyin(cursorp->image, (char *)(dc->dc_vaddr + 863 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 864 count); /* can't fail. */ 865 } 866 return (0); 867 } 868 869 int 870 tga_builtin_get_cursor(dc, cursorp) 871 struct tga_devconfig *dc; 872 struct wsdisplay_cursor *cursorp; 873 { 874 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 875 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 876 int count, error; 877 878 cursorp->which = WSDISPLAY_CURSOR_DOALL & 879 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 880 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 881 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 882 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 883 cursorp->size.x = 64; 884 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 885 886 if (cursorp->image != NULL) { 887 count = (cursorp->size.y * 64 * 2) / NBBY; 888 error = copyout((char *)(dc->dc_vaddr + 889 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 890 cursorp->image, count); 891 if (error) 892 return (error); 893 /* No mask */ 894 } 895 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 896 return (error); 897 } 898 899 int 900 tga_builtin_set_curpos(dc, curposp) 901 struct tga_devconfig *dc; 902 struct wsdisplay_curpos *curposp; 903 { 904 905 TGAWREG(dc, TGA_REG_CXYR, 906 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 907 return (0); 908 } 909 910 int 911 tga_builtin_get_curpos(dc, curposp) 912 struct tga_devconfig *dc; 913 struct wsdisplay_curpos *curposp; 914 { 915 916 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 917 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 918 return (0); 919 } 920 921 int 922 tga_builtin_get_curmax(dc, curposp) 923 struct tga_devconfig *dc; 924 struct wsdisplay_curpos *curposp; 925 { 926 927 curposp->x = curposp->y = 64; 928 return (0); 929 } 930 931 /* 932 * Copy columns (characters) in a row (line). 933 */ 934 static void 935 tga_copycols(id, row, srccol, dstcol, ncols) 936 void *id; 937 int row, srccol, dstcol, ncols; 938 { 939 struct rasops_info *ri = id; 940 int y, srcx, dstx, nx; 941 942 y = ri->ri_font->fontheight * row; 943 srcx = ri->ri_font->fontwidth * srccol; 944 dstx = ri->ri_font->fontwidth * dstcol; 945 nx = ri->ri_font->fontwidth * ncols; 946 947 tga_rop(ri, dstx, y, 948 nx, ri->ri_font->fontheight, RAS_SRC, 949 ri, srcx, y); 950 } 951 952 /* 953 * Copy rows (lines). 954 */ 955 static void 956 tga_copyrows(id, srcrow, dstrow, nrows) 957 void *id; 958 int srcrow, dstrow, nrows; 959 { 960 struct rasops_info *ri = id; 961 int srcy, dsty, ny; 962 963 srcy = ri->ri_font->fontheight * srcrow; 964 dsty = ri->ri_font->fontheight * dstrow; 965 ny = ri->ri_font->fontheight * nrows; 966 967 tga_rop(ri, 0, dsty, 968 ri->ri_emuwidth, ny, RAS_SRC, 969 ri, 0, srcy); 970 } 971 972 /* Do we need the src? */ 973 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 974 975 /* A mapping between our API and the TGA card */ 976 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 977 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 978 }; 979 980 /* 981 * Generic TGA raster op. 982 * This covers all possible raster ops, and 983 * clips the sizes and all of that. 984 */ 985 static int 986 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 987 struct rasops_info *dst; 988 int dx, dy, w, h, rop; 989 struct rasops_info *src; 990 int sx, sy; 991 { 992 if (!dst) 993 return -1; 994 if (needsrc[RAS_GETOP(rop)]) { 995 if (src == NULL) 996 return -1; /* We want a src */ 997 /* Clip against src */ 998 if (sx < 0) { 999 w += sx; 1000 sx = 0; 1001 } 1002 if (sy < 0) { 1003 h += sy; 1004 sy = 0; 1005 } 1006 if (sx + w > src->ri_emuwidth) 1007 w = src->ri_emuwidth - sx; 1008 if (sy + h > src->ri_emuheight) 1009 h = src->ri_emuheight - sy; 1010 } else { 1011 if (src != NULL) 1012 return -1; /* We need no src */ 1013 } 1014 /* Clip against dst. We modify src regardless of using it, 1015 * since it really doesn't matter. 1016 */ 1017 if (dx < 0) { 1018 w += dx; 1019 sx -= dx; 1020 dx = 0; 1021 } 1022 if (dy < 0) { 1023 h += dy; 1024 sy -= dy; 1025 dy = 0; 1026 } 1027 if (dx + w > dst->ri_emuwidth) 1028 w = dst->ri_emuwidth - dx; 1029 if (dy + h > dst->ri_emuheight) 1030 h = dst->ri_emuheight - dy; 1031 if (w <= 0 || h <= 0) 1032 return 0; /* Vacuously true; */ 1033 if (!src) { 1034 /* XXX Punt! */ 1035 return -1; 1036 } 1037 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1038 } 1039 1040 1041 1042 /* 1043 * Video to Video raster ops. 1044 * This function deals with all raster ops that have a src and dst 1045 * that are on the card. 1046 */ 1047 static int 1048 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1049 struct rasops_info *dst; 1050 int dx, dy, w, h, rop; 1051 struct rasops_info *src; 1052 int sx, sy; 1053 { 1054 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1055 int srcb, dstb, tga_srcb, tga_dstb; 1056 int x, y, wb; 1057 int xstart, xend, xdir; 1058 int ystart, yend, ydir, yinc; 1059 int xleft, lastx, lastleft; 1060 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1061 1062 /* 1063 * I don't yet want to deal with unaligned guys, really. And we don't 1064 * deal with copies from one card to another. 1065 */ 1066 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1067 /* XXX Punt! */ 1068 /* XXX should never happen, since it's only being used to 1069 * XXX copy 8-pixel-wide characters. 1070 */ 1071 return -1; 1072 } 1073 1074 wb = w * (dst->ri_depth / 8); 1075 if (sy >= dy) { 1076 ystart = 0; 1077 yend = h; 1078 ydir = 1; 1079 } else { 1080 ystart = h; 1081 yend = 0; 1082 ydir = -1; 1083 } 1084 if (sx >= dx) { /* moving to the left */ 1085 xstart = 0; 1086 xend = w * (dst->ri_depth / 8) - 4; 1087 xdir = 1; 1088 } else { /* moving to the right */ 1089 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 ); 1090 xend = 0; 1091 xdir = -1; 1092 } 1093 #define XINC4 4 1094 #define XINC64 64 1095 #define XINC256 (64*4) 1096 yinc = ydir * dst->ri_stride; 1097 ystart *= dst->ri_stride; 1098 yend *= dst->ri_stride; 1099 1100 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1101 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1102 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1103 (sx + src->ri_xorigin) * (src->ri_depth/8); 1104 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1105 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1106 1107 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1108 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1109 1110 /* 1111 * we have 3 sizes of pixels to move in X direction: 1112 * 4 * 64 (unrolled TGA ops) 1113 * 64 (single TGA op) 1114 * 4 (CPU, using long word) 1115 */ 1116 1117 if (xdir == 1) { /* move to the left */ 1118 1119 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1120 1121 /* 4*64 byte chunks */ 1122 for (xleft = wb, x = xstart; 1123 x <= xend && xleft >= 4*64; 1124 x += XINC256, xleft -= XINC256) { 1125 1126 /* XXX XXX Eight writes to different addresses should fill 1127 * XXX XXX up the write buffers on 21064 and 21164 chips, 1128 * XXX XXX but later CPUs might have larger write buffers which 1129 * XXX XXX require further unrolling of this loop, or the 1130 * XXX XXX insertion of memory barriers. 1131 */ 1132 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1133 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1134 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1135 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1136 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1137 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1138 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1139 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1140 } 1141 1142 /* 64 byte chunks */ 1143 for ( ; x <= xend && xleft >= 64; 1144 x += XINC64, xleft -= XINC64) { 1145 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1146 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1147 } 1148 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1149 1150 } 1151 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1152 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1153 1154 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1155 /* 4 byte granularity */ 1156 for (x = lastx, xleft = lastleft; 1157 x <= xend && xleft >= 4; 1158 x += XINC4, xleft -= XINC4) { 1159 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1160 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1161 } 1162 } 1163 } 1164 else { /* above move to the left, below move to the right */ 1165 1166 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1167 1168 /* 4*64 byte chunks */ 1169 for (xleft = wb, x = xstart; 1170 x >= xend && xleft >= 4*64; 1171 x -= XINC256, xleft -= XINC256) { 1172 1173 /* XXX XXX Eight writes to different addresses should fill 1174 * XXX XXX up the write buffers on 21064 and 21164 chips, 1175 * XXX XXX but later CPUs might have larger write buffers which 1176 * XXX XXX require further unrolling of this loop, or the 1177 * XXX XXX insertion of memory barriers. 1178 */ 1179 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64); 1180 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64); 1181 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64); 1182 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64); 1183 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64); 1184 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64); 1185 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64); 1186 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64); 1187 } 1188 1189 if (xleft) x += XINC256 - XINC64; 1190 1191 /* 64 byte chunks */ 1192 for ( ; x >= xend && xleft >= 64; 1193 x -= XINC64, xleft -= XINC64) { 1194 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1195 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1196 } 1197 if (xleft) x += XINC64 - XINC4; 1198 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1199 } 1200 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1201 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1202 1203 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1204 /* 4 byte granularity */ 1205 for (x = lastx, xleft = lastleft; 1206 x >= xend && xleft >= 4; 1207 x -= XINC4, xleft -= XINC4) { 1208 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1209 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1210 } 1211 } 1212 } 1213 return 0; 1214 } 1215 1216 1217 void tga_putchar (c, row, col, uc, attr) 1218 void *c; 1219 int row, col; 1220 u_int uc; 1221 long attr; 1222 { 1223 struct rasops_info *ri = c; 1224 struct tga_devconfig *dc = ri->ri_hw; 1225 int fs, height, width; 1226 u_char *fr; 1227 int32_t *rp; 1228 1229 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1230 1231 height = ri->ri_font->fontheight; 1232 width = ri->ri_font->fontwidth; 1233 1234 uc -= ri->ri_font->firstchar; 1235 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1236 fs = ri->ri_font->stride; 1237 1238 /* Set foreground and background color. XXX memoize this somehow? 1239 * The rasops code has already expanded the color entry to 32 bits 1240 * for us, even for 8-bit displays, so we don't have to do anything. 1241 */ 1242 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1243 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1244 1245 /* Set raster operation to "copy"... */ 1246 if (ri->ri_depth == 8) 1247 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1248 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1249 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1250 1251 /* Set which pixels we're drawing (of a possible 32). */ 1252 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1253 1254 /* Set drawing mode to opaque stipple. */ 1255 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1256 1257 /* Insert write barrier before actually sending data */ 1258 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1259 TGAREGWB(dc, TGA_REG_GMOR, 1); 1260 1261 while(height--) { 1262 /* The actual stipple write */ 1263 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1264 1265 fr += fs; 1266 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1267 } 1268 1269 /* Do underline */ 1270 if ((attr & 1) != 0) { 1271 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1272 *rp = 0xffffffff; 1273 } 1274 1275 /* Set grapics mode back to normal. */ 1276 TGAWREG(dc, TGA_REG_GMOR, 0); 1277 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1278 1279 } 1280 1281 static void 1282 tga_eraserows(c, row, num, attr) 1283 void *c; 1284 int row, num; 1285 long attr; 1286 { 1287 struct rasops_info *ri = c; 1288 struct tga_devconfig *dc = ri->ri_hw; 1289 int32_t color, lines, pixels; 1290 int32_t *rp; 1291 1292 color = ri->ri_devcmap[(attr >> 16) & 15]; 1293 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1294 lines = num * ri->ri_font->fontheight; 1295 pixels = ri->ri_emuwidth - 1; 1296 1297 /* Set fill color in block-color registers */ 1298 TGAWREG(dc, TGA_REG_GBCR0, color); 1299 TGAWREG(dc, TGA_REG_GBCR1, color); 1300 if (ri->ri_depth != 8) { 1301 TGAWREG(dc, TGA_REG_GBCR2, color); 1302 TGAWREG(dc, TGA_REG_GBCR3, color); 1303 TGAWREG(dc, TGA_REG_GBCR4, color); 1304 TGAWREG(dc, TGA_REG_GBCR5, color); 1305 TGAWREG(dc, TGA_REG_GBCR6, color); 1306 TGAWREG(dc, TGA_REG_GBCR7, color); 1307 } 1308 1309 /* Set raster operation to "copy"... */ 1310 if (ri->ri_depth == 8) 1311 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1312 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1313 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1314 1315 /* Set which pixels we're drawing (of a possible 32). */ 1316 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1317 1318 /* Set drawing mode to block fill. */ 1319 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1320 1321 /* Insert write barrier before actually sending data */ 1322 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1323 TGAREGWB(dc, TGA_REG_GMOR, 1); 1324 1325 while (lines--) { 1326 *rp = pixels; 1327 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1328 } 1329 1330 /* Set grapics mode back to normal. */ 1331 TGAWREG(dc, TGA_REG_GMOR, 0); 1332 1333 } 1334 1335 static void 1336 tga_erasecols (c, row, col, num, attr) 1337 void *c; 1338 int row, col, num; 1339 long attr; 1340 { 1341 struct rasops_info *ri = c; 1342 struct tga_devconfig *dc = ri->ri_hw; 1343 int32_t color, lines, pixels; 1344 int32_t *rp; 1345 1346 color = ri->ri_devcmap[(attr >> 16) & 15]; 1347 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1348 lines = ri->ri_font->fontheight; 1349 pixels = (num * ri->ri_font->fontwidth) - 1; 1350 1351 /* Set fill color in block-color registers */ 1352 TGAWREG(dc, TGA_REG_GBCR0, color); 1353 TGAWREG(dc, TGA_REG_GBCR1, color); 1354 if (ri->ri_depth != 8) { 1355 TGAWREG(dc, TGA_REG_GBCR2, color); 1356 TGAWREG(dc, TGA_REG_GBCR3, color); 1357 TGAWREG(dc, TGA_REG_GBCR4, color); 1358 TGAWREG(dc, TGA_REG_GBCR5, color); 1359 TGAWREG(dc, TGA_REG_GBCR6, color); 1360 TGAWREG(dc, TGA_REG_GBCR7, color); 1361 } 1362 1363 /* Set raster operation to "copy"... */ 1364 if (ri->ri_depth == 8) 1365 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1366 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1367 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1368 1369 /* Set which pixels we're drawing (of a possible 32). */ 1370 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1371 1372 /* Set drawing mode to block fill. */ 1373 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1374 1375 /* Insert write barrier before actually sending data */ 1376 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1377 TGAREGWB(dc, TGA_REG_GMOR, 1); 1378 1379 while (lines--) { 1380 *rp = pixels; 1381 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1382 } 1383 1384 /* Set grapics mode back to normal. */ 1385 TGAWREG(dc, TGA_REG_GMOR, 0); 1386 } 1387 1388 1389 static void 1390 tga_ramdac_wr(v, btreg, val) 1391 void *v; 1392 u_int btreg; 1393 u_int8_t val; 1394 { 1395 struct tga_devconfig *dc = v; 1396 1397 if (btreg > BT485_REG_MAX) 1398 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1399 1400 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1401 TGAREGWB(dc, TGA_REG_EPDR, 1); 1402 } 1403 1404 static void 1405 tga2_ramdac_wr(v, btreg, val) 1406 void *v; 1407 u_int btreg; 1408 u_int8_t val; 1409 { 1410 struct tga_devconfig *dc = v; 1411 bus_space_handle_t ramdac; 1412 1413 if (btreg > BT485_REG_MAX) 1414 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1415 1416 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1417 (0xe << 12) + (btreg << 8), 4, &ramdac); 1418 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1419 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1420 } 1421 1422 static u_int8_t 1423 tga_bt463_rd(v, btreg) 1424 void *v; 1425 u_int btreg; 1426 { 1427 struct tga_devconfig *dc = v; 1428 tga_reg_t rdval; 1429 1430 /* 1431 * Strobe CE# (high->low->high) since status and data are latched on 1432 * the falling and rising edges (repsectively) of this active-low signal. 1433 */ 1434 1435 TGAREGWB(dc, TGA_REG_EPSR, 1); 1436 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1437 TGAREGWB(dc, TGA_REG_EPSR, 1); 1438 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1439 1440 TGAREGRB(dc, TGA_REG_EPSR, 1); 1441 1442 rdval = TGARREG(dc, TGA_REG_EPDR); 1443 TGAREGWB(dc, TGA_REG_EPSR, 1); 1444 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1445 1446 return (rdval >> 16) & 0xff; 1447 } 1448 1449 static void 1450 tga_bt463_wr(v, btreg, val) 1451 void *v; 1452 u_int btreg; 1453 u_int8_t val; 1454 { 1455 struct tga_devconfig *dc = v; 1456 1457 /* 1458 * In spite of the 21030 documentation, to set the MPU bus bits for 1459 * a write, you set them in the upper bits of EPDR, not EPSR. 1460 */ 1461 1462 /* 1463 * Strobe CE# (high->low->high) since status and data are latched on 1464 * the falling and rising edges of this active-low signal. 1465 */ 1466 1467 TGAREGWB(dc, TGA_REG_EPDR, 1); 1468 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1469 TGAREGWB(dc, TGA_REG_EPDR, 1); 1470 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1471 TGAREGWB(dc, TGA_REG_EPDR, 1); 1472 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1473 1474 } 1475 1476 static u_int8_t 1477 tga_ramdac_rd(v, btreg) 1478 void *v; 1479 u_int btreg; 1480 { 1481 struct tga_devconfig *dc = v; 1482 tga_reg_t rdval; 1483 1484 if (btreg > BT485_REG_MAX) 1485 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1486 1487 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1488 TGAREGWB(dc, TGA_REG_EPSR, 1); 1489 1490 rdval = TGARREG(dc, TGA_REG_EPDR); 1491 return (rdval >> 16) & 0xff; /* XXX */ 1492 } 1493 1494 static u_int8_t 1495 tga2_ramdac_rd(v, btreg) 1496 void *v; 1497 u_int btreg; 1498 { 1499 struct tga_devconfig *dc = v; 1500 bus_space_handle_t ramdac; 1501 u_int8_t retval; 1502 1503 if (btreg > BT485_REG_MAX) 1504 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1505 1506 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1507 (0xe << 12) + (btreg << 8), 4, &ramdac); 1508 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1509 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1510 return retval; 1511 } 1512 1513 #include <dev/ic/decmonitors.c> 1514 void tga2_ics9110_wr __P(( 1515 struct tga_devconfig *dc, 1516 int dotclock 1517 )); 1518 1519 void 1520 tga2_init(dc, m) 1521 struct tga_devconfig *dc; 1522 int m; 1523 { 1524 1525 tga2_ics9110_wr(dc, decmonitors[m].dotclock); 1526 #if 0 1527 TGAWREG(dc, TGA_REG_VHCR, 1528 ((decmonitors[m].hbp / 4) << 21) | 1529 ((decmonitors[m].hsync / 4) << 14) | 1530 (((decmonitors[m].hfp - 4) / 4) << 9) | 1531 ((decmonitors[m].cols + 4) / 4)); 1532 #else 1533 TGAWREG(dc, TGA_REG_VHCR, 1534 ((decmonitors[m].hbp / 4) << 21) | 1535 ((decmonitors[m].hsync / 4) << 14) | 1536 (((decmonitors[m].hfp) / 4) << 9) | 1537 ((decmonitors[m].cols) / 4)); 1538 #endif 1539 TGAWREG(dc, TGA_REG_VVCR, 1540 (decmonitors[m].vbp << 22) | 1541 (decmonitors[m].vsync << 16) | 1542 (decmonitors[m].vfp << 11) | 1543 (decmonitors[m].rows)); 1544 TGAWREG(dc, TGA_REG_VVBR, 1); 1545 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1546 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1547 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1548 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1549 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1550 } 1551 1552 void 1553 tga2_ics9110_wr(dc, dotclock) 1554 struct tga_devconfig *dc; 1555 int dotclock; 1556 { 1557 bus_space_handle_t clock; 1558 u_int32_t valU; 1559 int N, M, R, V, X; 1560 int i; 1561 1562 switch (dotclock) { 1563 case 130808000: 1564 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1565 case 119840000: 1566 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1567 case 108180000: 1568 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1569 case 103994000: 1570 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1571 case 175000000: 1572 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1573 case 75000000: 1574 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1575 case 74000000: 1576 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1577 case 69000000: 1578 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1579 case 65000000: 1580 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1581 case 50000000: 1582 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1583 case 40000000: 1584 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1585 case 31500000: 1586 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1587 case 25175000: 1588 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1589 case 135000000: 1590 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1591 case 110000000: 1592 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1593 case 202500000: 1594 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1595 default: 1596 panic("unrecognized clock rate %d\n", dotclock); 1597 } 1598 1599 /* XXX -- hard coded, bad */ 1600 valU = N | ( M << 7 ) | (V << 14); 1601 valU |= (X << 15) | (R << 17); 1602 valU |= 0x17 << 19; 1603 1604 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1605 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1606 1607 for (i=24; i>0; i--) { 1608 u_int32_t writeval; 1609 1610 writeval = valU & 0x1; 1611 if (i == 1) 1612 writeval |= 0x2; 1613 valU >>= 1; 1614 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1615 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1616 } 1617 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1618 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1619 &clock); /* XXX */ 1620 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1621 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1622 } 1623