1 /* $NetBSD: tga.c,v 1.49 2002/10/02 16:51:55 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.49 2002/10/02 16:51:55 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 #ifdef __alpha__ 63 #include <machine/pte.h> 64 #endif 65 #ifdef __mips__ 66 #include <mips/pte.h> 67 #endif 68 69 int tgamatch __P((struct device *, struct cfdata *, void *)); 70 void tgaattach __P((struct device *, struct device *, void *)); 71 int tgaprint __P((void *, const char *)); 72 73 CFATTACH_DECL(tga, sizeof(struct tga_softc), 74 tgamatch, tgaattach, NULL, NULL); 75 76 int tga_identify __P((struct tga_devconfig *)); 77 const struct tga_conf *tga_getconf __P((int)); 78 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 79 pcitag_t tag, struct tga_devconfig *dc)); 80 81 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 82 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 83 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 84 unsigned tga_getdotclock __P((struct tga_devconfig *dc)); 85 86 struct tga_devconfig tga_console_dc; 87 88 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 89 paddr_t tga_mmap __P((void *, off_t, int)); 90 static void tga_copyrows __P((void *, int, int, int)); 91 static void tga_copycols __P((void *, int, int, int, int)); 92 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 93 void **, int *, int *, long *)); 94 static void tga_free_screen __P((void *, void *)); 95 static int tga_show_screen __P((void *, void *, int, 96 void (*) (void *, int, int), void *)); 97 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 98 struct rasops_info *, int, int)); 99 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 100 int, struct rasops_info *, int, int )); 101 static void tga_putchar __P((void *c, int row, int col, 102 u_int uc, long attr)); 103 static void tga_eraserows __P((void *, int, int, long)); 104 static void tga_erasecols __P((void *, int, int, int, long)); 105 void tga2_init __P((struct tga_devconfig *)); 106 107 static void tga_config_interrupts __P((struct device *)); 108 109 /* RAMDAC interface functions */ 110 static int tga_sched_update __P((void *, void (*)(void *))); 111 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 112 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 113 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 114 static u_int8_t tga_bt463_rd __P((void *, u_int)); 115 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 116 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 117 118 /* Interrupt handler */ 119 static int tga_intr __P((void *)); 120 121 /* The NULL entries will get filled in by rasops_init(). 122 * XXX and the non-NULL ones will be overwritten; reset after calling it. 123 */ 124 struct wsdisplay_emulops tga_emulops = { 125 NULL, 126 NULL, 127 tga_putchar, 128 tga_copycols, 129 tga_erasecols, 130 tga_copyrows, 131 tga_eraserows, 132 NULL, 133 }; 134 135 struct wsscreen_descr tga_stdscreen = { 136 "std", 137 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 138 &tga_emulops, 139 0, 0, 140 WSSCREEN_REVERSE 141 }; 142 143 const struct wsscreen_descr *_tga_scrlist[] = { 144 &tga_stdscreen, 145 /* XXX other formats, graphics screen? */ 146 }; 147 148 struct wsscreen_list tga_screenlist = { 149 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 150 }; 151 152 struct wsdisplay_accessops tga_accessops = { 153 tga_ioctl, 154 tga_mmap, 155 tga_alloc_screen, 156 tga_free_screen, 157 tga_show_screen, 158 0 /* load_font */ 159 }; 160 161 static void tga_blank __P((struct tga_devconfig *)); 162 static void tga_unblank __P((struct tga_devconfig *)); 163 164 int 165 tga_cnmatch(iot, memt, pc, tag) 166 bus_space_tag_t iot, memt; 167 pci_chipset_tag_t pc; 168 pcitag_t tag; 169 { 170 return tga_matchcommon(memt, pc, tag); 171 } 172 173 int 174 tgamatch(parent, match, aux) 175 struct device *parent; 176 struct cfdata *match; 177 void *aux; 178 { 179 struct pci_attach_args *pa = aux; 180 181 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 182 return (0); 183 184 switch (PCI_PRODUCT(pa->pa_id)) { 185 case PCI_PRODUCT_DEC_21030: 186 case PCI_PRODUCT_DEC_PBXGB: 187 break; 188 default: 189 return 0; 190 } 191 192 /* short-circuit the following test, as we 193 * already have the memory mapped and hence 194 * cannot perform it---and we are the console 195 * anyway. 196 */ 197 if (pa->pa_tag == tga_console_dc.dc_pcitag) 198 return 10; 199 200 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 201 } 202 203 static int 204 tga_matchcommon(memt, pc, tag) 205 bus_space_tag_t memt; 206 pci_chipset_tag_t pc; 207 pcitag_t tag; 208 { 209 struct tga_devconfig tmp_dc; 210 struct tga_devconfig *dc = &tmp_dc; 211 bus_size_t pcisize; 212 213 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 214 dc->dc_tga_type = tga_identify(dc); 215 216 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 217 bus_space_unmap(memt, dc->dc_memh, pcisize); 218 if (dc->dc_tgaconf) 219 return 10; 220 return 0; 221 } 222 223 static void 224 tga_mapaddrs(memt, pc, tag, pcisize, dc) 225 bus_space_tag_t memt; 226 pci_chipset_tag_t pc; 227 pcitag_t tag; 228 bus_size_t *pcisize; 229 struct tga_devconfig *dc; 230 { 231 int flags; 232 233 dc->dc_memt = memt; 234 dc->dc_tgaconf = NULL; 235 236 /* XXX magic number */ 237 if (pci_mapreg_info(pc, tag, 0x10, 238 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 239 &dc->dc_pcipaddr, pcisize, &flags)) 240 panic("tga_mapaddrs: pci_mapreg_info() failed"); 241 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 242 panic("tga memory not prefetchable"); 243 244 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 245 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 246 panic("tga_mapaddrs: could not map TGA address space"); 247 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 248 249 bus_space_subregion(dc->dc_memt, dc->dc_memh, 250 TGA_MEM_CREGS, TGA_CREGS_SIZE, 251 &dc->dc_regs); 252 } 253 254 static void 255 tga_init(memt, pc, tag, dc) 256 bus_space_tag_t memt; 257 pci_chipset_tag_t pc; 258 pcitag_t tag; 259 struct tga_devconfig *dc; 260 { 261 const struct tga_conf *tgac; 262 struct rasops_info *rip; 263 int cookie; 264 bus_size_t pcisize; 265 int i; 266 267 dc->dc_pcitag = tag; 268 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 269 dc->dc_tga_type = tga_identify(dc); 270 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 271 #if 0 272 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 273 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 274 panic("tga_init: memory size mismatch?"); 275 #endif 276 277 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 278 case 0x01: 279 case 0x02: 280 case 0x03: 281 case 0x04: 282 dc->dc_tga2 = 0; 283 break; 284 case 0x20: 285 case 0x21: 286 case 0x22: 287 dc->dc_tga2 = 1; 288 break; 289 default: 290 panic("tga_init: TGA Revision not recognized"); 291 } 292 293 if (dc->dc_tga2) 294 tga2_init(dc); 295 296 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 297 case 0: 298 dc->dc_wid = 8192; 299 break; 300 301 case 1: 302 dc->dc_wid = 8196; 303 break; 304 305 default: 306 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 307 break; 308 } 309 310 /* 311 * XXX XXX Turning off "odd" shouldn't be necessary, 312 * XXX XXX but I can't make X work with the weird size. 313 */ 314 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 315 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 316 TGAWREG(dc, TGA_REG_VHCR, 317 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 318 dc->dc_wid -= 4; 319 } 320 321 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 322 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 323 324 /* XXX this seems to be what DEC does */ 325 TGAWREG(dc, TGA_REG_CCBR, 0); 326 TGAWREG(dc, TGA_REG_VVBR, 1); 327 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 328 1 * tgac->tgac_vvbr_units; 329 dc->dc_blanked = 1; 330 tga_unblank(dc); 331 332 /* 333 * Set all bits in the pixel mask, to enable writes to all pixels. 334 * It seems that the console firmware clears some of them 335 * under some circumstances, which causes cute vertical stripes. 336 */ 337 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 338 339 /* clear the screen */ 340 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 341 *(u_int32_t *)(dc->dc_videobase + i) = 0; 342 343 /* Initialize rasops descriptor */ 344 rip = &dc->dc_rinfo; 345 rip->ri_flg = RI_CENTER; 346 rip->ri_depth = tgac->tgac_phys_depth; 347 rip->ri_bits = (void *)dc->dc_videobase; 348 rip->ri_width = dc->dc_wid; 349 rip->ri_height = dc->dc_ht; 350 rip->ri_stride = dc->dc_rowbytes; 351 rip->ri_hw = dc; 352 353 if (tgac->tgac_phys_depth == 32) { 354 rip->ri_rnum = 8; 355 rip->ri_gnum = 8; 356 rip->ri_bnum = 8; 357 rip->ri_rpos = 16; 358 rip->ri_gpos = 8; 359 rip->ri_bpos = 0; 360 } 361 362 wsfont_init(); 363 /* prefer 8 pixel wide font */ 364 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 365 WSDISPLAY_FONTORDER_L2R); 366 if (cookie <= 0) 367 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 368 WSDISPLAY_FONTORDER_L2R); 369 if (cookie <= 0) { 370 printf("tga: no appropriate fonts.\n"); 371 return; 372 } 373 374 /* the accelerated tga_putchar() needs LSbit left */ 375 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 376 printf("tga: couldn't lock font\n"); 377 return; 378 } 379 dc->dc_rinfo.ri_wsfcookie = cookie; 380 381 rasops_init(rip, 34, 80); 382 383 /* add our accelerated functions */ 384 /* XXX shouldn't have to do this; rasops should leave non-NULL 385 * XXX entries alone. 386 */ 387 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 388 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 389 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 390 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 391 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 392 393 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 394 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 395 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 396 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 397 398 399 dc->dc_intrenabled = 0; 400 } 401 402 void 403 tgaattach(parent, self, aux) 404 struct device *parent, *self; 405 void *aux; 406 { 407 struct pci_attach_args *pa = aux; 408 struct tga_softc *sc = (struct tga_softc *)self; 409 struct wsemuldisplaydev_attach_args aa; 410 pci_intr_handle_t intrh; 411 const char *intrstr; 412 u_int8_t rev; 413 int console; 414 415 #if defined(__alpha__) || defined(arc) 416 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 417 #else 418 console = 0; 419 #endif 420 if (console) { 421 sc->sc_dc = &tga_console_dc; 422 sc->nscreens = 1; 423 } else { 424 sc->sc_dc = (struct tga_devconfig *) 425 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 426 M_WAITOK|M_ZERO); 427 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 428 } 429 if (sc->sc_dc->dc_vaddr == NULL) { 430 printf(": couldn't map memory space; punt!\n"); 431 return; 432 } 433 434 /* XXX say what's going on. */ 435 intrstr = NULL; 436 if (pci_intr_map(pa, &intrh)) { 437 printf(": couldn't map interrupt"); 438 return; 439 } 440 intrstr = pci_intr_string(pa->pa_pc, intrh); 441 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 442 sc->sc_dc); 443 if (sc->sc_intr == NULL) { 444 printf(": couldn't establish interrupt"); 445 if (intrstr != NULL) 446 printf("at %s", intrstr); 447 printf("\n"); 448 return; 449 } 450 451 rev = PCI_REVISION(pa->pa_class); 452 switch (rev) { 453 case 0x1: 454 case 0x2: 455 case 0x3: 456 printf(": DC21030 step %c", 'A' + rev - 1); 457 break; 458 case 0x20: 459 printf(": TGA2 abstract software model"); 460 break; 461 case 0x21: 462 case 0x22: 463 printf(": TGA2 pass %d", rev - 0x20); 464 break; 465 466 default: 467 printf("unknown stepping (0x%x)", rev); 468 break; 469 } 470 printf(", "); 471 472 /* 473 * Get RAMDAC function vectors and call the RAMDAC functions 474 * to allocate its private storage and pass that back to us. 475 */ 476 477 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 478 if (!sc->sc_dc->dc_tga2) { 479 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 480 sc->sc_dc->dc_ramdac_cookie = 481 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 482 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 483 else 484 sc->sc_dc->dc_ramdac_cookie = 485 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 486 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 487 } else { 488 sc->sc_dc->dc_ramdac_cookie = 489 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 490 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 491 492 /* XXX this is a bit of a hack, setting the dotclock here */ 493 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 494 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 495 (sc->sc_dc->dc_ramdac_cookie, 496 tga_getdotclock(sc->sc_dc)); 497 } 498 499 /* 500 * Initialize the RAMDAC. Initialization includes disabling 501 * cursor, setting a sane colormap, etc. We presume that we've 502 * filled in the necessary dot clock for PowerStorm 4d20. 503 */ 504 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 505 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 506 507 if (sc->sc_dc->dc_tgaconf == NULL) { 508 printf("unknown board configuration\n"); 509 return; 510 } 511 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 512 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 513 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 514 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 515 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 516 517 if (intrstr != NULL) 518 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 519 intrstr); 520 521 aa.console = console; 522 aa.scrdata = &tga_screenlist; 523 aa.accessops = &tga_accessops; 524 aa.accesscookie = sc; 525 526 config_found(self, &aa, wsemuldisplaydevprint); 527 528 config_interrupts(self, tga_config_interrupts); 529 } 530 531 static void 532 tga_config_interrupts (d) 533 struct device *d; 534 { 535 struct tga_softc *sc = (struct tga_softc *)d; 536 sc->sc_dc->dc_intrenabled = 1; 537 } 538 539 int 540 tga_ioctl(v, cmd, data, flag, p) 541 void *v; 542 u_long cmd; 543 caddr_t data; 544 int flag; 545 struct proc *p; 546 { 547 struct tga_softc *sc = v; 548 struct tga_devconfig *dc = sc->sc_dc; 549 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 550 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 551 552 switch (cmd) { 553 case WSDISPLAYIO_GTYPE: 554 *(u_int *)data = WSDISPLAY_TYPE_TGA; 555 return (0); 556 557 case WSDISPLAYIO_GINFO: 558 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 559 wsd_fbip->height = sc->sc_dc->dc_ht; 560 wsd_fbip->width = sc->sc_dc->dc_wid; 561 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 562 #if 0 563 wsd_fbip->cmsize = 256; /* XXX ??? */ 564 #else 565 wsd_fbip->cmsize = 1024; /* XXX ??? */ 566 #endif 567 #undef wsd_fbip 568 return (0); 569 570 case WSDISPLAYIO_GETCMAP: 571 return (*dcrf->ramdac_get_cmap)(dcrc, 572 (struct wsdisplay_cmap *)data); 573 574 case WSDISPLAYIO_PUTCMAP: 575 return (*dcrf->ramdac_set_cmap)(dcrc, 576 (struct wsdisplay_cmap *)data); 577 578 case WSDISPLAYIO_SVIDEO: 579 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 580 tga_blank(sc->sc_dc); 581 else 582 tga_unblank(sc->sc_dc); 583 return (0); 584 585 case WSDISPLAYIO_GVIDEO: 586 *(u_int *)data = dc->dc_blanked ? 587 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 588 return (0); 589 590 case WSDISPLAYIO_GCURPOS: 591 return (*dcrf->ramdac_get_curpos)(dcrc, 592 (struct wsdisplay_curpos *)data); 593 594 case WSDISPLAYIO_SCURPOS: 595 return (*dcrf->ramdac_set_curpos)(dcrc, 596 (struct wsdisplay_curpos *)data); 597 598 case WSDISPLAYIO_GCURMAX: 599 return (*dcrf->ramdac_get_curmax)(dcrc, 600 (struct wsdisplay_curpos *)data); 601 602 case WSDISPLAYIO_GCURSOR: 603 return (*dcrf->ramdac_get_cursor)(dcrc, 604 (struct wsdisplay_cursor *)data); 605 606 case WSDISPLAYIO_SCURSOR: 607 return (*dcrf->ramdac_set_cursor)(dcrc, 608 (struct wsdisplay_cursor *)data); 609 } 610 return (EPASSTHROUGH); 611 } 612 613 static int 614 tga_sched_update(v, f) 615 void *v; 616 void (*f) __P((void *)); 617 { 618 struct tga_devconfig *dc = v; 619 620 if (dc->dc_intrenabled) { 621 /* Arrange for f to be called at the next end-of-frame interrupt */ 622 dc->dc_ramdac_intr = f; 623 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 624 } else { 625 /* Spin until the end-of-frame, then call f */ 626 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 627 TGAREGWB(dc, TGA_REG_SISR, 1); 628 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 629 ; 630 f(dc->dc_ramdac_cookie); 631 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 632 TGAREGWB(dc, TGA_REG_SISR, 1); 633 } 634 635 return 0; 636 } 637 638 static int 639 tga_intr(v) 640 void *v; 641 { 642 struct tga_devconfig *dc = v; 643 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 644 645 u_int32_t reg; 646 647 reg = TGARREG(dc, TGA_REG_SISR); 648 if (( reg & 0x00010001) != 0x00010001) { 649 /* Odd. We never set any of the other interrupt enables. */ 650 if ((reg & 0x1f) != 0) { 651 /* Clear the mysterious pending interrupts. */ 652 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 653 TGAREGWB(dc, TGA_REG_SISR, 1); 654 /* This was our interrupt, even if we're puzzled as to why 655 * we got it. Don't make the interrupt handler think it 656 * was a stray. 657 */ 658 return -1; 659 } else { 660 return 0; 661 } 662 } 663 /* if we have something to do, do it */ 664 if (dc->dc_ramdac_intr) { 665 dc->dc_ramdac_intr(dcrc); 666 dc->dc_ramdac_intr = NULL; 667 } 668 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 669 TGAREGWB(dc, TGA_REG_SISR, 1); 670 return (1); 671 } 672 673 paddr_t 674 tga_mmap(v, offset, prot) 675 void *v; 676 off_t offset; 677 int prot; 678 { 679 struct tga_softc *sc = v; 680 681 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 682 return -1; 683 684 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 685 offset, prot, BUS_SPACE_MAP_LINEAR)); 686 } 687 688 static int 689 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 690 void *v; 691 const struct wsscreen_descr *type; 692 void **cookiep; 693 int *curxp, *curyp; 694 long *attrp; 695 { 696 struct tga_softc *sc = v; 697 long defattr; 698 699 if (sc->nscreens > 0) 700 return (ENOMEM); 701 702 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 703 *curxp = 0; 704 *curyp = 0; 705 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 706 0, 0, 0, &defattr); 707 *attrp = defattr; 708 sc->nscreens++; 709 return (0); 710 } 711 712 static void 713 tga_free_screen(v, cookie) 714 void *v; 715 void *cookie; 716 { 717 struct tga_softc *sc = v; 718 719 if (sc->sc_dc == &tga_console_dc) 720 panic("tga_free_screen: console"); 721 722 sc->nscreens--; 723 } 724 725 static int 726 tga_show_screen(v, cookie, waitok, cb, cbarg) 727 void *v; 728 void *cookie; 729 int waitok; 730 void (*cb) __P((void *, int, int)); 731 void *cbarg; 732 { 733 734 return (0); 735 } 736 737 int 738 tga_cnattach(iot, memt, pc, bus, device, function) 739 bus_space_tag_t iot, memt; 740 pci_chipset_tag_t pc; 741 int bus, device, function; 742 { 743 struct tga_devconfig *dcp = &tga_console_dc; 744 long defattr; 745 746 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 747 748 /* sanity checks */ 749 if (dcp->dc_vaddr == NULL) 750 panic("tga_console(%d, %d): couldn't map memory space", 751 device, function); 752 if (dcp->dc_tgaconf == NULL) 753 panic("tga_console(%d, %d): unknown board configuration", 754 device, function); 755 756 /* 757 * Initialize the RAMDAC but DO NOT allocate any private storage. 758 * Initialization includes disabling cursor, setting a sane 759 * colormap, etc. It will be reinitialized in tgaattach(). 760 */ 761 if (dcp->dc_tga2) { 762 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 763 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 764 tga2_ramdac_rd); 765 else 766 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 767 tga2_ramdac_rd, tga_getdotclock(dcp)); 768 } else { 769 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 770 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 771 tga_ramdac_rd); 772 else { 773 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 774 tga_bt463_rd); 775 } 776 } 777 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 778 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 779 780 return(0); 781 } 782 783 /* 784 * Functions to blank and unblank the display. 785 */ 786 static void 787 tga_blank(dc) 788 struct tga_devconfig *dc; 789 { 790 791 if (!dc->dc_blanked) { 792 dc->dc_blanked = 1; 793 /* XXX */ 794 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 795 } 796 } 797 798 static void 799 tga_unblank(dc) 800 struct tga_devconfig *dc; 801 { 802 803 if (dc->dc_blanked) { 804 dc->dc_blanked = 0; 805 /* XXX */ 806 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 807 } 808 } 809 810 /* 811 * Functions to manipulate the built-in cursor handing hardware. 812 */ 813 int 814 tga_builtin_set_cursor(dc, cursorp) 815 struct tga_devconfig *dc; 816 struct wsdisplay_cursor *cursorp; 817 { 818 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 819 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 820 u_int count, v; 821 int error; 822 823 v = cursorp->which; 824 if (v & WSDISPLAY_CURSOR_DOCMAP) { 825 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 826 if (error) 827 return (error); 828 } 829 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 830 if ((u_int)cursorp->size.x != 64 || 831 (u_int)cursorp->size.y > 64) 832 return (EINVAL); 833 /* The cursor is 2 bits deep, and there is no mask */ 834 count = (cursorp->size.y * 64 * 2) / NBBY; 835 if (!uvm_useracc(cursorp->image, count, B_READ)) 836 return (EFAULT); 837 } 838 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 839 return EINVAL; 840 841 /* parameters are OK; do it */ 842 if (v & WSDISPLAY_CURSOR_DOCUR) { 843 if (cursorp->enable) 844 /* XXX */ 845 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 846 else 847 /* XXX */ 848 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 849 } 850 if (v & WSDISPLAY_CURSOR_DOPOS) { 851 TGAWREG(dc, TGA_REG_CXYR, 852 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 853 } 854 if (v & WSDISPLAY_CURSOR_DOCMAP) { 855 /* can't fail. */ 856 dcrf->ramdac_set_curcmap(dcrc, cursorp); 857 } 858 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 859 count = ((64 * 2) / NBBY) * cursorp->size.y; 860 TGAWREG(dc, TGA_REG_CCBR, 861 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 862 copyin(cursorp->image, (char *)(dc->dc_vaddr + 863 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 864 count); /* can't fail. */ 865 } 866 return (0); 867 } 868 869 int 870 tga_builtin_get_cursor(dc, cursorp) 871 struct tga_devconfig *dc; 872 struct wsdisplay_cursor *cursorp; 873 { 874 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 875 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 876 int count, error; 877 878 cursorp->which = WSDISPLAY_CURSOR_DOALL & 879 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 880 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 881 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 882 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 883 cursorp->size.x = 64; 884 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 885 886 if (cursorp->image != NULL) { 887 count = (cursorp->size.y * 64 * 2) / NBBY; 888 error = copyout((char *)(dc->dc_vaddr + 889 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 890 cursorp->image, count); 891 if (error) 892 return (error); 893 /* No mask */ 894 } 895 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 896 return (error); 897 } 898 899 int 900 tga_builtin_set_curpos(dc, curposp) 901 struct tga_devconfig *dc; 902 struct wsdisplay_curpos *curposp; 903 { 904 905 TGAWREG(dc, TGA_REG_CXYR, 906 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 907 return (0); 908 } 909 910 int 911 tga_builtin_get_curpos(dc, curposp) 912 struct tga_devconfig *dc; 913 struct wsdisplay_curpos *curposp; 914 { 915 916 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 917 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 918 return (0); 919 } 920 921 int 922 tga_builtin_get_curmax(dc, curposp) 923 struct tga_devconfig *dc; 924 struct wsdisplay_curpos *curposp; 925 { 926 927 curposp->x = curposp->y = 64; 928 return (0); 929 } 930 931 /* 932 * Copy columns (characters) in a row (line). 933 */ 934 static void 935 tga_copycols(id, row, srccol, dstcol, ncols) 936 void *id; 937 int row, srccol, dstcol, ncols; 938 { 939 struct rasops_info *ri = id; 940 int y, srcx, dstx, nx; 941 942 y = ri->ri_font->fontheight * row; 943 srcx = ri->ri_font->fontwidth * srccol; 944 dstx = ri->ri_font->fontwidth * dstcol; 945 nx = ri->ri_font->fontwidth * ncols; 946 947 tga_rop(ri, dstx, y, 948 nx, ri->ri_font->fontheight, RAS_SRC, 949 ri, srcx, y); 950 } 951 952 /* 953 * Copy rows (lines). 954 */ 955 static void 956 tga_copyrows(id, srcrow, dstrow, nrows) 957 void *id; 958 int srcrow, dstrow, nrows; 959 { 960 struct rasops_info *ri = id; 961 int srcy, dsty, ny; 962 963 srcy = ri->ri_font->fontheight * srcrow; 964 dsty = ri->ri_font->fontheight * dstrow; 965 ny = ri->ri_font->fontheight * nrows; 966 967 tga_rop(ri, 0, dsty, 968 ri->ri_emuwidth, ny, RAS_SRC, 969 ri, 0, srcy); 970 } 971 972 /* Do we need the src? */ 973 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 974 975 /* A mapping between our API and the TGA card */ 976 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 977 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 978 }; 979 980 /* 981 * Generic TGA raster op. 982 * This covers all possible raster ops, and 983 * clips the sizes and all of that. 984 */ 985 static int 986 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 987 struct rasops_info *dst; 988 int dx, dy, w, h, rop; 989 struct rasops_info *src; 990 int sx, sy; 991 { 992 if (!dst) 993 return -1; 994 if (needsrc[RAS_GETOP(rop)]) { 995 if (src == NULL) 996 return -1; /* We want a src */ 997 /* Clip against src */ 998 if (sx < 0) { 999 w += sx; 1000 sx = 0; 1001 } 1002 if (sy < 0) { 1003 h += sy; 1004 sy = 0; 1005 } 1006 if (sx + w > src->ri_emuwidth) 1007 w = src->ri_emuwidth - sx; 1008 if (sy + h > src->ri_emuheight) 1009 h = src->ri_emuheight - sy; 1010 } else { 1011 if (src != NULL) 1012 return -1; /* We need no src */ 1013 } 1014 /* Clip against dst. We modify src regardless of using it, 1015 * since it really doesn't matter. 1016 */ 1017 if (dx < 0) { 1018 w += dx; 1019 sx -= dx; 1020 dx = 0; 1021 } 1022 if (dy < 0) { 1023 h += dy; 1024 sy -= dy; 1025 dy = 0; 1026 } 1027 if (dx + w > dst->ri_emuwidth) 1028 w = dst->ri_emuwidth - dx; 1029 if (dy + h > dst->ri_emuheight) 1030 h = dst->ri_emuheight - dy; 1031 if (w <= 0 || h <= 0) 1032 return 0; /* Vacuously true; */ 1033 if (!src) { 1034 /* XXX Punt! */ 1035 return -1; 1036 } 1037 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1038 } 1039 1040 1041 1042 /* 1043 * Video to Video raster ops. 1044 * This function deals with all raster ops that have a src and dst 1045 * that are on the card. 1046 */ 1047 static int 1048 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1049 struct rasops_info *dst; 1050 int dx, dy, w, h, rop; 1051 struct rasops_info *src; 1052 int sx, sy; 1053 { 1054 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1055 int srcb, dstb, tga_srcb, tga_dstb; 1056 int x, y, wb; 1057 int xstart, xend, xdir; 1058 int ystart, yend, ydir, yinc; 1059 int xleft, lastx, lastleft; 1060 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1061 1062 /* 1063 * I don't yet want to deal with unaligned guys, really. And we don't 1064 * deal with copies from one card to another. 1065 */ 1066 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1067 /* XXX Punt! */ 1068 /* XXX should never happen, since it's only being used to 1069 * XXX copy 8-pixel-wide characters. 1070 */ 1071 return -1; 1072 } 1073 1074 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1075 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1076 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1077 (sx + src->ri_xorigin) * (src->ri_depth/8); 1078 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1079 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1080 1081 if (sy >= dy) { 1082 ystart = 0; 1083 yend = (h - 1) * dst->ri_stride; 1084 ydir = 1; 1085 } else { 1086 ystart = (h - 1) * dst->ri_stride; 1087 yend = 0; 1088 ydir = -1; 1089 } 1090 yinc = ydir * dst->ri_stride; 1091 1092 wb = w * (dst->ri_depth / 8); 1093 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1094 xstart = 0; 1095 xend = wb; 1096 xdir = 1; 1097 } else { /* copy backwards */ 1098 xstart = wb; 1099 xend = 0; 1100 xdir = -1; 1101 } 1102 1103 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1104 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1105 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1106 1107 /* 1108 * we have 3 sizes of pixels to move in X direction: 1109 * 4 * 64 (unrolled TGA ops) 1110 * 64 (single TGA op) 1111 * 4 (CPU, using long word) 1112 */ 1113 1114 if (xdir == 1) { /* move to the left */ 1115 1116 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1117 /* 4*64 byte chunks */ 1118 for (xleft = wb, x = xstart; xleft >= 4*64; 1119 x += 4*64, xleft -= 4*64) { 1120 1121 /* XXX XXX Eight writes to different addresses should fill 1122 * XXX XXX up the write buffers on 21064 and 21164 chips, 1123 * XXX XXX but later CPUs might have larger write buffers which 1124 * XXX XXX require further unrolling of this loop, or the 1125 * XXX XXX insertion of memory barriers. 1126 */ 1127 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1128 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1129 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1130 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1131 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1132 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1133 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1134 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1135 } 1136 1137 /* 64 byte chunks */ 1138 for (; xleft >= 64; x += 64, xleft -= 64) { 1139 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1140 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1141 } 1142 1143 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1144 } 1145 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1146 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1147 1148 if (lastleft) { 1149 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1150 /* 4 byte granularity */ 1151 for (x = lastx, xleft = lastleft; xleft >= 4; 1152 x += 4, xleft -= 4) { 1153 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1154 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1155 } 1156 } 1157 } 1158 } 1159 else { /* above move to the left, below move to the right */ 1160 1161 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1162 /* 4*64 byte chunks */ 1163 for (xleft = wb, x = xstart; xleft >= 4*64; 1164 x -= 4*64, xleft -= 4*64) { 1165 1166 /* XXX XXX Eight writes to different addresses should fill 1167 * XXX XXX up the write buffers on 21064 and 21164 chips, 1168 * XXX XXX but later CPUs might have larger write buffers which 1169 * XXX XXX require further unrolling of this loop, or the 1170 * XXX XXX insertion of memory barriers. 1171 */ 1172 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1173 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1174 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1175 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1176 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1177 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1178 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1179 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1180 } 1181 1182 /* 64 byte chunks */ 1183 for (; xleft >= 64; x -= 64, xleft -= 64) { 1184 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1185 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1186 } 1187 1188 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1189 } 1190 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1191 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1192 1193 if (lastleft) { 1194 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1195 /* 4 byte granularity */ 1196 for (x = lastx, xleft = lastleft; xleft >= 4; 1197 x -= 4, xleft -= 4) { 1198 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1199 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1200 } 1201 } 1202 } 1203 } 1204 return 0; 1205 } 1206 1207 1208 void tga_putchar (c, row, col, uc, attr) 1209 void *c; 1210 int row, col; 1211 u_int uc; 1212 long attr; 1213 { 1214 struct rasops_info *ri = c; 1215 struct tga_devconfig *dc = ri->ri_hw; 1216 int fs, height, width; 1217 u_char *fr; 1218 int32_t *rp; 1219 1220 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1221 1222 height = ri->ri_font->fontheight; 1223 width = ri->ri_font->fontwidth; 1224 1225 uc -= ri->ri_font->firstchar; 1226 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1227 fs = ri->ri_font->stride; 1228 1229 /* Set foreground and background color. XXX memoize this somehow? 1230 * The rasops code has already expanded the color entry to 32 bits 1231 * for us, even for 8-bit displays, so we don't have to do anything. 1232 */ 1233 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1234 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1235 1236 /* Set raster operation to "copy"... */ 1237 if (ri->ri_depth == 8) 1238 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1239 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1240 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1241 1242 /* Set which pixels we're drawing (of a possible 32). */ 1243 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1244 1245 /* Set drawing mode to opaque stipple. */ 1246 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1247 1248 /* Insert write barrier before actually sending data */ 1249 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1250 TGAREGWB(dc, TGA_REG_GMOR, 1); 1251 1252 while(height--) { 1253 /* The actual stipple write */ 1254 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1255 1256 fr += fs; 1257 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1258 } 1259 1260 /* Do underline */ 1261 if ((attr & 1) != 0) { 1262 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1263 *rp = 0xffffffff; 1264 } 1265 1266 /* Set grapics mode back to normal. */ 1267 TGAWREG(dc, TGA_REG_GMOR, 0); 1268 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1269 1270 } 1271 1272 static void 1273 tga_eraserows(c, row, num, attr) 1274 void *c; 1275 int row, num; 1276 long attr; 1277 { 1278 struct rasops_info *ri = c; 1279 struct tga_devconfig *dc = ri->ri_hw; 1280 int32_t color, lines, pixels; 1281 int32_t *rp; 1282 1283 color = ri->ri_devcmap[(attr >> 16) & 15]; 1284 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1285 lines = num * ri->ri_font->fontheight; 1286 pixels = ri->ri_emuwidth - 1; 1287 1288 /* Set fill color in block-color registers */ 1289 TGAWREG(dc, TGA_REG_GBCR0, color); 1290 TGAWREG(dc, TGA_REG_GBCR1, color); 1291 if (ri->ri_depth != 8) { 1292 TGAWREG(dc, TGA_REG_GBCR2, color); 1293 TGAWREG(dc, TGA_REG_GBCR3, color); 1294 TGAWREG(dc, TGA_REG_GBCR4, color); 1295 TGAWREG(dc, TGA_REG_GBCR5, color); 1296 TGAWREG(dc, TGA_REG_GBCR6, color); 1297 TGAWREG(dc, TGA_REG_GBCR7, color); 1298 } 1299 1300 /* Set raster operation to "copy"... */ 1301 if (ri->ri_depth == 8) 1302 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1303 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1304 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1305 1306 /* Set which pixels we're drawing (of a possible 32). */ 1307 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1308 1309 /* Set drawing mode to block fill. */ 1310 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1311 1312 /* Insert write barrier before actually sending data */ 1313 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1314 TGAREGWB(dc, TGA_REG_GMOR, 1); 1315 1316 while (lines--) { 1317 *rp = pixels; 1318 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1319 } 1320 1321 /* Set grapics mode back to normal. */ 1322 TGAWREG(dc, TGA_REG_GMOR, 0); 1323 1324 } 1325 1326 static void 1327 tga_erasecols (c, row, col, num, attr) 1328 void *c; 1329 int row, col, num; 1330 long attr; 1331 { 1332 struct rasops_info *ri = c; 1333 struct tga_devconfig *dc = ri->ri_hw; 1334 int32_t color, lines, pixels; 1335 int32_t *rp; 1336 1337 color = ri->ri_devcmap[(attr >> 16) & 15]; 1338 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1339 lines = ri->ri_font->fontheight; 1340 pixels = (num * ri->ri_font->fontwidth) - 1; 1341 1342 /* Set fill color in block-color registers */ 1343 TGAWREG(dc, TGA_REG_GBCR0, color); 1344 TGAWREG(dc, TGA_REG_GBCR1, color); 1345 if (ri->ri_depth != 8) { 1346 TGAWREG(dc, TGA_REG_GBCR2, color); 1347 TGAWREG(dc, TGA_REG_GBCR3, color); 1348 TGAWREG(dc, TGA_REG_GBCR4, color); 1349 TGAWREG(dc, TGA_REG_GBCR5, color); 1350 TGAWREG(dc, TGA_REG_GBCR6, color); 1351 TGAWREG(dc, TGA_REG_GBCR7, color); 1352 } 1353 1354 /* Set raster operation to "copy"... */ 1355 if (ri->ri_depth == 8) 1356 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1357 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1358 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1359 1360 /* Set which pixels we're drawing (of a possible 32). */ 1361 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1362 1363 /* Set drawing mode to block fill. */ 1364 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1365 1366 /* Insert write barrier before actually sending data */ 1367 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1368 TGAREGWB(dc, TGA_REG_GMOR, 1); 1369 1370 while (lines--) { 1371 *rp = pixels; 1372 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1373 } 1374 1375 /* Set grapics mode back to normal. */ 1376 TGAWREG(dc, TGA_REG_GMOR, 0); 1377 } 1378 1379 1380 static void 1381 tga_ramdac_wr(v, btreg, val) 1382 void *v; 1383 u_int btreg; 1384 u_int8_t val; 1385 { 1386 struct tga_devconfig *dc = v; 1387 1388 if (btreg > BT485_REG_MAX) 1389 panic("tga_ramdac_wr: reg %d out of range", btreg); 1390 1391 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1392 TGAREGWB(dc, TGA_REG_EPDR, 1); 1393 } 1394 1395 static void 1396 tga2_ramdac_wr(v, btreg, val) 1397 void *v; 1398 u_int btreg; 1399 u_int8_t val; 1400 { 1401 struct tga_devconfig *dc = v; 1402 bus_space_handle_t ramdac; 1403 1404 if (btreg > BT485_REG_MAX) 1405 panic("tga_ramdac_wr: reg %d out of range", btreg); 1406 1407 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1408 (0xe << 12) + (btreg << 8), 4, &ramdac); 1409 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1410 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1411 } 1412 1413 static u_int8_t 1414 tga_bt463_rd(v, btreg) 1415 void *v; 1416 u_int btreg; 1417 { 1418 struct tga_devconfig *dc = v; 1419 tga_reg_t rdval; 1420 1421 /* 1422 * Strobe CE# (high->low->high) since status and data are latched on 1423 * the falling and rising edges (repsectively) of this active-low signal. 1424 */ 1425 1426 TGAREGWB(dc, TGA_REG_EPSR, 1); 1427 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1428 TGAREGWB(dc, TGA_REG_EPSR, 1); 1429 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1430 1431 TGAREGRB(dc, TGA_REG_EPSR, 1); 1432 1433 rdval = TGARREG(dc, TGA_REG_EPDR); 1434 TGAREGWB(dc, TGA_REG_EPSR, 1); 1435 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1436 1437 return (rdval >> 16) & 0xff; 1438 } 1439 1440 static void 1441 tga_bt463_wr(v, btreg, val) 1442 void *v; 1443 u_int btreg; 1444 u_int8_t val; 1445 { 1446 struct tga_devconfig *dc = v; 1447 1448 /* 1449 * In spite of the 21030 documentation, to set the MPU bus bits for 1450 * a write, you set them in the upper bits of EPDR, not EPSR. 1451 */ 1452 1453 /* 1454 * Strobe CE# (high->low->high) since status and data are latched on 1455 * the falling and rising edges of this active-low signal. 1456 */ 1457 1458 TGAREGWB(dc, TGA_REG_EPDR, 1); 1459 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1460 TGAREGWB(dc, TGA_REG_EPDR, 1); 1461 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1462 TGAREGWB(dc, TGA_REG_EPDR, 1); 1463 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1464 1465 } 1466 1467 static u_int8_t 1468 tga_ramdac_rd(v, btreg) 1469 void *v; 1470 u_int btreg; 1471 { 1472 struct tga_devconfig *dc = v; 1473 tga_reg_t rdval; 1474 1475 if (btreg > BT485_REG_MAX) 1476 panic("tga_ramdac_rd: reg %d out of range", btreg); 1477 1478 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1479 TGAREGWB(dc, TGA_REG_EPSR, 1); 1480 1481 rdval = TGARREG(dc, TGA_REG_EPDR); 1482 return (rdval >> 16) & 0xff; /* XXX */ 1483 } 1484 1485 static u_int8_t 1486 tga2_ramdac_rd(v, btreg) 1487 void *v; 1488 u_int btreg; 1489 { 1490 struct tga_devconfig *dc = v; 1491 bus_space_handle_t ramdac; 1492 u_int8_t retval; 1493 1494 if (btreg > BT485_REG_MAX) 1495 panic("tga_ramdac_rd: reg %d out of range", btreg); 1496 1497 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1498 (0xe << 12) + (btreg << 8), 4, &ramdac); 1499 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1500 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1501 return retval; 1502 } 1503 1504 #include <dev/ic/decmonitors.c> 1505 void tga2_ics9110_wr __P(( 1506 struct tga_devconfig *dc, 1507 int dotclock 1508 )); 1509 1510 struct monitor *tga_getmonitor __P((struct tga_devconfig *dc)); 1511 1512 void 1513 tga2_init(dc) 1514 struct tga_devconfig *dc; 1515 { 1516 struct monitor *m = tga_getmonitor(dc); 1517 1518 /* Deal with the dot clocks. 1519 */ 1520 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1521 /* Set this up as a reference clock for the 1522 * ibm561's PLL. 1523 */ 1524 tga2_ics9110_wr(dc, 14300000); 1525 /* XXX Can't set up the dotclock properly, until such time 1526 * as the RAMDAC is configured. 1527 */ 1528 } else { 1529 /* otherwise the ics9110 is our clock. */ 1530 tga2_ics9110_wr(dc, m->dotclock); 1531 } 1532 #if 0 1533 TGAWREG(dc, TGA_REG_VHCR, 1534 ((m->hbp / 4) << 21) | 1535 ((m->hsync / 4) << 14) | 1536 (((m->hfp - 4) / 4) << 9) | 1537 ((m->cols + 4) / 4)); 1538 #else 1539 TGAWREG(dc, TGA_REG_VHCR, 1540 ((m->hbp / 4) << 21) | 1541 ((m->hsync / 4) << 14) | 1542 (((m->hfp) / 4) << 9) | 1543 ((m->cols) / 4)); 1544 #endif 1545 TGAWREG(dc, TGA_REG_VVCR, 1546 (m->vbp << 22) | 1547 (m->vsync << 16) | 1548 (m->vfp << 11) | 1549 (m->rows)); 1550 TGAWREG(dc, TGA_REG_VVBR, 1); 1551 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1552 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1553 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1554 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1555 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1556 } 1557 1558 void 1559 tga2_ics9110_wr(dc, dotclock) 1560 struct tga_devconfig *dc; 1561 int dotclock; 1562 { 1563 bus_space_handle_t clock; 1564 u_int32_t valU; 1565 int N, M, R, V, X; 1566 int i; 1567 1568 switch (dotclock) { 1569 case 130808000: 1570 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1571 case 119840000: 1572 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1573 case 108180000: 1574 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1575 case 103994000: 1576 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1577 case 175000000: 1578 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1579 case 75000000: 1580 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1581 case 74000000: 1582 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1583 case 69000000: 1584 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1585 case 65000000: 1586 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1587 case 50000000: 1588 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1589 case 40000000: 1590 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1591 case 31500000: 1592 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1593 case 25175000: 1594 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1595 case 135000000: 1596 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1597 case 110000000: 1598 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1599 case 202500000: 1600 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1601 case 14300000: /* this one is just a ref clock */ 1602 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1603 default: 1604 panic("unrecognized clock rate %d", dotclock); 1605 } 1606 1607 /* XXX -- hard coded, bad */ 1608 valU = N | ( M << 7 ) | (V << 14); 1609 valU |= (X << 15) | (R << 17); 1610 valU |= 0x17 << 19; 1611 1612 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1613 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1614 1615 for (i=24; i>0; i--) { 1616 u_int32_t writeval; 1617 1618 writeval = valU & 0x1; 1619 if (i == 1) 1620 writeval |= 0x2; 1621 valU >>= 1; 1622 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1623 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1624 } 1625 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1626 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1627 &clock); /* XXX */ 1628 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1629 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1630 } 1631 1632 struct monitor * 1633 tga_getmonitor(dc) 1634 struct tga_devconfig *dc; 1635 { 1636 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1637 } 1638 1639 unsigned 1640 tga_getdotclock(dc) 1641 struct tga_devconfig *dc; 1642 { 1643 return tga_getmonitor(dc)->dotclock; 1644 } 1645