1 /* $NetBSD: tga.c,v 1.72 2009/03/16 23:11:16 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.72 2009/03/16 23:11:16 dsl Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <uvm/uvm_extern.h> 62 63 int tgamatch(struct device *, struct cfdata *, void *); 64 void tgaattach(struct device *, struct device *, void *); 65 int tgaprint(void *, const char *); 66 67 CFATTACH_DECL(tga, sizeof(struct tga_softc), 68 tgamatch, tgaattach, NULL, NULL); 69 70 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 71 pcitag_t tag, struct tga_devconfig *dc); 72 73 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 74 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 75 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 76 unsigned tga_getdotclock(struct tga_devconfig *dc); 77 78 struct tga_devconfig tga_console_dc; 79 80 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 81 paddr_t tga_mmap(void *, void *, off_t, int); 82 static void tga_copyrows(void *, int, int, int); 83 static void tga_copycols(void *, int, int, int, int); 84 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 85 void **, int *, int *, long *); 86 static void tga_free_screen(void *, void *); 87 static int tga_show_screen(void *, void *, int, 88 void (*) (void *, int, int), void *); 89 static int tga_rop(struct rasops_info *, int, int, int, int, int, 90 struct rasops_info *, int, int); 91 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 92 int, struct rasops_info *, int, int); 93 static void tga_putchar(void *c, int row, int col, 94 u_int uc, long attr); 95 static void tga_eraserows(void *, int, int, long); 96 static void tga_erasecols(void *, int, int, int, long); 97 void tga2_init(struct tga_devconfig *); 98 99 static void tga_config_interrupts(struct device *); 100 101 /* RAMDAC interface functions */ 102 static int tga_sched_update(void *, void (*)(void *)); 103 static void tga_ramdac_wr(void *, u_int, u_int8_t); 104 static u_int8_t tga_ramdac_rd(void *, u_int); 105 static void tga_bt463_wr(void *, u_int, u_int8_t); 106 static u_int8_t tga_bt463_rd(void *, u_int); 107 static void tga2_ramdac_wr(void *, u_int, u_int8_t); 108 static u_int8_t tga2_ramdac_rd(void *, u_int); 109 110 /* Interrupt handler */ 111 static int tga_intr(void *); 112 113 /* The NULL entries will get filled in by rasops_init(). 114 * XXX and the non-NULL ones will be overwritten; reset after calling it. 115 */ 116 struct wsdisplay_emulops tga_emulops = { 117 NULL, 118 NULL, 119 tga_putchar, 120 tga_copycols, 121 tga_erasecols, 122 tga_copyrows, 123 tga_eraserows, 124 NULL, 125 NULL, 126 }; 127 128 struct wsscreen_descr tga_stdscreen = { 129 "std", 130 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 131 &tga_emulops, 132 0, 0, 133 WSSCREEN_REVERSE, 134 NULL, 135 }; 136 137 const struct wsscreen_descr *_tga_scrlist[] = { 138 &tga_stdscreen, 139 /* XXX other formats, graphics screen? */ 140 }; 141 142 struct wsscreen_list tga_screenlist = { 143 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 144 }; 145 146 struct wsdisplay_accessops tga_accessops = { 147 tga_ioctl, 148 tga_mmap, 149 tga_alloc_screen, 150 tga_free_screen, 151 tga_show_screen, 152 NULL, /* load_font */ 153 NULL, 154 NULL, 155 }; 156 157 static void tga_blank(struct tga_devconfig *); 158 static void tga_unblank(struct tga_devconfig *); 159 160 int 161 tga_cnmatch(bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 162 { 163 return tga_matchcommon(memt, pc, tag); 164 } 165 166 int 167 tgamatch(struct device *parent, struct cfdata *match, void *aux) 168 { 169 struct pci_attach_args *pa = aux; 170 171 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 172 return (0); 173 174 switch (PCI_PRODUCT(pa->pa_id)) { 175 case PCI_PRODUCT_DEC_21030: 176 case PCI_PRODUCT_DEC_PBXGB: 177 break; 178 default: 179 return 0; 180 } 181 182 #if defined(__alpha__) || defined(arc) 183 /* short-circuit the following test, as we 184 * already have the memory mapped and hence 185 * cannot perform it---and we are the console 186 * anyway. 187 */ 188 if (pa->pa_tag == tga_console_dc.dc_pcitag) 189 return 10; 190 #endif 191 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 192 } 193 194 static int 195 tga_matchcommon(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 196 { 197 struct tga_devconfig tmp_dc; 198 struct tga_devconfig *dc = &tmp_dc; 199 bus_size_t pcisize; 200 201 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 202 dc->dc_tga_type = tga_identify(dc); 203 204 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 205 bus_space_unmap(memt, dc->dc_memh, pcisize); 206 if (dc->dc_tgaconf) 207 return 10; 208 return 0; 209 } 210 211 static void 212 tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, bus_size_t *pcisize, struct tga_devconfig *dc) 213 { 214 int flags; 215 216 dc->dc_memt = memt; 217 dc->dc_tgaconf = NULL; 218 219 /* XXX magic number */ 220 if (pci_mapreg_info(pc, tag, 0x10, 221 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 222 &dc->dc_pcipaddr, pcisize, &flags)) 223 panic("tga_mapaddrs: pci_mapreg_info() failed"); 224 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 225 panic("tga memory not prefetchable"); 226 227 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 228 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 229 panic("tga_mapaddrs: could not map TGA address space"); 230 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 231 232 bus_space_subregion(dc->dc_memt, dc->dc_memh, 233 TGA_MEM_CREGS, TGA_CREGS_SIZE, 234 &dc->dc_regs); 235 } 236 237 static void 238 tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, struct tga_devconfig *dc) 239 { 240 const struct tga_conf *tgac; 241 struct rasops_info *rip; 242 int cookie; 243 bus_size_t pcisize; 244 int i; 245 246 dc->dc_pc = pc; 247 dc->dc_pcitag = tag; 248 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 249 dc->dc_tga_type = tga_identify(dc); 250 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 251 #if 0 252 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 253 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 254 panic("tga_init: memory size mismatch?"); 255 #endif 256 257 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 258 case 0x01: 259 case 0x02: 260 case 0x03: 261 case 0x04: 262 dc->dc_tga2 = 0; 263 break; 264 case 0x20: 265 case 0x21: 266 case 0x22: 267 dc->dc_tga2 = 1; 268 break; 269 default: 270 panic("tga_init: TGA Revision not recognized"); 271 } 272 273 if (dc->dc_tga2) 274 tga2_init(dc); 275 276 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 277 case 0: 278 dc->dc_wid = 8192; 279 break; 280 281 case 1: 282 dc->dc_wid = 8196; 283 break; 284 285 default: 286 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 287 break; 288 } 289 290 /* 291 * XXX XXX Turning off "odd" shouldn't be necessary, 292 * XXX XXX but I can't make X work with the weird size. 293 */ 294 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 295 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 296 TGAWREG(dc, TGA_REG_VHCR, 297 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 298 dc->dc_wid -= 4; 299 } 300 301 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 302 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 303 304 /* XXX this seems to be what DEC does */ 305 TGAWREG(dc, TGA_REG_CCBR, 0); 306 TGAWREG(dc, TGA_REG_VVBR, 1); 307 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 308 1 * tgac->tgac_vvbr_units; 309 dc->dc_blanked = 1; 310 tga_unblank(dc); 311 312 /* 313 * Set all bits in the pixel mask, to enable writes to all pixels. 314 * It seems that the console firmware clears some of them 315 * under some circumstances, which causes cute vertical stripes. 316 */ 317 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 318 319 /* clear the screen */ 320 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 321 *(u_int32_t *)(dc->dc_videobase + i) = 0; 322 323 /* Initialize rasops descriptor */ 324 rip = &dc->dc_rinfo; 325 rip->ri_flg = RI_CENTER; 326 rip->ri_depth = tgac->tgac_phys_depth; 327 rip->ri_bits = (void *)dc->dc_videobase; 328 rip->ri_width = dc->dc_wid; 329 rip->ri_height = dc->dc_ht; 330 rip->ri_stride = dc->dc_rowbytes; 331 rip->ri_hw = dc; 332 333 if (tgac->tgac_phys_depth == 32) { 334 rip->ri_rnum = 8; 335 rip->ri_gnum = 8; 336 rip->ri_bnum = 8; 337 rip->ri_rpos = 16; 338 rip->ri_gpos = 8; 339 rip->ri_bpos = 0; 340 } 341 342 wsfont_init(); 343 /* prefer 8 pixel wide font */ 344 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 345 WSDISPLAY_FONTORDER_L2R); 346 if (cookie <= 0) 347 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 348 WSDISPLAY_FONTORDER_L2R); 349 if (cookie <= 0) { 350 printf("tga: no appropriate fonts.\n"); 351 return; 352 } 353 354 /* the accelerated tga_putchar() needs LSbit left */ 355 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 356 printf("tga: couldn't lock font\n"); 357 return; 358 } 359 dc->dc_rinfo.ri_wsfcookie = cookie; 360 361 rasops_init(rip, 34, 80); 362 363 /* add our accelerated functions */ 364 /* XXX shouldn't have to do this; rasops should leave non-NULL 365 * XXX entries alone. 366 */ 367 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 368 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 369 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 370 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 371 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 372 373 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 374 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 375 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 376 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 377 378 379 dc->dc_intrenabled = 0; 380 } 381 382 void 383 tgaattach(struct device *parent, struct device *self, void *aux) 384 { 385 struct pci_attach_args *pa = aux; 386 struct tga_softc *sc = (struct tga_softc *)self; 387 struct wsemuldisplaydev_attach_args aa; 388 pci_intr_handle_t intrh; 389 const char *intrstr; 390 u_int8_t rev; 391 int console; 392 393 #if defined(__alpha__) || defined(arc) 394 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 395 #else 396 console = 0; 397 #endif 398 if (console) { 399 sc->sc_dc = &tga_console_dc; 400 sc->nscreens = 1; 401 } else { 402 sc->sc_dc = (struct tga_devconfig *) 403 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 404 M_WAITOK|M_ZERO); 405 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 406 } 407 if (sc->sc_dc->dc_vaddr == 0) { 408 printf(": couldn't map memory space; punt!\n"); 409 return; 410 } 411 412 /* XXX say what's going on. */ 413 intrstr = NULL; 414 if (pci_intr_map(pa, &intrh)) { 415 printf(": couldn't map interrupt"); 416 return; 417 } 418 intrstr = pci_intr_string(pa->pa_pc, intrh); 419 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 420 sc->sc_dc); 421 if (sc->sc_intr == NULL) { 422 printf(": couldn't establish interrupt"); 423 if (intrstr != NULL) 424 printf("at %s", intrstr); 425 printf("\n"); 426 return; 427 } 428 429 rev = PCI_REVISION(pa->pa_class); 430 switch (rev) { 431 case 0x1: 432 case 0x2: 433 case 0x3: 434 printf(": DC21030 step %c", 'A' + rev - 1); 435 break; 436 case 0x20: 437 printf(": TGA2 abstract software model"); 438 break; 439 case 0x21: 440 case 0x22: 441 printf(": TGA2 pass %d", rev - 0x20); 442 break; 443 444 default: 445 printf("unknown stepping (0x%x)", rev); 446 break; 447 } 448 printf(", "); 449 450 /* 451 * Get RAMDAC function vectors and call the RAMDAC functions 452 * to allocate its private storage and pass that back to us. 453 */ 454 455 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 456 if (!sc->sc_dc->dc_tga2) { 457 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 458 sc->sc_dc->dc_ramdac_cookie = 459 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 460 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 461 else 462 sc->sc_dc->dc_ramdac_cookie = 463 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 464 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 465 } else { 466 sc->sc_dc->dc_ramdac_cookie = 467 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 468 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 469 470 /* XXX this is a bit of a hack, setting the dotclock here */ 471 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 472 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 473 (sc->sc_dc->dc_ramdac_cookie, 474 tga_getdotclock(sc->sc_dc)); 475 } 476 477 /* 478 * Initialize the RAMDAC. Initialization includes disabling 479 * cursor, setting a sane colormap, etc. We presume that we've 480 * filled in the necessary dot clock for PowerStorm 4d20. 481 */ 482 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 483 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 484 485 if (sc->sc_dc->dc_tgaconf == NULL) { 486 printf("unknown board configuration\n"); 487 return; 488 } 489 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 490 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", device_xname(&sc->sc_dev), 491 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 492 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 493 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 494 495 if (intrstr != NULL) 496 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), 497 intrstr); 498 499 aa.console = console; 500 aa.scrdata = &tga_screenlist; 501 aa.accessops = &tga_accessops; 502 aa.accesscookie = sc; 503 504 config_found(self, &aa, wsemuldisplaydevprint); 505 506 config_interrupts(self, tga_config_interrupts); 507 } 508 509 static void 510 tga_config_interrupts (struct device *d) 511 { 512 struct tga_softc *sc = (struct tga_softc *)d; 513 sc->sc_dc->dc_intrenabled = 1; 514 } 515 516 int 517 tga_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 518 { 519 struct tga_softc *sc = v; 520 struct tga_devconfig *dc = sc->sc_dc; 521 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 522 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 523 524 switch (cmd) { 525 case WSDISPLAYIO_GTYPE: 526 *(u_int *)data = WSDISPLAY_TYPE_TGA; 527 return (0); 528 529 case WSDISPLAYIO_GINFO: 530 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 531 wsd_fbip->height = sc->sc_dc->dc_ht; 532 wsd_fbip->width = sc->sc_dc->dc_wid; 533 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 534 #if 0 535 wsd_fbip->cmsize = 256; /* XXX ??? */ 536 #else 537 wsd_fbip->cmsize = 1024; /* XXX ??? */ 538 #endif 539 #undef wsd_fbip 540 return (0); 541 542 case WSDISPLAYIO_GETCMAP: 543 return (*dcrf->ramdac_get_cmap)(dcrc, 544 (struct wsdisplay_cmap *)data); 545 546 case WSDISPLAYIO_PUTCMAP: 547 return (*dcrf->ramdac_set_cmap)(dcrc, 548 (struct wsdisplay_cmap *)data); 549 550 case WSDISPLAYIO_SVIDEO: 551 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 552 tga_blank(sc->sc_dc); 553 else 554 tga_unblank(sc->sc_dc); 555 return (0); 556 557 case WSDISPLAYIO_GVIDEO: 558 *(u_int *)data = dc->dc_blanked ? 559 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 560 return (0); 561 562 case WSDISPLAYIO_GCURPOS: 563 return (*dcrf->ramdac_get_curpos)(dcrc, 564 (struct wsdisplay_curpos *)data); 565 566 case WSDISPLAYIO_SCURPOS: 567 return (*dcrf->ramdac_set_curpos)(dcrc, 568 (struct wsdisplay_curpos *)data); 569 570 case WSDISPLAYIO_GCURMAX: 571 return (*dcrf->ramdac_get_curmax)(dcrc, 572 (struct wsdisplay_curpos *)data); 573 574 case WSDISPLAYIO_GCURSOR: 575 return (*dcrf->ramdac_get_cursor)(dcrc, 576 (struct wsdisplay_cursor *)data); 577 578 case WSDISPLAYIO_SCURSOR: 579 return (*dcrf->ramdac_set_cursor)(dcrc, 580 (struct wsdisplay_cursor *)data); 581 582 case WSDISPLAYIO_LINEBYTES: 583 *(u_int *)data = dc->dc_rowbytes; 584 return (0); 585 586 /* PCI config read/write passthrough. */ 587 case PCI_IOC_CFGREAD: 588 case PCI_IOC_CFGWRITE: 589 return (pci_devioctl(dc->dc_pc, dc->dc_pcitag, 590 cmd, data, flag, l)); 591 } 592 return (EPASSTHROUGH); 593 } 594 595 static int 596 tga_sched_update(void *v, void (*f)(void *)) 597 { 598 struct tga_devconfig *dc = v; 599 600 if (dc->dc_intrenabled) { 601 /* Arrange for f to be called at the next end-of-frame interrupt */ 602 dc->dc_ramdac_intr = f; 603 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 604 } else { 605 /* Spin until the end-of-frame, then call f */ 606 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 607 TGAREGWB(dc, TGA_REG_SISR, 1); 608 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 609 ; 610 f(dc->dc_ramdac_cookie); 611 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 612 TGAREGWB(dc, TGA_REG_SISR, 1); 613 } 614 615 return 0; 616 } 617 618 static int 619 tga_intr(void *v) 620 { 621 struct tga_devconfig *dc = v; 622 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 623 624 u_int32_t reg; 625 626 reg = TGARREG(dc, TGA_REG_SISR); 627 if (( reg & 0x00010001) != 0x00010001) { 628 /* Odd. We never set any of the other interrupt enables. */ 629 if ((reg & 0x1f) != 0) { 630 /* Clear the mysterious pending interrupts. */ 631 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 632 TGAREGWB(dc, TGA_REG_SISR, 1); 633 /* This was our interrupt, even if we're puzzled as to why 634 * we got it. Don't make the interrupt handler think it 635 * was a stray. 636 */ 637 return -1; 638 } else { 639 return 0; 640 } 641 } 642 /* if we have something to do, do it */ 643 if (dc->dc_ramdac_intr) { 644 dc->dc_ramdac_intr(dcrc); 645 dc->dc_ramdac_intr = NULL; 646 } 647 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 648 TGAREGWB(dc, TGA_REG_SISR, 1); 649 return (1); 650 } 651 652 paddr_t 653 tga_mmap(void *v, void *vs, off_t offset, int prot) 654 { 655 struct tga_softc *sc = v; 656 657 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 658 return -1; 659 660 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 661 offset, prot, BUS_SPACE_MAP_LINEAR)); 662 } 663 664 static int 665 tga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, int *curxp, int *curyp, long *attrp) 666 { 667 struct tga_softc *sc = v; 668 long defattr; 669 670 if (sc->nscreens > 0) 671 return (ENOMEM); 672 673 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 674 *curxp = 0; 675 *curyp = 0; 676 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 677 0, 0, 0, &defattr); 678 *attrp = defattr; 679 sc->nscreens++; 680 return (0); 681 } 682 683 static void 684 tga_free_screen(void *v, void *cookie) 685 { 686 struct tga_softc *sc = v; 687 688 if (sc->sc_dc == &tga_console_dc) 689 panic("tga_free_screen: console"); 690 691 sc->nscreens--; 692 } 693 694 static int 695 tga_show_screen(void *v, void *cookie, int waitok, void (*cb)(void *, int, int), void *cbarg) 696 { 697 698 return (0); 699 } 700 701 int 702 tga_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc, int bus, int device, int function) 703 { 704 struct tga_devconfig *dcp = &tga_console_dc; 705 long defattr; 706 707 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 708 709 /* sanity checks */ 710 if (dcp->dc_vaddr == 0) 711 panic("tga_console(%d, %d): couldn't map memory space", 712 device, function); 713 if (dcp->dc_tgaconf == NULL) 714 panic("tga_console(%d, %d): unknown board configuration", 715 device, function); 716 717 /* 718 * Initialize the RAMDAC but DO NOT allocate any private storage. 719 * Initialization includes disabling cursor, setting a sane 720 * colormap, etc. It will be reinitialized in tgaattach(). 721 */ 722 if (dcp->dc_tga2) { 723 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 724 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 725 tga2_ramdac_rd); 726 else 727 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 728 tga2_ramdac_rd, tga_getdotclock(dcp)); 729 } else { 730 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 731 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 732 tga_ramdac_rd); 733 else { 734 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 735 tga_bt463_rd); 736 } 737 } 738 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 739 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 740 741 return(0); 742 } 743 744 /* 745 * Functions to blank and unblank the display. 746 */ 747 static void 748 tga_blank(struct tga_devconfig *dc) 749 { 750 751 if (!dc->dc_blanked) { 752 dc->dc_blanked = 1; 753 /* XXX */ 754 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 755 } 756 } 757 758 static void 759 tga_unblank(struct tga_devconfig *dc) 760 { 761 762 if (dc->dc_blanked) { 763 dc->dc_blanked = 0; 764 /* XXX */ 765 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 766 } 767 } 768 769 /* 770 * Functions to manipulate the built-in cursor handing hardware. 771 */ 772 int 773 tga_builtin_set_cursor(struct tga_devconfig *dc, struct wsdisplay_cursor *cursorp) 774 { 775 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 776 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 777 u_char image[512]; 778 u_int count, v; 779 int error; 780 781 v = cursorp->which; 782 if (v & WSDISPLAY_CURSOR_DOCMAP) { 783 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 784 if (error) 785 return (error); 786 } 787 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 788 if ((u_int)cursorp->size.x != 64 || 789 (u_int)cursorp->size.y > 64) 790 return (EINVAL); 791 /* The cursor is 2 bits deep, and there is no mask */ 792 count = (cursorp->size.y * 64 * 2) / NBBY; 793 error = copyin(cursorp->image, image, count); 794 if (error) 795 return error; 796 } 797 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 798 return EINVAL; 799 800 /* parameters are OK; do it */ 801 if (v & WSDISPLAY_CURSOR_DOCUR) { 802 if (cursorp->enable) 803 /* XXX */ 804 TGAWREG(dc, TGA_REG_VVVR, 805 TGARREG(dc, TGA_REG_VVVR) | 0x04); 806 else 807 /* XXX */ 808 TGAWREG(dc, TGA_REG_VVVR, 809 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 810 } 811 if (v & WSDISPLAY_CURSOR_DOPOS) { 812 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 813 (cursorp->pos.x & 0xfff)); 814 } 815 if (v & WSDISPLAY_CURSOR_DOCMAP) { 816 dcrf->ramdac_set_curcmap(dcrc, cursorp); 817 } 818 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 819 count = ((64 * 2) / NBBY) * cursorp->size.y; 820 TGAWREG(dc, TGA_REG_CCBR, 821 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 822 (cursorp->size.y << 10)); 823 memcpy((char *)(dc->dc_vaddr + 824 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 825 image, count); 826 } 827 return (0); 828 } 829 830 int 831 tga_builtin_get_cursor(struct tga_devconfig *dc, struct wsdisplay_cursor *cursorp) 832 { 833 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 834 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 835 int count, error; 836 837 cursorp->which = WSDISPLAY_CURSOR_DOALL & 838 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 839 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 840 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 841 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 842 cursorp->size.x = 64; 843 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 844 845 if (cursorp->image != NULL) { 846 count = (cursorp->size.y * 64 * 2) / NBBY; 847 error = copyout((char *)(dc->dc_vaddr + 848 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 849 cursorp->image, count); 850 if (error) 851 return (error); 852 /* No mask */ 853 } 854 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 855 return (error); 856 } 857 858 int 859 tga_builtin_set_curpos(struct tga_devconfig *dc, struct wsdisplay_curpos *curposp) 860 { 861 862 TGAWREG(dc, TGA_REG_CXYR, 863 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 864 return (0); 865 } 866 867 int 868 tga_builtin_get_curpos(struct tga_devconfig *dc, struct wsdisplay_curpos *curposp) 869 { 870 871 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 872 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 873 return (0); 874 } 875 876 int 877 tga_builtin_get_curmax(struct tga_devconfig *dc, struct wsdisplay_curpos *curposp) 878 { 879 880 curposp->x = curposp->y = 64; 881 return (0); 882 } 883 884 /* 885 * Copy columns (characters) in a row (line). 886 */ 887 static void 888 tga_copycols(void *id, int row, int srccol, int dstcol, int ncols) 889 { 890 struct rasops_info *ri = id; 891 int y, srcx, dstx, nx; 892 893 y = ri->ri_font->fontheight * row; 894 srcx = ri->ri_font->fontwidth * srccol; 895 dstx = ri->ri_font->fontwidth * dstcol; 896 nx = ri->ri_font->fontwidth * ncols; 897 898 tga_rop(ri, dstx, y, 899 nx, ri->ri_font->fontheight, RAS_SRC, 900 ri, srcx, y); 901 } 902 903 /* 904 * Copy rows (lines). 905 */ 906 static void 907 tga_copyrows(void *id, int srcrow, int dstrow, int nrows) 908 { 909 struct rasops_info *ri = id; 910 int srcy, dsty, ny; 911 912 srcy = ri->ri_font->fontheight * srcrow; 913 dsty = ri->ri_font->fontheight * dstrow; 914 ny = ri->ri_font->fontheight * nrows; 915 916 tga_rop(ri, 0, dsty, 917 ri->ri_emuwidth, ny, RAS_SRC, 918 ri, 0, srcy); 919 } 920 921 /* Do we need the src? */ 922 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 923 924 /* A mapping between our API and the TGA card */ 925 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 926 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 927 }; 928 929 /* 930 * Generic TGA raster op. 931 * This covers all possible raster ops, and 932 * clips the sizes and all of that. 933 */ 934 static int 935 tga_rop(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, struct rasops_info *src, int sx, int sy) 936 { 937 if (!dst) 938 return -1; 939 if (needsrc[RAS_GETOP(rop)]) { 940 if (src == NULL) 941 return -1; /* We want a src */ 942 /* Clip against src */ 943 if (sx < 0) { 944 w += sx; 945 sx = 0; 946 } 947 if (sy < 0) { 948 h += sy; 949 sy = 0; 950 } 951 if (sx + w > src->ri_emuwidth) 952 w = src->ri_emuwidth - sx; 953 if (sy + h > src->ri_emuheight) 954 h = src->ri_emuheight - sy; 955 } else { 956 if (src != NULL) 957 return -1; /* We need no src */ 958 } 959 /* Clip against dst. We modify src regardless of using it, 960 * since it really doesn't matter. 961 */ 962 if (dx < 0) { 963 w += dx; 964 sx -= dx; 965 dx = 0; 966 } 967 if (dy < 0) { 968 h += dy; 969 sy -= dy; 970 dy = 0; 971 } 972 if (dx + w > dst->ri_emuwidth) 973 w = dst->ri_emuwidth - dx; 974 if (dy + h > dst->ri_emuheight) 975 h = dst->ri_emuheight - dy; 976 if (w <= 0 || h <= 0) 977 return 0; /* Vacuously true; */ 978 if (!src) { 979 /* XXX Punt! */ 980 return -1; 981 } 982 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 983 } 984 985 986 987 /* 988 * Video to Video raster ops. 989 * This function deals with all raster ops that have a src and dst 990 * that are on the card. 991 */ 992 static int 993 tga_rop_vtov(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, struct rasops_info *src, int sx, int sy) 994 { 995 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 996 int srcb, dstb, tga_srcb, tga_dstb; 997 int x, y, wb; 998 int xstart, xend, xdir; 999 int ystart, yend, ydir, yinc; 1000 int xleft, lastx, lastleft; 1001 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1002 1003 /* 1004 * I don't yet want to deal with unaligned guys, really. And we don't 1005 * deal with copies from one card to another. 1006 */ 1007 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1008 /* XXX Punt! */ 1009 /* XXX should never happen, since it's only being used to 1010 * XXX copy 8-pixel-wide characters. 1011 */ 1012 return -1; 1013 } 1014 1015 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1016 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1017 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1018 (sx + src->ri_xorigin) * (src->ri_depth/8); 1019 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1020 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1021 1022 if (sy >= dy) { 1023 ystart = 0; 1024 yend = (h - 1) * dst->ri_stride; 1025 ydir = 1; 1026 } else { 1027 ystart = (h - 1) * dst->ri_stride; 1028 yend = 0; 1029 ydir = -1; 1030 } 1031 yinc = ydir * dst->ri_stride; 1032 1033 wb = w * (dst->ri_depth / 8); 1034 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1035 xstart = 0; 1036 xend = wb; 1037 xdir = 1; 1038 } else { /* copy backwards */ 1039 xstart = wb; 1040 xend = 0; 1041 xdir = -1; 1042 } 1043 1044 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1045 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1046 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1047 1048 /* 1049 * we have 3 sizes of pixels to move in X direction: 1050 * 4 * 64 (unrolled TGA ops) 1051 * 64 (single TGA op) 1052 * 4 (CPU, using long word) 1053 */ 1054 1055 if (xdir == 1) { /* move to the left */ 1056 1057 if (wb & ~63) 1058 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1059 /* 4*64 byte chunks */ 1060 for (xleft = wb, x = xstart; xleft >= 4*64; 1061 x += 4*64, xleft -= 4*64) { 1062 1063 /* XXX XXX Eight writes to different addresses should fill 1064 * XXX XXX up the write buffers on 21064 and 21164 chips, 1065 * XXX XXX but later CPUs might have larger write buffers which 1066 * XXX XXX require further unrolling of this loop, or the 1067 * XXX XXX insertion of memory barriers. 1068 */ 1069 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1070 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1071 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1072 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1073 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1074 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1075 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1076 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1077 } 1078 1079 /* 64 byte chunks */ 1080 for (; xleft >= 64; x += 64, xleft -= 64) { 1081 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1082 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1083 } 1084 } 1085 1086 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1087 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1088 1089 lastleft = wb & 63; 1090 if (lastleft) { 1091 lastx = xstart + (wb & ~63); 1092 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1093 /* 4 byte granularity */ 1094 for (x = lastx, xleft = lastleft; xleft >= 4; 1095 x += 4, xleft -= 4) { 1096 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1097 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1098 } 1099 } 1100 } 1101 } 1102 else { /* above move to the left, below move to the right */ 1103 1104 if (wb & ~63) 1105 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1106 /* 4*64 byte chunks */ 1107 for (xleft = wb, x = xstart; xleft >= 4*64; 1108 x -= 4*64, xleft -= 4*64) { 1109 1110 /* XXX XXX Eight writes to different addresses should fill 1111 * XXX XXX up the write buffers on 21064 and 21164 chips, 1112 * XXX XXX but later CPUs might have larger write buffers which 1113 * XXX XXX require further unrolling of this loop, or the 1114 * XXX XXX insertion of memory barriers. 1115 */ 1116 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1117 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1118 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1119 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1120 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1121 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1122 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1123 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1124 } 1125 1126 /* 64 byte chunks */ 1127 for (; xleft >= 64; x -= 64, xleft -= 64) { 1128 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1129 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1130 } 1131 } 1132 1133 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1134 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1135 1136 lastleft = wb & 63; 1137 if (lastleft) { 1138 lastx = xstart - (wb & ~63); 1139 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1140 /* 4 byte granularity */ 1141 for (x = lastx, xleft = lastleft; xleft >= 4; 1142 x -= 4, xleft -= 4) { 1143 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1144 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1145 } 1146 } 1147 } 1148 } 1149 return 0; 1150 } 1151 1152 1153 void tga_putchar (c, row, col, uc, attr) 1154 void *c; 1155 int row, col; 1156 u_int uc; 1157 long attr; 1158 { 1159 struct rasops_info *ri = c; 1160 struct tga_devconfig *dc = ri->ri_hw; 1161 int fs, height, width; 1162 u_char *fr; 1163 int32_t *rp; 1164 1165 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1166 1167 height = ri->ri_font->fontheight; 1168 width = ri->ri_font->fontwidth; 1169 1170 uc -= ri->ri_font->firstchar; 1171 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1172 fs = ri->ri_font->stride; 1173 1174 /* Set foreground and background color. XXX memoize this somehow? 1175 * The rasops code has already expanded the color entry to 32 bits 1176 * for us, even for 8-bit displays, so we don't have to do anything. 1177 */ 1178 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1179 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1180 1181 /* Set raster operation to "copy"... */ 1182 if (ri->ri_depth == 8) 1183 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1184 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1185 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1186 1187 /* Set which pixels we're drawing (of a possible 32). */ 1188 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1189 1190 /* Set drawing mode to opaque stipple. */ 1191 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1192 1193 /* Insert write barrier before actually sending data */ 1194 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1195 TGAREGWB(dc, TGA_REG_GMOR, 1); 1196 1197 while(height--) { 1198 /* The actual stipple write */ 1199 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1200 1201 fr += fs; 1202 rp = (int32_t *)((char *)rp + ri->ri_stride); 1203 } 1204 1205 /* Do underline */ 1206 if ((attr & 1) != 0) { 1207 rp = (int32_t *)((char *)rp - (ri->ri_stride << 1)); 1208 *rp = 0xffffffff; 1209 } 1210 1211 /* Set grapics mode back to normal. */ 1212 TGAWREG(dc, TGA_REG_GMOR, 0); 1213 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1214 1215 } 1216 1217 static void 1218 tga_eraserows(void *c, int row, int num, long attr) 1219 { 1220 struct rasops_info *ri = c; 1221 struct tga_devconfig *dc = ri->ri_hw; 1222 int32_t color, lines, pixels; 1223 int32_t *rp; 1224 1225 color = ri->ri_devcmap[(attr >> 16) & 15]; 1226 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1227 lines = num * ri->ri_font->fontheight; 1228 pixels = ri->ri_emuwidth - 1; 1229 1230 /* Set fill color in block-color registers */ 1231 TGAWREG(dc, TGA_REG_GBCR0, color); 1232 TGAWREG(dc, TGA_REG_GBCR1, color); 1233 if (ri->ri_depth != 8) { 1234 TGAWREG(dc, TGA_REG_GBCR2, color); 1235 TGAWREG(dc, TGA_REG_GBCR3, color); 1236 TGAWREG(dc, TGA_REG_GBCR4, color); 1237 TGAWREG(dc, TGA_REG_GBCR5, color); 1238 TGAWREG(dc, TGA_REG_GBCR6, color); 1239 TGAWREG(dc, TGA_REG_GBCR7, color); 1240 } 1241 1242 /* Set raster operation to "copy"... */ 1243 if (ri->ri_depth == 8) 1244 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1245 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1246 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1247 1248 /* Set which pixels we're drawing (of a possible 32). */ 1249 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1250 1251 /* Set drawing mode to block fill. */ 1252 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1253 1254 /* Insert write barrier before actually sending data */ 1255 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1256 TGAREGWB(dc, TGA_REG_GMOR, 1); 1257 1258 while (lines--) { 1259 *rp = pixels; 1260 rp = (int32_t *)((char *)rp + ri->ri_stride); 1261 } 1262 1263 /* Set grapics mode back to normal. */ 1264 TGAWREG(dc, TGA_REG_GMOR, 0); 1265 1266 } 1267 1268 static void 1269 tga_erasecols (void *c, int row, int col, int num, long attr) 1270 { 1271 struct rasops_info *ri = c; 1272 struct tga_devconfig *dc = ri->ri_hw; 1273 int32_t color, lines, pixels; 1274 int32_t *rp; 1275 1276 color = ri->ri_devcmap[(attr >> 16) & 15]; 1277 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1278 lines = ri->ri_font->fontheight; 1279 pixels = (num * ri->ri_font->fontwidth) - 1; 1280 1281 /* Set fill color in block-color registers */ 1282 TGAWREG(dc, TGA_REG_GBCR0, color); 1283 TGAWREG(dc, TGA_REG_GBCR1, color); 1284 if (ri->ri_depth != 8) { 1285 TGAWREG(dc, TGA_REG_GBCR2, color); 1286 TGAWREG(dc, TGA_REG_GBCR3, color); 1287 TGAWREG(dc, TGA_REG_GBCR4, color); 1288 TGAWREG(dc, TGA_REG_GBCR5, color); 1289 TGAWREG(dc, TGA_REG_GBCR6, color); 1290 TGAWREG(dc, TGA_REG_GBCR7, color); 1291 } 1292 1293 /* Set raster operation to "copy"... */ 1294 if (ri->ri_depth == 8) 1295 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1296 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1297 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1298 1299 /* Set which pixels we're drawing (of a possible 32). */ 1300 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1301 1302 /* Set drawing mode to block fill. */ 1303 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1304 1305 /* Insert write barrier before actually sending data */ 1306 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1307 TGAREGWB(dc, TGA_REG_GMOR, 1); 1308 1309 while (lines--) { 1310 *rp = pixels; 1311 rp = (int32_t *)((char *)rp + ri->ri_stride); 1312 } 1313 1314 /* Set grapics mode back to normal. */ 1315 TGAWREG(dc, TGA_REG_GMOR, 0); 1316 } 1317 1318 1319 static void 1320 tga_ramdac_wr(void *v, u_int btreg, u_int8_t val) 1321 { 1322 struct tga_devconfig *dc = v; 1323 1324 if (btreg > BT485_REG_MAX) 1325 panic("tga_ramdac_wr: reg %d out of range", btreg); 1326 1327 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1328 TGAREGWB(dc, TGA_REG_EPDR, 1); 1329 } 1330 1331 static void 1332 tga2_ramdac_wr(void *v, u_int btreg, u_int8_t val) 1333 { 1334 struct tga_devconfig *dc = v; 1335 bus_space_handle_t ramdac; 1336 1337 if (btreg > BT485_REG_MAX) 1338 panic("tga_ramdac_wr: reg %d out of range", btreg); 1339 1340 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1341 (0xe << 12) + (btreg << 8), 4, &ramdac); 1342 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1343 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1344 } 1345 1346 static u_int8_t 1347 tga_bt463_rd(void *v, u_int btreg) 1348 { 1349 struct tga_devconfig *dc = v; 1350 tga_reg_t rdval; 1351 1352 /* 1353 * Strobe CE# (high->low->high) since status and data are latched on 1354 * the falling and rising edges (repsectively) of this active-low signal. 1355 */ 1356 1357 TGAREGWB(dc, TGA_REG_EPSR, 1); 1358 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1359 TGAREGWB(dc, TGA_REG_EPSR, 1); 1360 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1361 1362 TGAREGRB(dc, TGA_REG_EPSR, 1); 1363 1364 rdval = TGARREG(dc, TGA_REG_EPDR); 1365 TGAREGWB(dc, TGA_REG_EPSR, 1); 1366 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1367 1368 return (rdval >> 16) & 0xff; 1369 } 1370 1371 static void 1372 tga_bt463_wr(void *v, u_int btreg, u_int8_t val) 1373 { 1374 struct tga_devconfig *dc = v; 1375 1376 /* 1377 * In spite of the 21030 documentation, to set the MPU bus bits for 1378 * a write, you set them in the upper bits of EPDR, not EPSR. 1379 */ 1380 1381 /* 1382 * Strobe CE# (high->low->high) since status and data are latched on 1383 * the falling and rising edges of this active-low signal. 1384 */ 1385 1386 TGAREGWB(dc, TGA_REG_EPDR, 1); 1387 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1388 TGAREGWB(dc, TGA_REG_EPDR, 1); 1389 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1390 TGAREGWB(dc, TGA_REG_EPDR, 1); 1391 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1392 1393 } 1394 1395 static u_int8_t 1396 tga_ramdac_rd(void *v, u_int btreg) 1397 { 1398 struct tga_devconfig *dc = v; 1399 tga_reg_t rdval; 1400 1401 if (btreg > BT485_REG_MAX) 1402 panic("tga_ramdac_rd: reg %d out of range", btreg); 1403 1404 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1405 TGAREGWB(dc, TGA_REG_EPSR, 1); 1406 1407 rdval = TGARREG(dc, TGA_REG_EPDR); 1408 return (rdval >> 16) & 0xff; /* XXX */ 1409 } 1410 1411 static u_int8_t 1412 tga2_ramdac_rd(void *v, u_int btreg) 1413 { 1414 struct tga_devconfig *dc = v; 1415 bus_space_handle_t ramdac; 1416 u_int8_t retval; 1417 1418 if (btreg > BT485_REG_MAX) 1419 panic("tga_ramdac_rd: reg %d out of range", btreg); 1420 1421 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1422 (0xe << 12) + (btreg << 8), 4, &ramdac); 1423 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1424 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1425 return retval; 1426 } 1427 1428 #include <dev/ic/decmonitors.c> 1429 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1430 1431 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1432 1433 void 1434 tga2_init(struct tga_devconfig *dc) 1435 { 1436 struct monitor *m = tga_getmonitor(dc); 1437 1438 /* Deal with the dot clocks. 1439 */ 1440 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1441 /* Set this up as a reference clock for the 1442 * ibm561's PLL. 1443 */ 1444 tga2_ics9110_wr(dc, 14300000); 1445 /* XXX Can't set up the dotclock properly, until such time 1446 * as the RAMDAC is configured. 1447 */ 1448 } else { 1449 /* otherwise the ics9110 is our clock. */ 1450 tga2_ics9110_wr(dc, m->dotclock); 1451 } 1452 #if 0 1453 TGAWREG(dc, TGA_REG_VHCR, 1454 ((m->hbp / 4) << 21) | 1455 ((m->hsync / 4) << 14) | 1456 (((m->hfp - 4) / 4) << 9) | 1457 ((m->cols + 4) / 4)); 1458 #else 1459 TGAWREG(dc, TGA_REG_VHCR, 1460 ((m->hbp / 4) << 21) | 1461 ((m->hsync / 4) << 14) | 1462 (((m->hfp) / 4) << 9) | 1463 ((m->cols) / 4)); 1464 #endif 1465 TGAWREG(dc, TGA_REG_VVCR, 1466 (m->vbp << 22) | 1467 (m->vsync << 16) | 1468 (m->vfp << 11) | 1469 (m->rows)); 1470 TGAWREG(dc, TGA_REG_VVBR, 1); 1471 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1472 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1473 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1474 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1475 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1476 } 1477 1478 void 1479 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock) 1480 { 1481 bus_space_handle_t clock; 1482 u_int32_t valU; 1483 int N, M, R, V, X; 1484 int i; 1485 1486 switch (dotclock) { 1487 case 130808000: 1488 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1489 case 119840000: 1490 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1491 case 108180000: 1492 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1493 case 103994000: 1494 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1495 case 175000000: 1496 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1497 case 75000000: 1498 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1499 case 74000000: 1500 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1501 case 69000000: 1502 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1503 case 65000000: 1504 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1505 case 50000000: 1506 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1507 case 40000000: 1508 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1509 case 31500000: 1510 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1511 case 25175000: 1512 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1513 case 135000000: 1514 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1515 case 110000000: 1516 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1517 case 202500000: 1518 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1519 case 14300000: /* this one is just a ref clock */ 1520 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1521 default: 1522 panic("unrecognized clock rate %d", dotclock); 1523 } 1524 1525 /* XXX -- hard coded, bad */ 1526 valU = N | ( M << 7 ) | (V << 14); 1527 valU |= (X << 15) | (R << 17); 1528 valU |= 0x17 << 19; 1529 1530 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1531 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1532 1533 for (i=24; i>0; i--) { 1534 u_int32_t writeval; 1535 1536 writeval = valU & 0x1; 1537 if (i == 1) 1538 writeval |= 0x2; 1539 valU >>= 1; 1540 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1541 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1542 } 1543 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1544 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1545 &clock); /* XXX */ 1546 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1547 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1548 } 1549 1550 struct monitor * 1551 tga_getmonitor(struct tga_devconfig *dc) 1552 { 1553 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1554 } 1555 1556 unsigned 1557 tga_getdotclock(struct tga_devconfig *dc) 1558 { 1559 return tga_getmonitor(dc)->dotclock; 1560 } 1561