1 /* $NetBSD: tga.c,v 1.58 2004/06/29 21:32:42 kleink Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.58 2004/06/29 21:32:42 kleink Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 int tgamatch __P((struct device *, struct cfdata *, void *)); 63 void tgaattach __P((struct device *, struct device *, void *)); 64 int tgaprint __P((void *, const char *)); 65 66 CFATTACH_DECL(tga, sizeof(struct tga_softc), 67 tgamatch, tgaattach, NULL, NULL); 68 69 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 70 pcitag_t tag, struct tga_devconfig *dc)); 71 72 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 73 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 74 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 75 unsigned tga_getdotclock __P((struct tga_devconfig *dc)); 76 77 struct tga_devconfig tga_console_dc; 78 79 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 80 paddr_t tga_mmap __P((void *, off_t, int)); 81 static void tga_copyrows __P((void *, int, int, int)); 82 static void tga_copycols __P((void *, int, int, int, int)); 83 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 84 void **, int *, int *, long *)); 85 static void tga_free_screen __P((void *, void *)); 86 static int tga_show_screen __P((void *, void *, int, 87 void (*) (void *, int, int), void *)); 88 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 89 struct rasops_info *, int, int)); 90 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 91 int, struct rasops_info *, int, int )); 92 static void tga_putchar __P((void *c, int row, int col, 93 u_int uc, long attr)); 94 static void tga_eraserows __P((void *, int, int, long)); 95 static void tga_erasecols __P((void *, int, int, int, long)); 96 void tga2_init __P((struct tga_devconfig *)); 97 98 static void tga_config_interrupts __P((struct device *)); 99 100 /* RAMDAC interface functions */ 101 static int tga_sched_update __P((void *, void (*)(void *))); 102 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 103 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 104 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 105 static u_int8_t tga_bt463_rd __P((void *, u_int)); 106 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 107 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 108 109 /* Interrupt handler */ 110 static int tga_intr __P((void *)); 111 112 /* The NULL entries will get filled in by rasops_init(). 113 * XXX and the non-NULL ones will be overwritten; reset after calling it. 114 */ 115 struct wsdisplay_emulops tga_emulops = { 116 NULL, 117 NULL, 118 tga_putchar, 119 tga_copycols, 120 tga_erasecols, 121 tga_copyrows, 122 tga_eraserows, 123 NULL, 124 }; 125 126 struct wsscreen_descr tga_stdscreen = { 127 "std", 128 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 129 &tga_emulops, 130 0, 0, 131 WSSCREEN_REVERSE 132 }; 133 134 const struct wsscreen_descr *_tga_scrlist[] = { 135 &tga_stdscreen, 136 /* XXX other formats, graphics screen? */ 137 }; 138 139 struct wsscreen_list tga_screenlist = { 140 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 141 }; 142 143 struct wsdisplay_accessops tga_accessops = { 144 tga_ioctl, 145 tga_mmap, 146 tga_alloc_screen, 147 tga_free_screen, 148 tga_show_screen, 149 0 /* load_font */ 150 }; 151 152 static void tga_blank __P((struct tga_devconfig *)); 153 static void tga_unblank __P((struct tga_devconfig *)); 154 155 int 156 tga_cnmatch(iot, memt, pc, tag) 157 bus_space_tag_t iot, memt; 158 pci_chipset_tag_t pc; 159 pcitag_t tag; 160 { 161 return tga_matchcommon(memt, pc, tag); 162 } 163 164 int 165 tgamatch(parent, match, aux) 166 struct device *parent; 167 struct cfdata *match; 168 void *aux; 169 { 170 struct pci_attach_args *pa = aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 173 return (0); 174 175 switch (PCI_PRODUCT(pa->pa_id)) { 176 case PCI_PRODUCT_DEC_21030: 177 case PCI_PRODUCT_DEC_PBXGB: 178 break; 179 default: 180 return 0; 181 } 182 183 /* short-circuit the following test, as we 184 * already have the memory mapped and hence 185 * cannot perform it---and we are the console 186 * anyway. 187 */ 188 if (pa->pa_tag == tga_console_dc.dc_pcitag) 189 return 10; 190 191 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 192 } 193 194 static int 195 tga_matchcommon(memt, pc, tag) 196 bus_space_tag_t memt; 197 pci_chipset_tag_t pc; 198 pcitag_t tag; 199 { 200 struct tga_devconfig tmp_dc; 201 struct tga_devconfig *dc = &tmp_dc; 202 bus_size_t pcisize; 203 204 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 205 dc->dc_tga_type = tga_identify(dc); 206 207 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 208 bus_space_unmap(memt, dc->dc_memh, pcisize); 209 if (dc->dc_tgaconf) 210 return 10; 211 return 0; 212 } 213 214 static void 215 tga_mapaddrs(memt, pc, tag, pcisize, dc) 216 bus_space_tag_t memt; 217 pci_chipset_tag_t pc; 218 pcitag_t tag; 219 bus_size_t *pcisize; 220 struct tga_devconfig *dc; 221 { 222 int flags; 223 224 dc->dc_memt = memt; 225 dc->dc_tgaconf = NULL; 226 227 /* XXX magic number */ 228 if (pci_mapreg_info(pc, tag, 0x10, 229 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 230 &dc->dc_pcipaddr, pcisize, &flags)) 231 panic("tga_mapaddrs: pci_mapreg_info() failed"); 232 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 233 panic("tga memory not prefetchable"); 234 235 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 236 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 237 panic("tga_mapaddrs: could not map TGA address space"); 238 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 239 240 bus_space_subregion(dc->dc_memt, dc->dc_memh, 241 TGA_MEM_CREGS, TGA_CREGS_SIZE, 242 &dc->dc_regs); 243 } 244 245 static void 246 tga_init(memt, pc, tag, dc) 247 bus_space_tag_t memt; 248 pci_chipset_tag_t pc; 249 pcitag_t tag; 250 struct tga_devconfig *dc; 251 { 252 const struct tga_conf *tgac; 253 struct rasops_info *rip; 254 int cookie; 255 bus_size_t pcisize; 256 int i; 257 258 dc->dc_pcitag = tag; 259 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 260 dc->dc_tga_type = tga_identify(dc); 261 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 262 #if 0 263 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 264 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 265 panic("tga_init: memory size mismatch?"); 266 #endif 267 268 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 269 case 0x01: 270 case 0x02: 271 case 0x03: 272 case 0x04: 273 dc->dc_tga2 = 0; 274 break; 275 case 0x20: 276 case 0x21: 277 case 0x22: 278 dc->dc_tga2 = 1; 279 break; 280 default: 281 panic("tga_init: TGA Revision not recognized"); 282 } 283 284 if (dc->dc_tga2) 285 tga2_init(dc); 286 287 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 288 case 0: 289 dc->dc_wid = 8192; 290 break; 291 292 case 1: 293 dc->dc_wid = 8196; 294 break; 295 296 default: 297 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 298 break; 299 } 300 301 /* 302 * XXX XXX Turning off "odd" shouldn't be necessary, 303 * XXX XXX but I can't make X work with the weird size. 304 */ 305 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 306 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 307 TGAWREG(dc, TGA_REG_VHCR, 308 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 309 dc->dc_wid -= 4; 310 } 311 312 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 313 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 314 315 /* XXX this seems to be what DEC does */ 316 TGAWREG(dc, TGA_REG_CCBR, 0); 317 TGAWREG(dc, TGA_REG_VVBR, 1); 318 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 319 1 * tgac->tgac_vvbr_units; 320 dc->dc_blanked = 1; 321 tga_unblank(dc); 322 323 /* 324 * Set all bits in the pixel mask, to enable writes to all pixels. 325 * It seems that the console firmware clears some of them 326 * under some circumstances, which causes cute vertical stripes. 327 */ 328 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 329 330 /* clear the screen */ 331 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 332 *(u_int32_t *)(dc->dc_videobase + i) = 0; 333 334 /* Initialize rasops descriptor */ 335 rip = &dc->dc_rinfo; 336 rip->ri_flg = RI_CENTER; 337 rip->ri_depth = tgac->tgac_phys_depth; 338 rip->ri_bits = (void *)dc->dc_videobase; 339 rip->ri_width = dc->dc_wid; 340 rip->ri_height = dc->dc_ht; 341 rip->ri_stride = dc->dc_rowbytes; 342 rip->ri_hw = dc; 343 344 if (tgac->tgac_phys_depth == 32) { 345 rip->ri_rnum = 8; 346 rip->ri_gnum = 8; 347 rip->ri_bnum = 8; 348 rip->ri_rpos = 16; 349 rip->ri_gpos = 8; 350 rip->ri_bpos = 0; 351 } 352 353 wsfont_init(); 354 /* prefer 8 pixel wide font */ 355 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 356 WSDISPLAY_FONTORDER_L2R); 357 if (cookie <= 0) 358 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 359 WSDISPLAY_FONTORDER_L2R); 360 if (cookie <= 0) { 361 printf("tga: no appropriate fonts.\n"); 362 return; 363 } 364 365 /* the accelerated tga_putchar() needs LSbit left */ 366 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 367 printf("tga: couldn't lock font\n"); 368 return; 369 } 370 dc->dc_rinfo.ri_wsfcookie = cookie; 371 372 rasops_init(rip, 34, 80); 373 374 /* add our accelerated functions */ 375 /* XXX shouldn't have to do this; rasops should leave non-NULL 376 * XXX entries alone. 377 */ 378 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 379 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 380 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 381 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 382 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 383 384 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 385 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 386 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 387 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 388 389 390 dc->dc_intrenabled = 0; 391 } 392 393 void 394 tgaattach(parent, self, aux) 395 struct device *parent, *self; 396 void *aux; 397 { 398 struct pci_attach_args *pa = aux; 399 struct tga_softc *sc = (struct tga_softc *)self; 400 struct wsemuldisplaydev_attach_args aa; 401 pci_intr_handle_t intrh; 402 const char *intrstr; 403 u_int8_t rev; 404 int console; 405 406 #if defined(__alpha__) || defined(arc) 407 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 408 #else 409 console = 0; 410 #endif 411 if (console) { 412 sc->sc_dc = &tga_console_dc; 413 sc->nscreens = 1; 414 } else { 415 sc->sc_dc = (struct tga_devconfig *) 416 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 417 M_WAITOK|M_ZERO); 418 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 419 } 420 if (sc->sc_dc->dc_vaddr == 0) { 421 printf(": couldn't map memory space; punt!\n"); 422 return; 423 } 424 425 /* XXX say what's going on. */ 426 intrstr = NULL; 427 if (pci_intr_map(pa, &intrh)) { 428 printf(": couldn't map interrupt"); 429 return; 430 } 431 intrstr = pci_intr_string(pa->pa_pc, intrh); 432 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 433 sc->sc_dc); 434 if (sc->sc_intr == NULL) { 435 printf(": couldn't establish interrupt"); 436 if (intrstr != NULL) 437 printf("at %s", intrstr); 438 printf("\n"); 439 return; 440 } 441 442 rev = PCI_REVISION(pa->pa_class); 443 switch (rev) { 444 case 0x1: 445 case 0x2: 446 case 0x3: 447 printf(": DC21030 step %c", 'A' + rev - 1); 448 break; 449 case 0x20: 450 printf(": TGA2 abstract software model"); 451 break; 452 case 0x21: 453 case 0x22: 454 printf(": TGA2 pass %d", rev - 0x20); 455 break; 456 457 default: 458 printf("unknown stepping (0x%x)", rev); 459 break; 460 } 461 printf(", "); 462 463 /* 464 * Get RAMDAC function vectors and call the RAMDAC functions 465 * to allocate its private storage and pass that back to us. 466 */ 467 468 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 469 if (!sc->sc_dc->dc_tga2) { 470 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 471 sc->sc_dc->dc_ramdac_cookie = 472 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 473 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 474 else 475 sc->sc_dc->dc_ramdac_cookie = 476 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 477 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 478 } else { 479 sc->sc_dc->dc_ramdac_cookie = 480 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 481 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 482 483 /* XXX this is a bit of a hack, setting the dotclock here */ 484 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 485 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 486 (sc->sc_dc->dc_ramdac_cookie, 487 tga_getdotclock(sc->sc_dc)); 488 } 489 490 /* 491 * Initialize the RAMDAC. Initialization includes disabling 492 * cursor, setting a sane colormap, etc. We presume that we've 493 * filled in the necessary dot clock for PowerStorm 4d20. 494 */ 495 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 496 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 497 498 if (sc->sc_dc->dc_tgaconf == NULL) { 499 printf("unknown board configuration\n"); 500 return; 501 } 502 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 503 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 504 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 505 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 506 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 507 508 if (intrstr != NULL) 509 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 510 intrstr); 511 512 aa.console = console; 513 aa.scrdata = &tga_screenlist; 514 aa.accessops = &tga_accessops; 515 aa.accesscookie = sc; 516 517 config_found(self, &aa, wsemuldisplaydevprint); 518 519 config_interrupts(self, tga_config_interrupts); 520 } 521 522 static void 523 tga_config_interrupts (d) 524 struct device *d; 525 { 526 struct tga_softc *sc = (struct tga_softc *)d; 527 sc->sc_dc->dc_intrenabled = 1; 528 } 529 530 int 531 tga_ioctl(v, cmd, data, flag, p) 532 void *v; 533 u_long cmd; 534 caddr_t data; 535 int flag; 536 struct proc *p; 537 { 538 struct tga_softc *sc = v; 539 struct tga_devconfig *dc = sc->sc_dc; 540 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 541 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 542 543 switch (cmd) { 544 case WSDISPLAYIO_GTYPE: 545 *(u_int *)data = WSDISPLAY_TYPE_TGA; 546 return (0); 547 548 case WSDISPLAYIO_GINFO: 549 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 550 wsd_fbip->height = sc->sc_dc->dc_ht; 551 wsd_fbip->width = sc->sc_dc->dc_wid; 552 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 553 #if 0 554 wsd_fbip->cmsize = 256; /* XXX ??? */ 555 #else 556 wsd_fbip->cmsize = 1024; /* XXX ??? */ 557 #endif 558 #undef wsd_fbip 559 return (0); 560 561 case WSDISPLAYIO_GETCMAP: 562 return (*dcrf->ramdac_get_cmap)(dcrc, 563 (struct wsdisplay_cmap *)data); 564 565 case WSDISPLAYIO_PUTCMAP: 566 return (*dcrf->ramdac_set_cmap)(dcrc, 567 (struct wsdisplay_cmap *)data); 568 569 case WSDISPLAYIO_SVIDEO: 570 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 571 tga_blank(sc->sc_dc); 572 else 573 tga_unblank(sc->sc_dc); 574 return (0); 575 576 case WSDISPLAYIO_GVIDEO: 577 *(u_int *)data = dc->dc_blanked ? 578 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 579 return (0); 580 581 case WSDISPLAYIO_GCURPOS: 582 return (*dcrf->ramdac_get_curpos)(dcrc, 583 (struct wsdisplay_curpos *)data); 584 585 case WSDISPLAYIO_SCURPOS: 586 return (*dcrf->ramdac_set_curpos)(dcrc, 587 (struct wsdisplay_curpos *)data); 588 589 case WSDISPLAYIO_GCURMAX: 590 return (*dcrf->ramdac_get_curmax)(dcrc, 591 (struct wsdisplay_curpos *)data); 592 593 case WSDISPLAYIO_GCURSOR: 594 return (*dcrf->ramdac_get_cursor)(dcrc, 595 (struct wsdisplay_cursor *)data); 596 597 case WSDISPLAYIO_SCURSOR: 598 return (*dcrf->ramdac_set_cursor)(dcrc, 599 (struct wsdisplay_cursor *)data); 600 } 601 return (EPASSTHROUGH); 602 } 603 604 static int 605 tga_sched_update(v, f) 606 void *v; 607 void (*f) __P((void *)); 608 { 609 struct tga_devconfig *dc = v; 610 611 if (dc->dc_intrenabled) { 612 /* Arrange for f to be called at the next end-of-frame interrupt */ 613 dc->dc_ramdac_intr = f; 614 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 615 } else { 616 /* Spin until the end-of-frame, then call f */ 617 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 618 TGAREGWB(dc, TGA_REG_SISR, 1); 619 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 620 ; 621 f(dc->dc_ramdac_cookie); 622 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 623 TGAREGWB(dc, TGA_REG_SISR, 1); 624 } 625 626 return 0; 627 } 628 629 static int 630 tga_intr(v) 631 void *v; 632 { 633 struct tga_devconfig *dc = v; 634 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 635 636 u_int32_t reg; 637 638 reg = TGARREG(dc, TGA_REG_SISR); 639 if (( reg & 0x00010001) != 0x00010001) { 640 /* Odd. We never set any of the other interrupt enables. */ 641 if ((reg & 0x1f) != 0) { 642 /* Clear the mysterious pending interrupts. */ 643 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 644 TGAREGWB(dc, TGA_REG_SISR, 1); 645 /* This was our interrupt, even if we're puzzled as to why 646 * we got it. Don't make the interrupt handler think it 647 * was a stray. 648 */ 649 return -1; 650 } else { 651 return 0; 652 } 653 } 654 /* if we have something to do, do it */ 655 if (dc->dc_ramdac_intr) { 656 dc->dc_ramdac_intr(dcrc); 657 dc->dc_ramdac_intr = NULL; 658 } 659 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 660 TGAREGWB(dc, TGA_REG_SISR, 1); 661 return (1); 662 } 663 664 paddr_t 665 tga_mmap(v, offset, prot) 666 void *v; 667 off_t offset; 668 int prot; 669 { 670 struct tga_softc *sc = v; 671 672 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 673 return -1; 674 675 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 676 offset, prot, BUS_SPACE_MAP_LINEAR)); 677 } 678 679 static int 680 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 681 void *v; 682 const struct wsscreen_descr *type; 683 void **cookiep; 684 int *curxp, *curyp; 685 long *attrp; 686 { 687 struct tga_softc *sc = v; 688 long defattr; 689 690 if (sc->nscreens > 0) 691 return (ENOMEM); 692 693 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 694 *curxp = 0; 695 *curyp = 0; 696 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 697 0, 0, 0, &defattr); 698 *attrp = defattr; 699 sc->nscreens++; 700 return (0); 701 } 702 703 static void 704 tga_free_screen(v, cookie) 705 void *v; 706 void *cookie; 707 { 708 struct tga_softc *sc = v; 709 710 if (sc->sc_dc == &tga_console_dc) 711 panic("tga_free_screen: console"); 712 713 sc->nscreens--; 714 } 715 716 static int 717 tga_show_screen(v, cookie, waitok, cb, cbarg) 718 void *v; 719 void *cookie; 720 int waitok; 721 void (*cb) __P((void *, int, int)); 722 void *cbarg; 723 { 724 725 return (0); 726 } 727 728 int 729 tga_cnattach(iot, memt, pc, bus, device, function) 730 bus_space_tag_t iot, memt; 731 pci_chipset_tag_t pc; 732 int bus, device, function; 733 { 734 struct tga_devconfig *dcp = &tga_console_dc; 735 long defattr; 736 737 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 738 739 /* sanity checks */ 740 if (dcp->dc_vaddr == 0) 741 panic("tga_console(%d, %d): couldn't map memory space", 742 device, function); 743 if (dcp->dc_tgaconf == NULL) 744 panic("tga_console(%d, %d): unknown board configuration", 745 device, function); 746 747 /* 748 * Initialize the RAMDAC but DO NOT allocate any private storage. 749 * Initialization includes disabling cursor, setting a sane 750 * colormap, etc. It will be reinitialized in tgaattach(). 751 */ 752 if (dcp->dc_tga2) { 753 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 754 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 755 tga2_ramdac_rd); 756 else 757 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 758 tga2_ramdac_rd, tga_getdotclock(dcp)); 759 } else { 760 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 761 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 762 tga_ramdac_rd); 763 else { 764 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 765 tga_bt463_rd); 766 } 767 } 768 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 769 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 770 771 return(0); 772 } 773 774 /* 775 * Functions to blank and unblank the display. 776 */ 777 static void 778 tga_blank(dc) 779 struct tga_devconfig *dc; 780 { 781 782 if (!dc->dc_blanked) { 783 dc->dc_blanked = 1; 784 /* XXX */ 785 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 786 } 787 } 788 789 static void 790 tga_unblank(dc) 791 struct tga_devconfig *dc; 792 { 793 794 if (dc->dc_blanked) { 795 dc->dc_blanked = 0; 796 /* XXX */ 797 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 798 } 799 } 800 801 /* 802 * Functions to manipulate the built-in cursor handing hardware. 803 */ 804 int 805 tga_builtin_set_cursor(dc, cursorp) 806 struct tga_devconfig *dc; 807 struct wsdisplay_cursor *cursorp; 808 { 809 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 810 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 811 u_char image[512]; 812 u_int count, v; 813 int error; 814 815 v = cursorp->which; 816 if (v & WSDISPLAY_CURSOR_DOCMAP) { 817 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 818 if (error) 819 return (error); 820 } 821 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 822 if ((u_int)cursorp->size.x != 64 || 823 (u_int)cursorp->size.y > 64) 824 return (EINVAL); 825 /* The cursor is 2 bits deep, and there is no mask */ 826 count = (cursorp->size.y * 64 * 2) / NBBY; 827 error = copyin(cursorp->image, image, count); 828 if (error) 829 return error; 830 } 831 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 832 return EINVAL; 833 834 /* parameters are OK; do it */ 835 if (v & WSDISPLAY_CURSOR_DOCUR) { 836 if (cursorp->enable) 837 /* XXX */ 838 TGAWREG(dc, TGA_REG_VVVR, 839 TGARREG(dc, TGA_REG_VVVR) | 0x04); 840 else 841 /* XXX */ 842 TGAWREG(dc, TGA_REG_VVVR, 843 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 844 } 845 if (v & WSDISPLAY_CURSOR_DOPOS) { 846 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 847 (cursorp->pos.x & 0xfff)); 848 } 849 if (v & WSDISPLAY_CURSOR_DOCMAP) { 850 dcrf->ramdac_set_curcmap(dcrc, cursorp); 851 } 852 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 853 count = ((64 * 2) / NBBY) * cursorp->size.y; 854 TGAWREG(dc, TGA_REG_CCBR, 855 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 856 (cursorp->size.y << 10)); 857 memcpy((char *)(dc->dc_vaddr + 858 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 859 image, count); 860 } 861 return (0); 862 } 863 864 int 865 tga_builtin_get_cursor(dc, cursorp) 866 struct tga_devconfig *dc; 867 struct wsdisplay_cursor *cursorp; 868 { 869 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 870 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 871 int count, error; 872 873 cursorp->which = WSDISPLAY_CURSOR_DOALL & 874 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 875 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 876 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 877 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 878 cursorp->size.x = 64; 879 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 880 881 if (cursorp->image != NULL) { 882 count = (cursorp->size.y * 64 * 2) / NBBY; 883 error = copyout((char *)(dc->dc_vaddr + 884 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 885 cursorp->image, count); 886 if (error) 887 return (error); 888 /* No mask */ 889 } 890 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 891 return (error); 892 } 893 894 int 895 tga_builtin_set_curpos(dc, curposp) 896 struct tga_devconfig *dc; 897 struct wsdisplay_curpos *curposp; 898 { 899 900 TGAWREG(dc, TGA_REG_CXYR, 901 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 902 return (0); 903 } 904 905 int 906 tga_builtin_get_curpos(dc, curposp) 907 struct tga_devconfig *dc; 908 struct wsdisplay_curpos *curposp; 909 { 910 911 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 912 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 913 return (0); 914 } 915 916 int 917 tga_builtin_get_curmax(dc, curposp) 918 struct tga_devconfig *dc; 919 struct wsdisplay_curpos *curposp; 920 { 921 922 curposp->x = curposp->y = 64; 923 return (0); 924 } 925 926 /* 927 * Copy columns (characters) in a row (line). 928 */ 929 static void 930 tga_copycols(id, row, srccol, dstcol, ncols) 931 void *id; 932 int row, srccol, dstcol, ncols; 933 { 934 struct rasops_info *ri = id; 935 int y, srcx, dstx, nx; 936 937 y = ri->ri_font->fontheight * row; 938 srcx = ri->ri_font->fontwidth * srccol; 939 dstx = ri->ri_font->fontwidth * dstcol; 940 nx = ri->ri_font->fontwidth * ncols; 941 942 tga_rop(ri, dstx, y, 943 nx, ri->ri_font->fontheight, RAS_SRC, 944 ri, srcx, y); 945 } 946 947 /* 948 * Copy rows (lines). 949 */ 950 static void 951 tga_copyrows(id, srcrow, dstrow, nrows) 952 void *id; 953 int srcrow, dstrow, nrows; 954 { 955 struct rasops_info *ri = id; 956 int srcy, dsty, ny; 957 958 srcy = ri->ri_font->fontheight * srcrow; 959 dsty = ri->ri_font->fontheight * dstrow; 960 ny = ri->ri_font->fontheight * nrows; 961 962 tga_rop(ri, 0, dsty, 963 ri->ri_emuwidth, ny, RAS_SRC, 964 ri, 0, srcy); 965 } 966 967 /* Do we need the src? */ 968 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 969 970 /* A mapping between our API and the TGA card */ 971 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 972 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 973 }; 974 975 /* 976 * Generic TGA raster op. 977 * This covers all possible raster ops, and 978 * clips the sizes and all of that. 979 */ 980 static int 981 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 982 struct rasops_info *dst; 983 int dx, dy, w, h, rop; 984 struct rasops_info *src; 985 int sx, sy; 986 { 987 if (!dst) 988 return -1; 989 if (needsrc[RAS_GETOP(rop)]) { 990 if (src == NULL) 991 return -1; /* We want a src */ 992 /* Clip against src */ 993 if (sx < 0) { 994 w += sx; 995 sx = 0; 996 } 997 if (sy < 0) { 998 h += sy; 999 sy = 0; 1000 } 1001 if (sx + w > src->ri_emuwidth) 1002 w = src->ri_emuwidth - sx; 1003 if (sy + h > src->ri_emuheight) 1004 h = src->ri_emuheight - sy; 1005 } else { 1006 if (src != NULL) 1007 return -1; /* We need no src */ 1008 } 1009 /* Clip against dst. We modify src regardless of using it, 1010 * since it really doesn't matter. 1011 */ 1012 if (dx < 0) { 1013 w += dx; 1014 sx -= dx; 1015 dx = 0; 1016 } 1017 if (dy < 0) { 1018 h += dy; 1019 sy -= dy; 1020 dy = 0; 1021 } 1022 if (dx + w > dst->ri_emuwidth) 1023 w = dst->ri_emuwidth - dx; 1024 if (dy + h > dst->ri_emuheight) 1025 h = dst->ri_emuheight - dy; 1026 if (w <= 0 || h <= 0) 1027 return 0; /* Vacuously true; */ 1028 if (!src) { 1029 /* XXX Punt! */ 1030 return -1; 1031 } 1032 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1033 } 1034 1035 1036 1037 /* 1038 * Video to Video raster ops. 1039 * This function deals with all raster ops that have a src and dst 1040 * that are on the card. 1041 */ 1042 static int 1043 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1044 struct rasops_info *dst; 1045 int dx, dy, w, h, rop; 1046 struct rasops_info *src; 1047 int sx, sy; 1048 { 1049 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1050 int srcb, dstb, tga_srcb, tga_dstb; 1051 int x, y, wb; 1052 int xstart, xend, xdir; 1053 int ystart, yend, ydir, yinc; 1054 int xleft, lastx, lastleft; 1055 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1056 1057 /* 1058 * I don't yet want to deal with unaligned guys, really. And we don't 1059 * deal with copies from one card to another. 1060 */ 1061 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1062 /* XXX Punt! */ 1063 /* XXX should never happen, since it's only being used to 1064 * XXX copy 8-pixel-wide characters. 1065 */ 1066 return -1; 1067 } 1068 1069 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1070 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1071 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1072 (sx + src->ri_xorigin) * (src->ri_depth/8); 1073 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1074 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1075 1076 if (sy >= dy) { 1077 ystart = 0; 1078 yend = (h - 1) * dst->ri_stride; 1079 ydir = 1; 1080 } else { 1081 ystart = (h - 1) * dst->ri_stride; 1082 yend = 0; 1083 ydir = -1; 1084 } 1085 yinc = ydir * dst->ri_stride; 1086 1087 wb = w * (dst->ri_depth / 8); 1088 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1089 xstart = 0; 1090 xend = wb; 1091 xdir = 1; 1092 } else { /* copy backwards */ 1093 xstart = wb; 1094 xend = 0; 1095 xdir = -1; 1096 } 1097 1098 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1099 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1100 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1101 1102 /* 1103 * we have 3 sizes of pixels to move in X direction: 1104 * 4 * 64 (unrolled TGA ops) 1105 * 64 (single TGA op) 1106 * 4 (CPU, using long word) 1107 */ 1108 1109 if (xdir == 1) { /* move to the left */ 1110 1111 if (wb & ~63) 1112 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1113 /* 4*64 byte chunks */ 1114 for (xleft = wb, x = xstart; xleft >= 4*64; 1115 x += 4*64, xleft -= 4*64) { 1116 1117 /* XXX XXX Eight writes to different addresses should fill 1118 * XXX XXX up the write buffers on 21064 and 21164 chips, 1119 * XXX XXX but later CPUs might have larger write buffers which 1120 * XXX XXX require further unrolling of this loop, or the 1121 * XXX XXX insertion of memory barriers. 1122 */ 1123 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1124 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1125 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1126 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1127 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1128 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1129 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1130 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1131 } 1132 1133 /* 64 byte chunks */ 1134 for (; xleft >= 64; x += 64, xleft -= 64) { 1135 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1136 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1137 } 1138 } 1139 1140 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1141 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1142 1143 lastleft = wb & 63; 1144 if (lastleft) { 1145 lastx = xstart + (wb & ~63); 1146 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1147 /* 4 byte granularity */ 1148 for (x = lastx, xleft = lastleft; xleft >= 4; 1149 x += 4, xleft -= 4) { 1150 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1151 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1152 } 1153 } 1154 } 1155 } 1156 else { /* above move to the left, below move to the right */ 1157 1158 if (wb & ~63) 1159 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1160 /* 4*64 byte chunks */ 1161 for (xleft = wb, x = xstart; xleft >= 4*64; 1162 x -= 4*64, xleft -= 4*64) { 1163 1164 /* XXX XXX Eight writes to different addresses should fill 1165 * XXX XXX up the write buffers on 21064 and 21164 chips, 1166 * XXX XXX but later CPUs might have larger write buffers which 1167 * XXX XXX require further unrolling of this loop, or the 1168 * XXX XXX insertion of memory barriers. 1169 */ 1170 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1171 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1172 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1173 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1174 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1175 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1176 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1177 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1178 } 1179 1180 /* 64 byte chunks */ 1181 for (; xleft >= 64; x -= 64, xleft -= 64) { 1182 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1183 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1184 } 1185 } 1186 1187 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1188 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1189 1190 lastleft = wb & 63; 1191 if (lastleft) { 1192 lastx = xstart - (wb & ~63); 1193 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1194 /* 4 byte granularity */ 1195 for (x = lastx, xleft = lastleft; xleft >= 4; 1196 x -= 4, xleft -= 4) { 1197 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1198 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1199 } 1200 } 1201 } 1202 } 1203 return 0; 1204 } 1205 1206 1207 void tga_putchar (c, row, col, uc, attr) 1208 void *c; 1209 int row, col; 1210 u_int uc; 1211 long attr; 1212 { 1213 struct rasops_info *ri = c; 1214 struct tga_devconfig *dc = ri->ri_hw; 1215 int fs, height, width; 1216 u_char *fr; 1217 int32_t *rp; 1218 1219 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1220 1221 height = ri->ri_font->fontheight; 1222 width = ri->ri_font->fontwidth; 1223 1224 uc -= ri->ri_font->firstchar; 1225 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1226 fs = ri->ri_font->stride; 1227 1228 /* Set foreground and background color. XXX memoize this somehow? 1229 * The rasops code has already expanded the color entry to 32 bits 1230 * for us, even for 8-bit displays, so we don't have to do anything. 1231 */ 1232 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1233 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1234 1235 /* Set raster operation to "copy"... */ 1236 if (ri->ri_depth == 8) 1237 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1238 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1239 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1240 1241 /* Set which pixels we're drawing (of a possible 32). */ 1242 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1243 1244 /* Set drawing mode to opaque stipple. */ 1245 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1246 1247 /* Insert write barrier before actually sending data */ 1248 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1249 TGAREGWB(dc, TGA_REG_GMOR, 1); 1250 1251 while(height--) { 1252 /* The actual stipple write */ 1253 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1254 1255 fr += fs; 1256 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1257 } 1258 1259 /* Do underline */ 1260 if ((attr & 1) != 0) { 1261 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1262 *rp = 0xffffffff; 1263 } 1264 1265 /* Set grapics mode back to normal. */ 1266 TGAWREG(dc, TGA_REG_GMOR, 0); 1267 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1268 1269 } 1270 1271 static void 1272 tga_eraserows(c, row, num, attr) 1273 void *c; 1274 int row, num; 1275 long attr; 1276 { 1277 struct rasops_info *ri = c; 1278 struct tga_devconfig *dc = ri->ri_hw; 1279 int32_t color, lines, pixels; 1280 int32_t *rp; 1281 1282 color = ri->ri_devcmap[(attr >> 16) & 15]; 1283 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1284 lines = num * ri->ri_font->fontheight; 1285 pixels = ri->ri_emuwidth - 1; 1286 1287 /* Set fill color in block-color registers */ 1288 TGAWREG(dc, TGA_REG_GBCR0, color); 1289 TGAWREG(dc, TGA_REG_GBCR1, color); 1290 if (ri->ri_depth != 8) { 1291 TGAWREG(dc, TGA_REG_GBCR2, color); 1292 TGAWREG(dc, TGA_REG_GBCR3, color); 1293 TGAWREG(dc, TGA_REG_GBCR4, color); 1294 TGAWREG(dc, TGA_REG_GBCR5, color); 1295 TGAWREG(dc, TGA_REG_GBCR6, color); 1296 TGAWREG(dc, TGA_REG_GBCR7, color); 1297 } 1298 1299 /* Set raster operation to "copy"... */ 1300 if (ri->ri_depth == 8) 1301 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1302 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1303 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1304 1305 /* Set which pixels we're drawing (of a possible 32). */ 1306 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1307 1308 /* Set drawing mode to block fill. */ 1309 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1310 1311 /* Insert write barrier before actually sending data */ 1312 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1313 TGAREGWB(dc, TGA_REG_GMOR, 1); 1314 1315 while (lines--) { 1316 *rp = pixels; 1317 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1318 } 1319 1320 /* Set grapics mode back to normal. */ 1321 TGAWREG(dc, TGA_REG_GMOR, 0); 1322 1323 } 1324 1325 static void 1326 tga_erasecols (c, row, col, num, attr) 1327 void *c; 1328 int row, col, num; 1329 long attr; 1330 { 1331 struct rasops_info *ri = c; 1332 struct tga_devconfig *dc = ri->ri_hw; 1333 int32_t color, lines, pixels; 1334 int32_t *rp; 1335 1336 color = ri->ri_devcmap[(attr >> 16) & 15]; 1337 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1338 lines = ri->ri_font->fontheight; 1339 pixels = (num * ri->ri_font->fontwidth) - 1; 1340 1341 /* Set fill color in block-color registers */ 1342 TGAWREG(dc, TGA_REG_GBCR0, color); 1343 TGAWREG(dc, TGA_REG_GBCR1, color); 1344 if (ri->ri_depth != 8) { 1345 TGAWREG(dc, TGA_REG_GBCR2, color); 1346 TGAWREG(dc, TGA_REG_GBCR3, color); 1347 TGAWREG(dc, TGA_REG_GBCR4, color); 1348 TGAWREG(dc, TGA_REG_GBCR5, color); 1349 TGAWREG(dc, TGA_REG_GBCR6, color); 1350 TGAWREG(dc, TGA_REG_GBCR7, color); 1351 } 1352 1353 /* Set raster operation to "copy"... */ 1354 if (ri->ri_depth == 8) 1355 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1356 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1357 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1358 1359 /* Set which pixels we're drawing (of a possible 32). */ 1360 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1361 1362 /* Set drawing mode to block fill. */ 1363 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1364 1365 /* Insert write barrier before actually sending data */ 1366 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1367 TGAREGWB(dc, TGA_REG_GMOR, 1); 1368 1369 while (lines--) { 1370 *rp = pixels; 1371 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1372 } 1373 1374 /* Set grapics mode back to normal. */ 1375 TGAWREG(dc, TGA_REG_GMOR, 0); 1376 } 1377 1378 1379 static void 1380 tga_ramdac_wr(v, btreg, val) 1381 void *v; 1382 u_int btreg; 1383 u_int8_t val; 1384 { 1385 struct tga_devconfig *dc = v; 1386 1387 if (btreg > BT485_REG_MAX) 1388 panic("tga_ramdac_wr: reg %d out of range", btreg); 1389 1390 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1391 TGAREGWB(dc, TGA_REG_EPDR, 1); 1392 } 1393 1394 static void 1395 tga2_ramdac_wr(v, btreg, val) 1396 void *v; 1397 u_int btreg; 1398 u_int8_t val; 1399 { 1400 struct tga_devconfig *dc = v; 1401 bus_space_handle_t ramdac; 1402 1403 if (btreg > BT485_REG_MAX) 1404 panic("tga_ramdac_wr: reg %d out of range", btreg); 1405 1406 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1407 (0xe << 12) + (btreg << 8), 4, &ramdac); 1408 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1409 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1410 } 1411 1412 static u_int8_t 1413 tga_bt463_rd(v, btreg) 1414 void *v; 1415 u_int btreg; 1416 { 1417 struct tga_devconfig *dc = v; 1418 tga_reg_t rdval; 1419 1420 /* 1421 * Strobe CE# (high->low->high) since status and data are latched on 1422 * the falling and rising edges (repsectively) of this active-low signal. 1423 */ 1424 1425 TGAREGWB(dc, TGA_REG_EPSR, 1); 1426 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1427 TGAREGWB(dc, TGA_REG_EPSR, 1); 1428 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1429 1430 TGAREGRB(dc, TGA_REG_EPSR, 1); 1431 1432 rdval = TGARREG(dc, TGA_REG_EPDR); 1433 TGAREGWB(dc, TGA_REG_EPSR, 1); 1434 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1435 1436 return (rdval >> 16) & 0xff; 1437 } 1438 1439 static void 1440 tga_bt463_wr(v, btreg, val) 1441 void *v; 1442 u_int btreg; 1443 u_int8_t val; 1444 { 1445 struct tga_devconfig *dc = v; 1446 1447 /* 1448 * In spite of the 21030 documentation, to set the MPU bus bits for 1449 * a write, you set them in the upper bits of EPDR, not EPSR. 1450 */ 1451 1452 /* 1453 * Strobe CE# (high->low->high) since status and data are latched on 1454 * the falling and rising edges of this active-low signal. 1455 */ 1456 1457 TGAREGWB(dc, TGA_REG_EPDR, 1); 1458 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1459 TGAREGWB(dc, TGA_REG_EPDR, 1); 1460 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1461 TGAREGWB(dc, TGA_REG_EPDR, 1); 1462 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1463 1464 } 1465 1466 static u_int8_t 1467 tga_ramdac_rd(v, btreg) 1468 void *v; 1469 u_int btreg; 1470 { 1471 struct tga_devconfig *dc = v; 1472 tga_reg_t rdval; 1473 1474 if (btreg > BT485_REG_MAX) 1475 panic("tga_ramdac_rd: reg %d out of range", btreg); 1476 1477 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1478 TGAREGWB(dc, TGA_REG_EPSR, 1); 1479 1480 rdval = TGARREG(dc, TGA_REG_EPDR); 1481 return (rdval >> 16) & 0xff; /* XXX */ 1482 } 1483 1484 static u_int8_t 1485 tga2_ramdac_rd(v, btreg) 1486 void *v; 1487 u_int btreg; 1488 { 1489 struct tga_devconfig *dc = v; 1490 bus_space_handle_t ramdac; 1491 u_int8_t retval; 1492 1493 if (btreg > BT485_REG_MAX) 1494 panic("tga_ramdac_rd: reg %d out of range", btreg); 1495 1496 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1497 (0xe << 12) + (btreg << 8), 4, &ramdac); 1498 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1499 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1500 return retval; 1501 } 1502 1503 #include <dev/ic/decmonitors.c> 1504 void tga2_ics9110_wr __P(( 1505 struct tga_devconfig *dc, 1506 int dotclock 1507 )); 1508 1509 struct monitor *tga_getmonitor __P((struct tga_devconfig *dc)); 1510 1511 void 1512 tga2_init(dc) 1513 struct tga_devconfig *dc; 1514 { 1515 struct monitor *m = tga_getmonitor(dc); 1516 1517 /* Deal with the dot clocks. 1518 */ 1519 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1520 /* Set this up as a reference clock for the 1521 * ibm561's PLL. 1522 */ 1523 tga2_ics9110_wr(dc, 14300000); 1524 /* XXX Can't set up the dotclock properly, until such time 1525 * as the RAMDAC is configured. 1526 */ 1527 } else { 1528 /* otherwise the ics9110 is our clock. */ 1529 tga2_ics9110_wr(dc, m->dotclock); 1530 } 1531 #if 0 1532 TGAWREG(dc, TGA_REG_VHCR, 1533 ((m->hbp / 4) << 21) | 1534 ((m->hsync / 4) << 14) | 1535 (((m->hfp - 4) / 4) << 9) | 1536 ((m->cols + 4) / 4)); 1537 #else 1538 TGAWREG(dc, TGA_REG_VHCR, 1539 ((m->hbp / 4) << 21) | 1540 ((m->hsync / 4) << 14) | 1541 (((m->hfp) / 4) << 9) | 1542 ((m->cols) / 4)); 1543 #endif 1544 TGAWREG(dc, TGA_REG_VVCR, 1545 (m->vbp << 22) | 1546 (m->vsync << 16) | 1547 (m->vfp << 11) | 1548 (m->rows)); 1549 TGAWREG(dc, TGA_REG_VVBR, 1); 1550 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1551 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1552 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1553 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1554 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1555 } 1556 1557 void 1558 tga2_ics9110_wr(dc, dotclock) 1559 struct tga_devconfig *dc; 1560 int dotclock; 1561 { 1562 bus_space_handle_t clock; 1563 u_int32_t valU; 1564 int N, M, R, V, X; 1565 int i; 1566 1567 switch (dotclock) { 1568 case 130808000: 1569 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1570 case 119840000: 1571 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1572 case 108180000: 1573 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1574 case 103994000: 1575 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1576 case 175000000: 1577 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1578 case 75000000: 1579 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1580 case 74000000: 1581 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1582 case 69000000: 1583 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1584 case 65000000: 1585 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1586 case 50000000: 1587 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1588 case 40000000: 1589 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1590 case 31500000: 1591 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1592 case 25175000: 1593 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1594 case 135000000: 1595 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1596 case 110000000: 1597 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1598 case 202500000: 1599 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1600 case 14300000: /* this one is just a ref clock */ 1601 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1602 default: 1603 panic("unrecognized clock rate %d", dotclock); 1604 } 1605 1606 /* XXX -- hard coded, bad */ 1607 valU = N | ( M << 7 ) | (V << 14); 1608 valU |= (X << 15) | (R << 17); 1609 valU |= 0x17 << 19; 1610 1611 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1612 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1613 1614 for (i=24; i>0; i--) { 1615 u_int32_t writeval; 1616 1617 writeval = valU & 0x1; 1618 if (i == 1) 1619 writeval |= 0x2; 1620 valU >>= 1; 1621 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1622 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1623 } 1624 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1625 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1626 &clock); /* XXX */ 1627 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1628 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1629 } 1630 1631 struct monitor * 1632 tga_getmonitor(dc) 1633 struct tga_devconfig *dc; 1634 { 1635 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1636 } 1637 1638 unsigned 1639 tga_getdotclock(dc) 1640 struct tga_devconfig *dc; 1641 { 1642 return tga_getmonitor(dc)->dotclock; 1643 } 1644