1 /* $NetBSD: tga.c,v 1.39 2002/01/12 16:17:06 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.39 2002/01/12 16:17:06 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 #ifdef __alpha__ 63 #include <machine/pte.h> 64 #endif 65 #ifdef __mips__ 66 #include <mips/pte.h> 67 #endif 68 69 int tgamatch __P((struct device *, struct cfdata *, void *)); 70 void tgaattach __P((struct device *, struct device *, void *)); 71 int tgaprint __P((void *, const char *)); 72 73 struct cfattach tga_ca = { 74 sizeof(struct tga_softc), tgamatch, tgaattach, 75 }; 76 77 int tga_identify __P((struct tga_devconfig *)); 78 const struct tga_conf *tga_getconf __P((int)); 79 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 80 pcitag_t tag, struct tga_devconfig *dc)); 81 82 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 83 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 84 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 85 unsigned tga_getdotclock __P((struct tga_devconfig *dc)); 86 87 struct tga_devconfig tga_console_dc; 88 89 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 90 paddr_t tga_mmap __P((void *, off_t, int)); 91 static void tga_copyrows __P((void *, int, int, int)); 92 static void tga_copycols __P((void *, int, int, int, int)); 93 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 94 void **, int *, int *, long *)); 95 static void tga_free_screen __P((void *, void *)); 96 static int tga_show_screen __P((void *, void *, int, 97 void (*) (void *, int, int), void *)); 98 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 99 struct rasops_info *, int, int)); 100 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 101 int, struct rasops_info *, int, int )); 102 static void tga_putchar __P((void *c, int row, int col, 103 u_int uc, long attr)); 104 static void tga_eraserows __P((void *, int, int, long)); 105 static void tga_erasecols __P((void *, int, int, int, long)); 106 void tga2_init __P((struct tga_devconfig *)); 107 108 static void tga_config_interrupts __P((struct device *)); 109 110 /* RAMDAC interface functions */ 111 static int tga_sched_update __P((void *, void (*)(void *))); 112 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 113 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 114 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 115 static u_int8_t tga_bt463_rd __P((void *, u_int)); 116 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 117 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 118 119 /* Interrupt handler */ 120 static int tga_intr __P((void *)); 121 122 /* The NULL entries will get filled in by rasops_init(). 123 * XXX and the non-NULL ones will be overwritten; reset after calling it. 124 */ 125 struct wsdisplay_emulops tga_emulops = { 126 NULL, 127 NULL, 128 tga_putchar, 129 tga_copycols, 130 tga_erasecols, 131 tga_copyrows, 132 tga_eraserows, 133 NULL, 134 }; 135 136 struct wsscreen_descr tga_stdscreen = { 137 "std", 138 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 139 &tga_emulops, 140 0, 0, 141 WSSCREEN_REVERSE 142 }; 143 144 const struct wsscreen_descr *_tga_scrlist[] = { 145 &tga_stdscreen, 146 /* XXX other formats, graphics screen? */ 147 }; 148 149 struct wsscreen_list tga_screenlist = { 150 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 151 }; 152 153 struct wsdisplay_accessops tga_accessops = { 154 tga_ioctl, 155 tga_mmap, 156 tga_alloc_screen, 157 tga_free_screen, 158 tga_show_screen, 159 0 /* load_font */ 160 }; 161 162 static void tga_blank __P((struct tga_devconfig *)); 163 static void tga_unblank __P((struct tga_devconfig *)); 164 165 int 166 tga_cnmatch(iot, memt, pc, tag) 167 bus_space_tag_t iot, memt; 168 pci_chipset_tag_t pc; 169 pcitag_t tag; 170 { 171 return tga_matchcommon(memt, pc, tag); 172 } 173 174 int 175 tgamatch(parent, match, aux) 176 struct device *parent; 177 struct cfdata *match; 178 void *aux; 179 { 180 struct pci_attach_args *pa = aux; 181 182 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 183 return (0); 184 185 switch (PCI_PRODUCT(pa->pa_id)) { 186 case PCI_PRODUCT_DEC_21030: 187 case PCI_PRODUCT_DEC_PBXGB: 188 break; 189 default: 190 return 0; 191 } 192 193 /* short-circuit the following test, as we 194 * already have the memory mapped and hence 195 * cannot perform it---and we are the console 196 * anyway. 197 */ 198 if (pa->pa_tag == tga_console_dc.dc_pcitag) 199 return 10; 200 201 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 202 } 203 204 static int 205 tga_matchcommon(memt, pc, tag) 206 bus_space_tag_t memt; 207 pci_chipset_tag_t pc; 208 pcitag_t tag; 209 { 210 struct tga_devconfig tmp_dc; 211 struct tga_devconfig *dc = &tmp_dc; 212 bus_size_t pcisize; 213 214 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 215 dc->dc_tga_type = tga_identify(dc); 216 217 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 218 bus_space_unmap(memt, dc->dc_memh, pcisize); 219 if (dc->dc_tgaconf) 220 return 10; 221 return 0; 222 } 223 224 static void 225 tga_mapaddrs(memt, pc, tag, pcisize, dc) 226 bus_space_tag_t memt; 227 pci_chipset_tag_t pc; 228 pcitag_t tag; 229 bus_size_t *pcisize; 230 struct tga_devconfig *dc; 231 { 232 int flags; 233 234 dc->dc_memt = memt; 235 dc->dc_tgaconf = NULL; 236 237 /* XXX magic number */ 238 if (pci_mapreg_info(pc, tag, 0x10, 239 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 240 &dc->dc_pcipaddr, pcisize, &flags)) 241 panic("tga_mapaddrs: pci_mapreg_info() failed"); 242 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 243 panic("tga memory not prefetchable"); 244 245 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 246 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 247 panic("tga_mapaddrs: could not map TGA address space"); 248 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 249 250 bus_space_subregion(dc->dc_memt, dc->dc_memh, 251 TGA_MEM_CREGS, TGA_CREGS_SIZE, 252 &dc->dc_regs); 253 } 254 255 static void 256 tga_init(memt, pc, tag, dc) 257 bus_space_tag_t memt; 258 pci_chipset_tag_t pc; 259 pcitag_t tag; 260 struct tga_devconfig *dc; 261 { 262 const struct tga_conf *tgac; 263 struct rasops_info *rip; 264 int cookie; 265 bus_size_t pcisize; 266 int i; 267 268 dc->dc_pcitag = tag; 269 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 270 dc->dc_tga_type = tga_identify(dc); 271 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 272 #if 0 273 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 274 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 275 panic("tga_init: memory size mismatch?"); 276 #endif 277 278 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 279 case 0x01: 280 case 0x02: 281 case 0x03: 282 case 0x04: 283 dc->dc_tga2 = 0; 284 break; 285 case 0x20: 286 case 0x21: 287 case 0x22: 288 dc->dc_tga2 = 1; 289 break; 290 default: 291 panic("tga_init: TGA Revision not recognized"); 292 } 293 294 if (dc->dc_tga2) 295 tga2_init(dc); 296 297 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 298 case 0: 299 dc->dc_wid = 8192; 300 break; 301 302 case 1: 303 dc->dc_wid = 8196; 304 break; 305 306 default: 307 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 308 break; 309 } 310 311 /* 312 * XXX XXX Turning off "odd" shouldn't be necessary, 313 * XXX XXX but I can't make X work with the weird size. 314 */ 315 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 316 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 317 TGAWREG(dc, TGA_REG_VHCR, 318 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 319 dc->dc_wid -= 4; 320 } 321 322 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 323 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 324 325 /* XXX this seems to be what DEC does */ 326 TGAWREG(dc, TGA_REG_CCBR, 0); 327 TGAWREG(dc, TGA_REG_VVBR, 1); 328 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 329 1 * tgac->tgac_vvbr_units; 330 dc->dc_blanked = 1; 331 tga_unblank(dc); 332 333 /* 334 * Set all bits in the pixel mask, to enable writes to all pixels. 335 * It seems that the console firmware clears some of them 336 * under some circumstances, which causes cute vertical stripes. 337 */ 338 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 339 340 /* clear the screen */ 341 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 342 *(u_int32_t *)(dc->dc_videobase + i) = 0; 343 344 /* Initialize rasops descriptor */ 345 rip = &dc->dc_rinfo; 346 rip->ri_flg = RI_CENTER; 347 rip->ri_depth = tgac->tgac_phys_depth; 348 rip->ri_bits = (void *)dc->dc_videobase; 349 rip->ri_width = dc->dc_wid; 350 rip->ri_height = dc->dc_ht; 351 rip->ri_stride = dc->dc_rowbytes; 352 rip->ri_hw = dc; 353 354 if (tgac->tgac_phys_depth == 32) { 355 rip->ri_rnum = 8; 356 rip->ri_gnum = 8; 357 rip->ri_bnum = 8; 358 rip->ri_rpos = 16; 359 rip->ri_gpos = 8; 360 rip->ri_bpos = 0; 361 } 362 363 wsfont_init(); 364 /* prefer 8 pixel wide font */ 365 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0) 366 cookie = wsfont_find(NULL, 0, 0, 0); 367 if (cookie <= 0) { 368 printf("tga: no appropriate fonts.\n"); 369 return; 370 } 371 372 /* the accelerated tga_putchar() needs LSbit left */ 373 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font, 374 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 375 printf("tga: couldn't lock font\n"); 376 return; 377 } 378 dc->dc_rinfo.ri_wsfcookie = cookie; 379 380 rasops_init(rip, 34, 80); 381 382 /* add our accelerated functions */ 383 /* XXX shouldn't have to do this; rasops should leave non-NULL 384 * XXX entries alone. 385 */ 386 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 387 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 388 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 389 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 390 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 391 392 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 393 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 394 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 395 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 396 397 398 dc->dc_intrenabled = 0; 399 } 400 401 void 402 tgaattach(parent, self, aux) 403 struct device *parent, *self; 404 void *aux; 405 { 406 struct pci_attach_args *pa = aux; 407 struct tga_softc *sc = (struct tga_softc *)self; 408 struct wsemuldisplaydev_attach_args aa; 409 pci_intr_handle_t intrh; 410 const char *intrstr; 411 u_int8_t rev; 412 int console; 413 414 #if defined(__alpha__) || defined(arc) 415 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 416 #else 417 console = 0; 418 #endif 419 if (console) { 420 sc->sc_dc = &tga_console_dc; 421 sc->nscreens = 1; 422 } else { 423 sc->sc_dc = (struct tga_devconfig *) 424 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 425 M_WAITOK|M_ZERO); 426 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 427 } 428 if (sc->sc_dc->dc_vaddr == NULL) { 429 printf(": couldn't map memory space; punt!\n"); 430 return; 431 } 432 433 /* XXX say what's going on. */ 434 intrstr = NULL; 435 if (pci_intr_map(pa, &intrh)) { 436 printf(": couldn't map interrupt"); 437 return; 438 } 439 intrstr = pci_intr_string(pa->pa_pc, intrh); 440 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 441 sc->sc_dc); 442 if (sc->sc_intr == NULL) { 443 printf(": couldn't establish interrupt"); 444 if (intrstr != NULL) 445 printf("at %s", intrstr); 446 printf("\n"); 447 return; 448 } 449 450 rev = PCI_REVISION(pa->pa_class); 451 switch (rev) { 452 case 0x1: 453 case 0x2: 454 case 0x3: 455 printf(": DC21030 step %c", 'A' + rev - 1); 456 break; 457 case 0x20: 458 printf(": TGA2 abstract software model"); 459 break; 460 case 0x21: 461 case 0x22: 462 printf(": TGA2 pass %d", rev - 0x20); 463 break; 464 465 default: 466 printf("unknown stepping (0x%x)", rev); 467 break; 468 } 469 printf(", "); 470 471 /* 472 * Get RAMDAC function vectors and call the RAMDAC functions 473 * to allocate its private storage and pass that back to us. 474 */ 475 476 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 477 if (!sc->sc_dc->dc_tga2) { 478 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 479 sc->sc_dc->dc_ramdac_cookie = 480 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 481 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 482 else 483 sc->sc_dc->dc_ramdac_cookie = 484 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 485 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 486 } else { 487 sc->sc_dc->dc_ramdac_cookie = 488 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 489 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 490 491 /* XXX this is a bit of a hack, setting the dotclock here */ 492 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 493 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 494 (sc->sc_dc->dc_ramdac_cookie, 495 tga_getdotclock(sc->sc_dc)); 496 } 497 498 /* 499 * Initialize the RAMDAC. Initialization includes disabling 500 * cursor, setting a sane colormap, etc. We presume that we've 501 * filled in the necessary dot clock for PowerStorm 4d20. 502 */ 503 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 504 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 505 506 if (sc->sc_dc->dc_tgaconf == NULL) { 507 printf("unknown board configuration\n"); 508 return; 509 } 510 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 511 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 512 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 513 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 514 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 515 516 if (intrstr != NULL) 517 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 518 intrstr); 519 520 aa.console = console; 521 aa.scrdata = &tga_screenlist; 522 aa.accessops = &tga_accessops; 523 aa.accesscookie = sc; 524 525 config_found(self, &aa, wsemuldisplaydevprint); 526 527 config_interrupts(self, tga_config_interrupts); 528 } 529 530 static void 531 tga_config_interrupts (d) 532 struct device *d; 533 { 534 struct tga_softc *sc = (struct tga_softc *)d; 535 sc->sc_dc->dc_intrenabled = 1; 536 } 537 538 int 539 tga_ioctl(v, cmd, data, flag, p) 540 void *v; 541 u_long cmd; 542 caddr_t data; 543 int flag; 544 struct proc *p; 545 { 546 struct tga_softc *sc = v; 547 struct tga_devconfig *dc = sc->sc_dc; 548 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 549 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 550 551 switch (cmd) { 552 case WSDISPLAYIO_GTYPE: 553 *(u_int *)data = WSDISPLAY_TYPE_TGA; 554 return (0); 555 556 case WSDISPLAYIO_GINFO: 557 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 558 wsd_fbip->height = sc->sc_dc->dc_ht; 559 wsd_fbip->width = sc->sc_dc->dc_wid; 560 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 561 #if 0 562 wsd_fbip->cmsize = 256; /* XXX ??? */ 563 #else 564 wsd_fbip->cmsize = 1024; /* XXX ??? */ 565 #endif 566 #undef wsd_fbip 567 return (0); 568 569 case WSDISPLAYIO_GETCMAP: 570 return (*dcrf->ramdac_get_cmap)(dcrc, 571 (struct wsdisplay_cmap *)data); 572 573 case WSDISPLAYIO_PUTCMAP: 574 return (*dcrf->ramdac_set_cmap)(dcrc, 575 (struct wsdisplay_cmap *)data); 576 577 case WSDISPLAYIO_SVIDEO: 578 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 579 tga_blank(sc->sc_dc); 580 else 581 tga_unblank(sc->sc_dc); 582 return (0); 583 584 case WSDISPLAYIO_GVIDEO: 585 *(u_int *)data = dc->dc_blanked ? 586 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 587 return (0); 588 589 case WSDISPLAYIO_GCURPOS: 590 return (*dcrf->ramdac_get_curpos)(dcrc, 591 (struct wsdisplay_curpos *)data); 592 593 case WSDISPLAYIO_SCURPOS: 594 return (*dcrf->ramdac_set_curpos)(dcrc, 595 (struct wsdisplay_curpos *)data); 596 597 case WSDISPLAYIO_GCURMAX: 598 return (*dcrf->ramdac_get_curmax)(dcrc, 599 (struct wsdisplay_curpos *)data); 600 601 case WSDISPLAYIO_GCURSOR: 602 return (*dcrf->ramdac_get_cursor)(dcrc, 603 (struct wsdisplay_cursor *)data); 604 605 case WSDISPLAYIO_SCURSOR: 606 return (*dcrf->ramdac_set_cursor)(dcrc, 607 (struct wsdisplay_cursor *)data); 608 } 609 return (-1); 610 } 611 612 static int 613 tga_sched_update(v, f) 614 void *v; 615 void (*f) __P((void *)); 616 { 617 struct tga_devconfig *dc = v; 618 619 if (dc->dc_intrenabled) { 620 /* Arrange for f to be called at the next end-of-frame interrupt */ 621 dc->dc_ramdac_intr = f; 622 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 623 } else { 624 /* Spin until the end-of-frame, then call f */ 625 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 626 TGAREGWB(dc, TGA_REG_SISR, 1); 627 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 628 ; 629 f(dc->dc_ramdac_cookie); 630 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 631 TGAREGWB(dc, TGA_REG_SISR, 1); 632 } 633 634 return 0; 635 } 636 637 static int 638 tga_intr(v) 639 void *v; 640 { 641 struct tga_devconfig *dc = v; 642 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 643 644 u_int32_t reg; 645 646 reg = TGARREG(dc, TGA_REG_SISR); 647 if (( reg & 0x00010001) != 0x00010001) { 648 /* Odd. We never set any of the other interrupt enables. */ 649 if ((reg & 0x1f) != 0) { 650 /* Clear the mysterious pending interrupts. */ 651 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 652 TGAREGWB(dc, TGA_REG_SISR, 1); 653 /* This was our interrupt, even if we're puzzled as to why 654 * we got it. Don't make the interrupt handler think it 655 * was a stray. 656 */ 657 return -1; 658 } else { 659 return 0; 660 } 661 } 662 /* if we have something to do, do it */ 663 if (dc->dc_ramdac_intr) { 664 dc->dc_ramdac_intr(dcrc); 665 dc->dc_ramdac_intr = NULL; 666 } 667 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 668 TGAREGWB(dc, TGA_REG_SISR, 1); 669 return (1); 670 } 671 672 paddr_t 673 tga_mmap(v, offset, prot) 674 void *v; 675 off_t offset; 676 int prot; 677 { 678 struct tga_softc *sc = v; 679 680 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 681 return -1; 682 683 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 684 offset, prot, BUS_SPACE_MAP_LINEAR)); 685 } 686 687 static int 688 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 689 void *v; 690 const struct wsscreen_descr *type; 691 void **cookiep; 692 int *curxp, *curyp; 693 long *attrp; 694 { 695 struct tga_softc *sc = v; 696 long defattr; 697 698 if (sc->nscreens > 0) 699 return (ENOMEM); 700 701 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 702 *curxp = 0; 703 *curyp = 0; 704 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 705 0, 0, 0, &defattr); 706 *attrp = defattr; 707 sc->nscreens++; 708 return (0); 709 } 710 711 static void 712 tga_free_screen(v, cookie) 713 void *v; 714 void *cookie; 715 { 716 struct tga_softc *sc = v; 717 718 if (sc->sc_dc == &tga_console_dc) 719 panic("tga_free_screen: console"); 720 721 sc->nscreens--; 722 } 723 724 static int 725 tga_show_screen(v, cookie, waitok, cb, cbarg) 726 void *v; 727 void *cookie; 728 int waitok; 729 void (*cb) __P((void *, int, int)); 730 void *cbarg; 731 { 732 733 return (0); 734 } 735 736 int 737 tga_cnattach(iot, memt, pc, bus, device, function) 738 bus_space_tag_t iot, memt; 739 pci_chipset_tag_t pc; 740 int bus, device, function; 741 { 742 struct tga_devconfig *dcp = &tga_console_dc; 743 long defattr; 744 745 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 746 747 /* sanity checks */ 748 if (dcp->dc_vaddr == NULL) 749 panic("tga_console(%d, %d): couldn't map memory space", 750 device, function); 751 if (dcp->dc_tgaconf == NULL) 752 panic("tga_console(%d, %d): unknown board configuration", 753 device, function); 754 755 /* 756 * Initialize the RAMDAC but DO NOT allocate any private storage. 757 * Initialization includes disabling cursor, setting a sane 758 * colormap, etc. It will be reinitialized in tgaattach(). 759 */ 760 if (dcp->dc_tga2) { 761 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 762 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 763 tga2_ramdac_rd); 764 else 765 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 766 tga2_ramdac_rd, tga_getdotclock(dcp)); 767 } else { 768 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 769 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 770 tga_ramdac_rd); 771 else { 772 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 773 tga_bt463_rd); 774 } 775 } 776 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 777 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 778 779 return(0); 780 } 781 782 /* 783 * Functions to blank and unblank the display. 784 */ 785 static void 786 tga_blank(dc) 787 struct tga_devconfig *dc; 788 { 789 790 if (!dc->dc_blanked) { 791 dc->dc_blanked = 1; 792 /* XXX */ 793 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 794 } 795 } 796 797 static void 798 tga_unblank(dc) 799 struct tga_devconfig *dc; 800 { 801 802 if (dc->dc_blanked) { 803 dc->dc_blanked = 0; 804 /* XXX */ 805 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 806 } 807 } 808 809 /* 810 * Functions to manipulate the built-in cursor handing hardware. 811 */ 812 int 813 tga_builtin_set_cursor(dc, cursorp) 814 struct tga_devconfig *dc; 815 struct wsdisplay_cursor *cursorp; 816 { 817 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 818 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 819 u_int count, v; 820 int error; 821 822 v = cursorp->which; 823 if (v & WSDISPLAY_CURSOR_DOCMAP) { 824 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 825 if (error) 826 return (error); 827 } 828 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 829 if ((u_int)cursorp->size.x != 64 || 830 (u_int)cursorp->size.y > 64) 831 return (EINVAL); 832 /* The cursor is 2 bits deep, and there is no mask */ 833 count = (cursorp->size.y * 64 * 2) / NBBY; 834 if (!uvm_useracc(cursorp->image, count, B_READ)) 835 return (EFAULT); 836 } 837 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 838 return EINVAL; 839 840 /* parameters are OK; do it */ 841 if (v & WSDISPLAY_CURSOR_DOCUR) { 842 if (cursorp->enable) 843 /* XXX */ 844 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 845 else 846 /* XXX */ 847 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 848 } 849 if (v & WSDISPLAY_CURSOR_DOPOS) { 850 TGAWREG(dc, TGA_REG_CXYR, 851 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 852 } 853 if (v & WSDISPLAY_CURSOR_DOCMAP) { 854 /* can't fail. */ 855 dcrf->ramdac_set_curcmap(dcrc, cursorp); 856 } 857 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 858 count = ((64 * 2) / NBBY) * cursorp->size.y; 859 TGAWREG(dc, TGA_REG_CCBR, 860 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 861 copyin(cursorp->image, (char *)(dc->dc_vaddr + 862 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 863 count); /* can't fail. */ 864 } 865 return (0); 866 } 867 868 int 869 tga_builtin_get_cursor(dc, cursorp) 870 struct tga_devconfig *dc; 871 struct wsdisplay_cursor *cursorp; 872 { 873 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 874 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 875 int count, error; 876 877 cursorp->which = WSDISPLAY_CURSOR_DOALL & 878 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 879 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 880 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 881 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 882 cursorp->size.x = 64; 883 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 884 885 if (cursorp->image != NULL) { 886 count = (cursorp->size.y * 64 * 2) / NBBY; 887 error = copyout((char *)(dc->dc_vaddr + 888 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 889 cursorp->image, count); 890 if (error) 891 return (error); 892 /* No mask */ 893 } 894 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 895 return (error); 896 } 897 898 int 899 tga_builtin_set_curpos(dc, curposp) 900 struct tga_devconfig *dc; 901 struct wsdisplay_curpos *curposp; 902 { 903 904 TGAWREG(dc, TGA_REG_CXYR, 905 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 906 return (0); 907 } 908 909 int 910 tga_builtin_get_curpos(dc, curposp) 911 struct tga_devconfig *dc; 912 struct wsdisplay_curpos *curposp; 913 { 914 915 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 916 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 917 return (0); 918 } 919 920 int 921 tga_builtin_get_curmax(dc, curposp) 922 struct tga_devconfig *dc; 923 struct wsdisplay_curpos *curposp; 924 { 925 926 curposp->x = curposp->y = 64; 927 return (0); 928 } 929 930 /* 931 * Copy columns (characters) in a row (line). 932 */ 933 static void 934 tga_copycols(id, row, srccol, dstcol, ncols) 935 void *id; 936 int row, srccol, dstcol, ncols; 937 { 938 struct rasops_info *ri = id; 939 int y, srcx, dstx, nx; 940 941 y = ri->ri_font->fontheight * row; 942 srcx = ri->ri_font->fontwidth * srccol; 943 dstx = ri->ri_font->fontwidth * dstcol; 944 nx = ri->ri_font->fontwidth * ncols; 945 946 tga_rop(ri, dstx, y, 947 nx, ri->ri_font->fontheight, RAS_SRC, 948 ri, srcx, y); 949 } 950 951 /* 952 * Copy rows (lines). 953 */ 954 static void 955 tga_copyrows(id, srcrow, dstrow, nrows) 956 void *id; 957 int srcrow, dstrow, nrows; 958 { 959 struct rasops_info *ri = id; 960 int srcy, dsty, ny; 961 962 srcy = ri->ri_font->fontheight * srcrow; 963 dsty = ri->ri_font->fontheight * dstrow; 964 ny = ri->ri_font->fontheight * nrows; 965 966 tga_rop(ri, 0, dsty, 967 ri->ri_emuwidth, ny, RAS_SRC, 968 ri, 0, srcy); 969 } 970 971 /* Do we need the src? */ 972 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 973 974 /* A mapping between our API and the TGA card */ 975 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 976 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 977 }; 978 979 /* 980 * Generic TGA raster op. 981 * This covers all possible raster ops, and 982 * clips the sizes and all of that. 983 */ 984 static int 985 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 986 struct rasops_info *dst; 987 int dx, dy, w, h, rop; 988 struct rasops_info *src; 989 int sx, sy; 990 { 991 if (!dst) 992 return -1; 993 if (needsrc[RAS_GETOP(rop)]) { 994 if (src == NULL) 995 return -1; /* We want a src */ 996 /* Clip against src */ 997 if (sx < 0) { 998 w += sx; 999 sx = 0; 1000 } 1001 if (sy < 0) { 1002 h += sy; 1003 sy = 0; 1004 } 1005 if (sx + w > src->ri_emuwidth) 1006 w = src->ri_emuwidth - sx; 1007 if (sy + h > src->ri_emuheight) 1008 h = src->ri_emuheight - sy; 1009 } else { 1010 if (src != NULL) 1011 return -1; /* We need no src */ 1012 } 1013 /* Clip against dst. We modify src regardless of using it, 1014 * since it really doesn't matter. 1015 */ 1016 if (dx < 0) { 1017 w += dx; 1018 sx -= dx; 1019 dx = 0; 1020 } 1021 if (dy < 0) { 1022 h += dy; 1023 sy -= dy; 1024 dy = 0; 1025 } 1026 if (dx + w > dst->ri_emuwidth) 1027 w = dst->ri_emuwidth - dx; 1028 if (dy + h > dst->ri_emuheight) 1029 h = dst->ri_emuheight - dy; 1030 if (w <= 0 || h <= 0) 1031 return 0; /* Vacuously true; */ 1032 if (!src) { 1033 /* XXX Punt! */ 1034 return -1; 1035 } 1036 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1037 } 1038 1039 1040 1041 /* 1042 * Video to Video raster ops. 1043 * This function deals with all raster ops that have a src and dst 1044 * that are on the card. 1045 */ 1046 static int 1047 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1048 struct rasops_info *dst; 1049 int dx, dy, w, h, rop; 1050 struct rasops_info *src; 1051 int sx, sy; 1052 { 1053 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1054 int srcb, dstb, tga_srcb, tga_dstb; 1055 int x, y, wb; 1056 int xstart, xend, xdir; 1057 int ystart, yend, ydir, yinc; 1058 int xleft, lastx, lastleft; 1059 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1060 1061 /* 1062 * I don't yet want to deal with unaligned guys, really. And we don't 1063 * deal with copies from one card to another. 1064 */ 1065 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1066 /* XXX Punt! */ 1067 /* XXX should never happen, since it's only being used to 1068 * XXX copy 8-pixel-wide characters. 1069 */ 1070 return -1; 1071 } 1072 1073 wb = w * (dst->ri_depth / 8); 1074 if (sy >= dy) { 1075 ystart = 0; 1076 yend = h; 1077 ydir = 1; 1078 } else { 1079 ystart = h; 1080 yend = 0; 1081 ydir = -1; 1082 } 1083 if (sx >= dx) { /* moving to the left */ 1084 xstart = 0; 1085 xend = w * (dst->ri_depth / 8) - 4; 1086 xdir = 1; 1087 } else { /* moving to the right */ 1088 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 ); 1089 xend = 0; 1090 xdir = -1; 1091 } 1092 #define XINC4 4 1093 #define XINC64 64 1094 #define XINC256 (64*4) 1095 yinc = ydir * dst->ri_stride; 1096 ystart *= dst->ri_stride; 1097 yend *= dst->ri_stride; 1098 1099 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1100 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1101 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1102 (sx + src->ri_xorigin) * (src->ri_depth/8); 1103 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1104 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1105 1106 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1107 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1108 1109 /* 1110 * we have 3 sizes of pixels to move in X direction: 1111 * 4 * 64 (unrolled TGA ops) 1112 * 64 (single TGA op) 1113 * 4 (CPU, using long word) 1114 */ 1115 1116 if (xdir == 1) { /* move to the left */ 1117 1118 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1119 1120 /* 4*64 byte chunks */ 1121 for (xleft = wb, x = xstart; 1122 x <= xend && xleft >= 4*64; 1123 x += XINC256, xleft -= XINC256) { 1124 1125 /* XXX XXX Eight writes to different addresses should fill 1126 * XXX XXX up the write buffers on 21064 and 21164 chips, 1127 * XXX XXX but later CPUs might have larger write buffers which 1128 * XXX XXX require further unrolling of this loop, or the 1129 * XXX XXX insertion of memory barriers. 1130 */ 1131 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1132 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1133 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1134 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1135 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1136 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1137 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1138 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1139 } 1140 1141 /* 64 byte chunks */ 1142 for ( ; x <= xend && xleft >= 64; 1143 x += XINC64, xleft -= XINC64) { 1144 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1145 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1146 } 1147 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1148 1149 } 1150 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1151 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1152 1153 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1154 /* 4 byte granularity */ 1155 for (x = lastx, xleft = lastleft; 1156 x <= xend && xleft >= 4; 1157 x += XINC4, xleft -= XINC4) { 1158 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1159 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1160 } 1161 } 1162 } 1163 else { /* above move to the left, below move to the right */ 1164 1165 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1166 1167 /* 4*64 byte chunks */ 1168 for (xleft = wb, x = xstart; 1169 x >= xend && xleft >= 4*64; 1170 x -= XINC256, xleft -= XINC256) { 1171 1172 /* XXX XXX Eight writes to different addresses should fill 1173 * XXX XXX up the write buffers on 21064 and 21164 chips, 1174 * XXX XXX but later CPUs might have larger write buffers which 1175 * XXX XXX require further unrolling of this loop, or the 1176 * XXX XXX insertion of memory barriers. 1177 */ 1178 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64); 1179 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64); 1180 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64); 1181 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64); 1182 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64); 1183 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64); 1184 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64); 1185 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64); 1186 } 1187 1188 if (xleft) x += XINC256 - XINC64; 1189 1190 /* 64 byte chunks */ 1191 for ( ; x >= xend && xleft >= 64; 1192 x -= XINC64, xleft -= XINC64) { 1193 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1194 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1195 } 1196 if (xleft) x += XINC64 - XINC4; 1197 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1198 } 1199 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1200 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1201 1202 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1203 /* 4 byte granularity */ 1204 for (x = lastx, xleft = lastleft; 1205 x >= xend && xleft >= 4; 1206 x -= XINC4, xleft -= XINC4) { 1207 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1208 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1209 } 1210 } 1211 } 1212 return 0; 1213 } 1214 1215 1216 void tga_putchar (c, row, col, uc, attr) 1217 void *c; 1218 int row, col; 1219 u_int uc; 1220 long attr; 1221 { 1222 struct rasops_info *ri = c; 1223 struct tga_devconfig *dc = ri->ri_hw; 1224 int fs, height, width; 1225 u_char *fr; 1226 int32_t *rp; 1227 1228 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1229 1230 height = ri->ri_font->fontheight; 1231 width = ri->ri_font->fontwidth; 1232 1233 uc -= ri->ri_font->firstchar; 1234 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1235 fs = ri->ri_font->stride; 1236 1237 /* Set foreground and background color. XXX memoize this somehow? 1238 * The rasops code has already expanded the color entry to 32 bits 1239 * for us, even for 8-bit displays, so we don't have to do anything. 1240 */ 1241 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1242 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1243 1244 /* Set raster operation to "copy"... */ 1245 if (ri->ri_depth == 8) 1246 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1247 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1248 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1249 1250 /* Set which pixels we're drawing (of a possible 32). */ 1251 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1252 1253 /* Set drawing mode to opaque stipple. */ 1254 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1255 1256 /* Insert write barrier before actually sending data */ 1257 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1258 TGAREGWB(dc, TGA_REG_GMOR, 1); 1259 1260 while(height--) { 1261 /* The actual stipple write */ 1262 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1263 1264 fr += fs; 1265 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1266 } 1267 1268 /* Do underline */ 1269 if ((attr & 1) != 0) { 1270 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1271 *rp = 0xffffffff; 1272 } 1273 1274 /* Set grapics mode back to normal. */ 1275 TGAWREG(dc, TGA_REG_GMOR, 0); 1276 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1277 1278 } 1279 1280 static void 1281 tga_eraserows(c, row, num, attr) 1282 void *c; 1283 int row, num; 1284 long attr; 1285 { 1286 struct rasops_info *ri = c; 1287 struct tga_devconfig *dc = ri->ri_hw; 1288 int32_t color, lines, pixels; 1289 int32_t *rp; 1290 1291 color = ri->ri_devcmap[(attr >> 16) & 15]; 1292 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1293 lines = num * ri->ri_font->fontheight; 1294 pixels = ri->ri_emuwidth - 1; 1295 1296 /* Set fill color in block-color registers */ 1297 TGAWREG(dc, TGA_REG_GBCR0, color); 1298 TGAWREG(dc, TGA_REG_GBCR1, color); 1299 if (ri->ri_depth != 8) { 1300 TGAWREG(dc, TGA_REG_GBCR2, color); 1301 TGAWREG(dc, TGA_REG_GBCR3, color); 1302 TGAWREG(dc, TGA_REG_GBCR4, color); 1303 TGAWREG(dc, TGA_REG_GBCR5, color); 1304 TGAWREG(dc, TGA_REG_GBCR6, color); 1305 TGAWREG(dc, TGA_REG_GBCR7, color); 1306 } 1307 1308 /* Set raster operation to "copy"... */ 1309 if (ri->ri_depth == 8) 1310 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1311 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1312 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1313 1314 /* Set which pixels we're drawing (of a possible 32). */ 1315 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1316 1317 /* Set drawing mode to block fill. */ 1318 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1319 1320 /* Insert write barrier before actually sending data */ 1321 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1322 TGAREGWB(dc, TGA_REG_GMOR, 1); 1323 1324 while (lines--) { 1325 *rp = pixels; 1326 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1327 } 1328 1329 /* Set grapics mode back to normal. */ 1330 TGAWREG(dc, TGA_REG_GMOR, 0); 1331 1332 } 1333 1334 static void 1335 tga_erasecols (c, row, col, num, attr) 1336 void *c; 1337 int row, col, num; 1338 long attr; 1339 { 1340 struct rasops_info *ri = c; 1341 struct tga_devconfig *dc = ri->ri_hw; 1342 int32_t color, lines, pixels; 1343 int32_t *rp; 1344 1345 color = ri->ri_devcmap[(attr >> 16) & 15]; 1346 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1347 lines = ri->ri_font->fontheight; 1348 pixels = (num * ri->ri_font->fontwidth) - 1; 1349 1350 /* Set fill color in block-color registers */ 1351 TGAWREG(dc, TGA_REG_GBCR0, color); 1352 TGAWREG(dc, TGA_REG_GBCR1, color); 1353 if (ri->ri_depth != 8) { 1354 TGAWREG(dc, TGA_REG_GBCR2, color); 1355 TGAWREG(dc, TGA_REG_GBCR3, color); 1356 TGAWREG(dc, TGA_REG_GBCR4, color); 1357 TGAWREG(dc, TGA_REG_GBCR5, color); 1358 TGAWREG(dc, TGA_REG_GBCR6, color); 1359 TGAWREG(dc, TGA_REG_GBCR7, color); 1360 } 1361 1362 /* Set raster operation to "copy"... */ 1363 if (ri->ri_depth == 8) 1364 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1365 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1366 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1367 1368 /* Set which pixels we're drawing (of a possible 32). */ 1369 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1370 1371 /* Set drawing mode to block fill. */ 1372 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1373 1374 /* Insert write barrier before actually sending data */ 1375 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1376 TGAREGWB(dc, TGA_REG_GMOR, 1); 1377 1378 while (lines--) { 1379 *rp = pixels; 1380 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1381 } 1382 1383 /* Set grapics mode back to normal. */ 1384 TGAWREG(dc, TGA_REG_GMOR, 0); 1385 } 1386 1387 1388 static void 1389 tga_ramdac_wr(v, btreg, val) 1390 void *v; 1391 u_int btreg; 1392 u_int8_t val; 1393 { 1394 struct tga_devconfig *dc = v; 1395 1396 if (btreg > BT485_REG_MAX) 1397 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1398 1399 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1400 TGAREGWB(dc, TGA_REG_EPDR, 1); 1401 } 1402 1403 static void 1404 tga2_ramdac_wr(v, btreg, val) 1405 void *v; 1406 u_int btreg; 1407 u_int8_t val; 1408 { 1409 struct tga_devconfig *dc = v; 1410 bus_space_handle_t ramdac; 1411 1412 if (btreg > BT485_REG_MAX) 1413 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1414 1415 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1416 (0xe << 12) + (btreg << 8), 4, &ramdac); 1417 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1418 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1419 } 1420 1421 static u_int8_t 1422 tga_bt463_rd(v, btreg) 1423 void *v; 1424 u_int btreg; 1425 { 1426 struct tga_devconfig *dc = v; 1427 tga_reg_t rdval; 1428 1429 /* 1430 * Strobe CE# (high->low->high) since status and data are latched on 1431 * the falling and rising edges (repsectively) of this active-low signal. 1432 */ 1433 1434 TGAREGWB(dc, TGA_REG_EPSR, 1); 1435 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1436 TGAREGWB(dc, TGA_REG_EPSR, 1); 1437 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1438 1439 TGAREGRB(dc, TGA_REG_EPSR, 1); 1440 1441 rdval = TGARREG(dc, TGA_REG_EPDR); 1442 TGAREGWB(dc, TGA_REG_EPSR, 1); 1443 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1444 1445 return (rdval >> 16) & 0xff; 1446 } 1447 1448 static void 1449 tga_bt463_wr(v, btreg, val) 1450 void *v; 1451 u_int btreg; 1452 u_int8_t val; 1453 { 1454 struct tga_devconfig *dc = v; 1455 1456 /* 1457 * In spite of the 21030 documentation, to set the MPU bus bits for 1458 * a write, you set them in the upper bits of EPDR, not EPSR. 1459 */ 1460 1461 /* 1462 * Strobe CE# (high->low->high) since status and data are latched on 1463 * the falling and rising edges of this active-low signal. 1464 */ 1465 1466 TGAREGWB(dc, TGA_REG_EPDR, 1); 1467 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1468 TGAREGWB(dc, TGA_REG_EPDR, 1); 1469 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1470 TGAREGWB(dc, TGA_REG_EPDR, 1); 1471 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1472 1473 } 1474 1475 static u_int8_t 1476 tga_ramdac_rd(v, btreg) 1477 void *v; 1478 u_int btreg; 1479 { 1480 struct tga_devconfig *dc = v; 1481 tga_reg_t rdval; 1482 1483 if (btreg > BT485_REG_MAX) 1484 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1485 1486 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1487 TGAREGWB(dc, TGA_REG_EPSR, 1); 1488 1489 rdval = TGARREG(dc, TGA_REG_EPDR); 1490 return (rdval >> 16) & 0xff; /* XXX */ 1491 } 1492 1493 static u_int8_t 1494 tga2_ramdac_rd(v, btreg) 1495 void *v; 1496 u_int btreg; 1497 { 1498 struct tga_devconfig *dc = v; 1499 bus_space_handle_t ramdac; 1500 u_int8_t retval; 1501 1502 if (btreg > BT485_REG_MAX) 1503 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1504 1505 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1506 (0xe << 12) + (btreg << 8), 4, &ramdac); 1507 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1508 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1509 return retval; 1510 } 1511 1512 #include <dev/ic/decmonitors.c> 1513 void tga2_ics9110_wr __P(( 1514 struct tga_devconfig *dc, 1515 int dotclock 1516 )); 1517 1518 struct monitor *tga_getmonitor __P((struct tga_devconfig *dc)); 1519 1520 void 1521 tga2_init(dc) 1522 struct tga_devconfig *dc; 1523 { 1524 struct monitor *m = tga_getmonitor(dc); 1525 1526 /* Deal with the dot clocks. 1527 */ 1528 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1529 /* Set this up as a reference clock for the 1530 * ibm561's PLL. 1531 */ 1532 tga2_ics9110_wr(dc, 14300000); 1533 /* XXX Can't set up the dotclock properly, until such time 1534 * as the RAMDAC is configured. 1535 */ 1536 } else { 1537 /* otherwise the ics9110 is our clock. */ 1538 tga2_ics9110_wr(dc, m->dotclock); 1539 } 1540 #if 0 1541 TGAWREG(dc, TGA_REG_VHCR, 1542 ((m->hbp / 4) << 21) | 1543 ((m->hsync / 4) << 14) | 1544 (((m->hfp - 4) / 4) << 9) | 1545 ((m->cols + 4) / 4)); 1546 #else 1547 TGAWREG(dc, TGA_REG_VHCR, 1548 ((m->hbp / 4) << 21) | 1549 ((m->hsync / 4) << 14) | 1550 (((m->hfp) / 4) << 9) | 1551 ((m->cols) / 4)); 1552 #endif 1553 TGAWREG(dc, TGA_REG_VVCR, 1554 (m->vbp << 22) | 1555 (m->vsync << 16) | 1556 (m->vfp << 11) | 1557 (m->rows)); 1558 TGAWREG(dc, TGA_REG_VVBR, 1); 1559 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1560 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1561 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1562 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1563 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1564 } 1565 1566 void 1567 tga2_ics9110_wr(dc, dotclock) 1568 struct tga_devconfig *dc; 1569 int dotclock; 1570 { 1571 bus_space_handle_t clock; 1572 u_int32_t valU; 1573 int N, M, R, V, X; 1574 int i; 1575 1576 switch (dotclock) { 1577 case 130808000: 1578 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1579 case 119840000: 1580 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1581 case 108180000: 1582 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1583 case 103994000: 1584 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1585 case 175000000: 1586 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1587 case 75000000: 1588 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1589 case 74000000: 1590 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1591 case 69000000: 1592 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1593 case 65000000: 1594 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1595 case 50000000: 1596 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1597 case 40000000: 1598 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1599 case 31500000: 1600 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1601 case 25175000: 1602 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1603 case 135000000: 1604 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1605 case 110000000: 1606 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1607 case 202500000: 1608 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1609 case 14300000: /* this one is just a ref clock */ 1610 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1611 default: 1612 panic("unrecognized clock rate %d\n", dotclock); 1613 } 1614 1615 /* XXX -- hard coded, bad */ 1616 valU = N | ( M << 7 ) | (V << 14); 1617 valU |= (X << 15) | (R << 17); 1618 valU |= 0x17 << 19; 1619 1620 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1621 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1622 1623 for (i=24; i>0; i--) { 1624 u_int32_t writeval; 1625 1626 writeval = valU & 0x1; 1627 if (i == 1) 1628 writeval |= 0x2; 1629 valU >>= 1; 1630 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1631 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1632 } 1633 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1634 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1635 &clock); /* XXX */ 1636 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1637 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1638 } 1639 1640 struct monitor * 1641 tga_getmonitor(dc) 1642 struct tga_devconfig *dc; 1643 { 1644 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1645 } 1646 1647 unsigned 1648 tga_getdotclock(dc) 1649 struct tga_devconfig *dc; 1650 { 1651 return tga_getmonitor(dc)->dotclock; 1652 } 1653