1 /* $NetBSD: tga.c,v 1.45 2002/09/16 17:12:07 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.45 2002/09/16 17:12:07 mycroft Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/tgareg.h> 49 #include <dev/pci/tgavar.h> 50 #include <dev/ic/bt485reg.h> 51 #include <dev/ic/bt485var.h> 52 #include <dev/ic/bt463reg.h> 53 #include <dev/ic/bt463var.h> 54 #include <dev/ic/ibm561var.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wscons/wscons_raster.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <uvm/uvm_extern.h> 61 62 #ifdef __alpha__ 63 #include <machine/pte.h> 64 #endif 65 #ifdef __mips__ 66 #include <mips/pte.h> 67 #endif 68 69 int tgamatch __P((struct device *, struct cfdata *, void *)); 70 void tgaattach __P((struct device *, struct device *, void *)); 71 int tgaprint __P((void *, const char *)); 72 73 struct cfattach tga_ca = { 74 sizeof(struct tga_softc), tgamatch, tgaattach, 75 }; 76 77 int tga_identify __P((struct tga_devconfig *)); 78 const struct tga_conf *tga_getconf __P((int)); 79 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 80 pcitag_t tag, struct tga_devconfig *dc)); 81 82 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t)); 83 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 84 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc)); 85 unsigned tga_getdotclock __P((struct tga_devconfig *dc)); 86 87 struct tga_devconfig tga_console_dc; 88 89 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 90 paddr_t tga_mmap __P((void *, off_t, int)); 91 static void tga_copyrows __P((void *, int, int, int)); 92 static void tga_copycols __P((void *, int, int, int, int)); 93 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 94 void **, int *, int *, long *)); 95 static void tga_free_screen __P((void *, void *)); 96 static int tga_show_screen __P((void *, void *, int, 97 void (*) (void *, int, int), void *)); 98 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 99 struct rasops_info *, int, int)); 100 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 101 int, struct rasops_info *, int, int )); 102 static void tga_putchar __P((void *c, int row, int col, 103 u_int uc, long attr)); 104 static void tga_eraserows __P((void *, int, int, long)); 105 static void tga_erasecols __P((void *, int, int, int, long)); 106 void tga2_init __P((struct tga_devconfig *)); 107 108 static void tga_config_interrupts __P((struct device *)); 109 110 /* RAMDAC interface functions */ 111 static int tga_sched_update __P((void *, void (*)(void *))); 112 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 113 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 114 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 115 static u_int8_t tga_bt463_rd __P((void *, u_int)); 116 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 117 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 118 119 /* Interrupt handler */ 120 static int tga_intr __P((void *)); 121 122 /* The NULL entries will get filled in by rasops_init(). 123 * XXX and the non-NULL ones will be overwritten; reset after calling it. 124 */ 125 struct wsdisplay_emulops tga_emulops = { 126 NULL, 127 NULL, 128 tga_putchar, 129 tga_copycols, 130 tga_erasecols, 131 tga_copyrows, 132 tga_eraserows, 133 NULL, 134 }; 135 136 struct wsscreen_descr tga_stdscreen = { 137 "std", 138 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 139 &tga_emulops, 140 0, 0, 141 WSSCREEN_REVERSE 142 }; 143 144 const struct wsscreen_descr *_tga_scrlist[] = { 145 &tga_stdscreen, 146 /* XXX other formats, graphics screen? */ 147 }; 148 149 struct wsscreen_list tga_screenlist = { 150 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 151 }; 152 153 struct wsdisplay_accessops tga_accessops = { 154 tga_ioctl, 155 tga_mmap, 156 tga_alloc_screen, 157 tga_free_screen, 158 tga_show_screen, 159 0 /* load_font */ 160 }; 161 162 static void tga_blank __P((struct tga_devconfig *)); 163 static void tga_unblank __P((struct tga_devconfig *)); 164 165 int 166 tga_cnmatch(iot, memt, pc, tag) 167 bus_space_tag_t iot, memt; 168 pci_chipset_tag_t pc; 169 pcitag_t tag; 170 { 171 return tga_matchcommon(memt, pc, tag); 172 } 173 174 int 175 tgamatch(parent, match, aux) 176 struct device *parent; 177 struct cfdata *match; 178 void *aux; 179 { 180 struct pci_attach_args *pa = aux; 181 182 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 183 return (0); 184 185 switch (PCI_PRODUCT(pa->pa_id)) { 186 case PCI_PRODUCT_DEC_21030: 187 case PCI_PRODUCT_DEC_PBXGB: 188 break; 189 default: 190 return 0; 191 } 192 193 /* short-circuit the following test, as we 194 * already have the memory mapped and hence 195 * cannot perform it---and we are the console 196 * anyway. 197 */ 198 if (pa->pa_tag == tga_console_dc.dc_pcitag) 199 return 10; 200 201 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 202 } 203 204 static int 205 tga_matchcommon(memt, pc, tag) 206 bus_space_tag_t memt; 207 pci_chipset_tag_t pc; 208 pcitag_t tag; 209 { 210 struct tga_devconfig tmp_dc; 211 struct tga_devconfig *dc = &tmp_dc; 212 bus_size_t pcisize; 213 214 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 215 dc->dc_tga_type = tga_identify(dc); 216 217 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 218 bus_space_unmap(memt, dc->dc_memh, pcisize); 219 if (dc->dc_tgaconf) 220 return 10; 221 return 0; 222 } 223 224 static void 225 tga_mapaddrs(memt, pc, tag, pcisize, dc) 226 bus_space_tag_t memt; 227 pci_chipset_tag_t pc; 228 pcitag_t tag; 229 bus_size_t *pcisize; 230 struct tga_devconfig *dc; 231 { 232 int flags; 233 234 dc->dc_memt = memt; 235 dc->dc_tgaconf = NULL; 236 237 /* XXX magic number */ 238 if (pci_mapreg_info(pc, tag, 0x10, 239 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 240 &dc->dc_pcipaddr, pcisize, &flags)) 241 panic("tga_mapaddrs: pci_mapreg_info() failed"); 242 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 243 panic("tga memory not prefetchable"); 244 245 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 246 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 247 panic("tga_mapaddrs: could not map TGA address space"); 248 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 249 250 bus_space_subregion(dc->dc_memt, dc->dc_memh, 251 TGA_MEM_CREGS, TGA_CREGS_SIZE, 252 &dc->dc_regs); 253 } 254 255 static void 256 tga_init(memt, pc, tag, dc) 257 bus_space_tag_t memt; 258 pci_chipset_tag_t pc; 259 pcitag_t tag; 260 struct tga_devconfig *dc; 261 { 262 const struct tga_conf *tgac; 263 struct rasops_info *rip; 264 int cookie; 265 bus_size_t pcisize; 266 int i; 267 268 dc->dc_pcitag = tag; 269 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 270 dc->dc_tga_type = tga_identify(dc); 271 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 272 #if 0 273 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 274 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 275 panic("tga_init: memory size mismatch?"); 276 #endif 277 278 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 279 case 0x01: 280 case 0x02: 281 case 0x03: 282 case 0x04: 283 dc->dc_tga2 = 0; 284 break; 285 case 0x20: 286 case 0x21: 287 case 0x22: 288 dc->dc_tga2 = 1; 289 break; 290 default: 291 panic("tga_init: TGA Revision not recognized"); 292 } 293 294 if (dc->dc_tga2) 295 tga2_init(dc); 296 297 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 298 case 0: 299 dc->dc_wid = 8192; 300 break; 301 302 case 1: 303 dc->dc_wid = 8196; 304 break; 305 306 default: 307 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 308 break; 309 } 310 311 /* 312 * XXX XXX Turning off "odd" shouldn't be necessary, 313 * XXX XXX but I can't make X work with the weird size. 314 */ 315 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 316 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 317 TGAWREG(dc, TGA_REG_VHCR, 318 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 319 dc->dc_wid -= 4; 320 } 321 322 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 323 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 324 325 /* XXX this seems to be what DEC does */ 326 TGAWREG(dc, TGA_REG_CCBR, 0); 327 TGAWREG(dc, TGA_REG_VVBR, 1); 328 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 329 1 * tgac->tgac_vvbr_units; 330 dc->dc_blanked = 1; 331 tga_unblank(dc); 332 333 /* 334 * Set all bits in the pixel mask, to enable writes to all pixels. 335 * It seems that the console firmware clears some of them 336 * under some circumstances, which causes cute vertical stripes. 337 */ 338 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 339 340 /* clear the screen */ 341 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 342 *(u_int32_t *)(dc->dc_videobase + i) = 0; 343 344 /* Initialize rasops descriptor */ 345 rip = &dc->dc_rinfo; 346 rip->ri_flg = RI_CENTER; 347 rip->ri_depth = tgac->tgac_phys_depth; 348 rip->ri_bits = (void *)dc->dc_videobase; 349 rip->ri_width = dc->dc_wid; 350 rip->ri_height = dc->dc_ht; 351 rip->ri_stride = dc->dc_rowbytes; 352 rip->ri_hw = dc; 353 354 if (tgac->tgac_phys_depth == 32) { 355 rip->ri_rnum = 8; 356 rip->ri_gnum = 8; 357 rip->ri_bnum = 8; 358 rip->ri_rpos = 16; 359 rip->ri_gpos = 8; 360 rip->ri_bpos = 0; 361 } 362 363 wsfont_init(); 364 /* prefer 8 pixel wide font */ 365 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 366 WSDISPLAY_FONTORDER_L2R); 367 if (cookie <= 0) 368 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 369 WSDISPLAY_FONTORDER_L2R); 370 if (cookie <= 0) { 371 printf("tga: no appropriate fonts.\n"); 372 return; 373 } 374 375 /* the accelerated tga_putchar() needs LSbit left */ 376 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 377 printf("tga: couldn't lock font\n"); 378 return; 379 } 380 dc->dc_rinfo.ri_wsfcookie = cookie; 381 382 rasops_init(rip, 34, 80); 383 384 /* add our accelerated functions */ 385 /* XXX shouldn't have to do this; rasops should leave non-NULL 386 * XXX entries alone. 387 */ 388 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 389 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 390 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 391 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 392 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 393 394 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 395 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 396 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 397 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 398 399 400 dc->dc_intrenabled = 0; 401 } 402 403 void 404 tgaattach(parent, self, aux) 405 struct device *parent, *self; 406 void *aux; 407 { 408 struct pci_attach_args *pa = aux; 409 struct tga_softc *sc = (struct tga_softc *)self; 410 struct wsemuldisplaydev_attach_args aa; 411 pci_intr_handle_t intrh; 412 const char *intrstr; 413 u_int8_t rev; 414 int console; 415 416 #if defined(__alpha__) || defined(arc) 417 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 418 #else 419 console = 0; 420 #endif 421 if (console) { 422 sc->sc_dc = &tga_console_dc; 423 sc->nscreens = 1; 424 } else { 425 sc->sc_dc = (struct tga_devconfig *) 426 malloc(sizeof(struct tga_devconfig), M_DEVBUF, 427 M_WAITOK|M_ZERO); 428 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 429 } 430 if (sc->sc_dc->dc_vaddr == NULL) { 431 printf(": couldn't map memory space; punt!\n"); 432 return; 433 } 434 435 /* XXX say what's going on. */ 436 intrstr = NULL; 437 if (pci_intr_map(pa, &intrh)) { 438 printf(": couldn't map interrupt"); 439 return; 440 } 441 intrstr = pci_intr_string(pa->pa_pc, intrh); 442 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 443 sc->sc_dc); 444 if (sc->sc_intr == NULL) { 445 printf(": couldn't establish interrupt"); 446 if (intrstr != NULL) 447 printf("at %s", intrstr); 448 printf("\n"); 449 return; 450 } 451 452 rev = PCI_REVISION(pa->pa_class); 453 switch (rev) { 454 case 0x1: 455 case 0x2: 456 case 0x3: 457 printf(": DC21030 step %c", 'A' + rev - 1); 458 break; 459 case 0x20: 460 printf(": TGA2 abstract software model"); 461 break; 462 case 0x21: 463 case 0x22: 464 printf(": TGA2 pass %d", rev - 0x20); 465 break; 466 467 default: 468 printf("unknown stepping (0x%x)", rev); 469 break; 470 } 471 printf(", "); 472 473 /* 474 * Get RAMDAC function vectors and call the RAMDAC functions 475 * to allocate its private storage and pass that back to us. 476 */ 477 478 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 479 if (!sc->sc_dc->dc_tga2) { 480 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 481 sc->sc_dc->dc_ramdac_cookie = 482 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 483 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 484 else 485 sc->sc_dc->dc_ramdac_cookie = 486 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 487 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 488 } else { 489 sc->sc_dc->dc_ramdac_cookie = 490 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 491 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 492 493 /* XXX this is a bit of a hack, setting the dotclock here */ 494 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 495 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 496 (sc->sc_dc->dc_ramdac_cookie, 497 tga_getdotclock(sc->sc_dc)); 498 } 499 500 /* 501 * Initialize the RAMDAC. Initialization includes disabling 502 * cursor, setting a sane colormap, etc. We presume that we've 503 * filled in the necessary dot clock for PowerStorm 4d20. 504 */ 505 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 506 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 507 508 if (sc->sc_dc->dc_tgaconf == NULL) { 509 printf("unknown board configuration\n"); 510 return; 511 } 512 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 513 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 514 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 515 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 516 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 517 518 if (intrstr != NULL) 519 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 520 intrstr); 521 522 aa.console = console; 523 aa.scrdata = &tga_screenlist; 524 aa.accessops = &tga_accessops; 525 aa.accesscookie = sc; 526 527 config_found(self, &aa, wsemuldisplaydevprint); 528 529 config_interrupts(self, tga_config_interrupts); 530 } 531 532 static void 533 tga_config_interrupts (d) 534 struct device *d; 535 { 536 struct tga_softc *sc = (struct tga_softc *)d; 537 sc->sc_dc->dc_intrenabled = 1; 538 } 539 540 int 541 tga_ioctl(v, cmd, data, flag, p) 542 void *v; 543 u_long cmd; 544 caddr_t data; 545 int flag; 546 struct proc *p; 547 { 548 struct tga_softc *sc = v; 549 struct tga_devconfig *dc = sc->sc_dc; 550 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 551 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 552 553 switch (cmd) { 554 case WSDISPLAYIO_GTYPE: 555 *(u_int *)data = WSDISPLAY_TYPE_TGA; 556 return (0); 557 558 case WSDISPLAYIO_GINFO: 559 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 560 wsd_fbip->height = sc->sc_dc->dc_ht; 561 wsd_fbip->width = sc->sc_dc->dc_wid; 562 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 563 #if 0 564 wsd_fbip->cmsize = 256; /* XXX ??? */ 565 #else 566 wsd_fbip->cmsize = 1024; /* XXX ??? */ 567 #endif 568 #undef wsd_fbip 569 return (0); 570 571 case WSDISPLAYIO_GETCMAP: 572 return (*dcrf->ramdac_get_cmap)(dcrc, 573 (struct wsdisplay_cmap *)data); 574 575 case WSDISPLAYIO_PUTCMAP: 576 return (*dcrf->ramdac_set_cmap)(dcrc, 577 (struct wsdisplay_cmap *)data); 578 579 case WSDISPLAYIO_SVIDEO: 580 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 581 tga_blank(sc->sc_dc); 582 else 583 tga_unblank(sc->sc_dc); 584 return (0); 585 586 case WSDISPLAYIO_GVIDEO: 587 *(u_int *)data = dc->dc_blanked ? 588 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 589 return (0); 590 591 case WSDISPLAYIO_GCURPOS: 592 return (*dcrf->ramdac_get_curpos)(dcrc, 593 (struct wsdisplay_curpos *)data); 594 595 case WSDISPLAYIO_SCURPOS: 596 return (*dcrf->ramdac_set_curpos)(dcrc, 597 (struct wsdisplay_curpos *)data); 598 599 case WSDISPLAYIO_GCURMAX: 600 return (*dcrf->ramdac_get_curmax)(dcrc, 601 (struct wsdisplay_curpos *)data); 602 603 case WSDISPLAYIO_GCURSOR: 604 return (*dcrf->ramdac_get_cursor)(dcrc, 605 (struct wsdisplay_cursor *)data); 606 607 case WSDISPLAYIO_SCURSOR: 608 return (*dcrf->ramdac_set_cursor)(dcrc, 609 (struct wsdisplay_cursor *)data); 610 } 611 return (EPASSTHROUGH); 612 } 613 614 static int 615 tga_sched_update(v, f) 616 void *v; 617 void (*f) __P((void *)); 618 { 619 struct tga_devconfig *dc = v; 620 621 if (dc->dc_intrenabled) { 622 /* Arrange for f to be called at the next end-of-frame interrupt */ 623 dc->dc_ramdac_intr = f; 624 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 625 } else { 626 /* Spin until the end-of-frame, then call f */ 627 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 628 TGAREGWB(dc, TGA_REG_SISR, 1); 629 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 630 ; 631 f(dc->dc_ramdac_cookie); 632 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 633 TGAREGWB(dc, TGA_REG_SISR, 1); 634 } 635 636 return 0; 637 } 638 639 static int 640 tga_intr(v) 641 void *v; 642 { 643 struct tga_devconfig *dc = v; 644 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 645 646 u_int32_t reg; 647 648 reg = TGARREG(dc, TGA_REG_SISR); 649 if (( reg & 0x00010001) != 0x00010001) { 650 /* Odd. We never set any of the other interrupt enables. */ 651 if ((reg & 0x1f) != 0) { 652 /* Clear the mysterious pending interrupts. */ 653 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 654 TGAREGWB(dc, TGA_REG_SISR, 1); 655 /* This was our interrupt, even if we're puzzled as to why 656 * we got it. Don't make the interrupt handler think it 657 * was a stray. 658 */ 659 return -1; 660 } else { 661 return 0; 662 } 663 } 664 /* if we have something to do, do it */ 665 if (dc->dc_ramdac_intr) { 666 dc->dc_ramdac_intr(dcrc); 667 dc->dc_ramdac_intr = NULL; 668 } 669 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 670 TGAREGWB(dc, TGA_REG_SISR, 1); 671 return (1); 672 } 673 674 paddr_t 675 tga_mmap(v, offset, prot) 676 void *v; 677 off_t offset; 678 int prot; 679 { 680 struct tga_softc *sc = v; 681 682 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 683 return -1; 684 685 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 686 offset, prot, BUS_SPACE_MAP_LINEAR)); 687 } 688 689 static int 690 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 691 void *v; 692 const struct wsscreen_descr *type; 693 void **cookiep; 694 int *curxp, *curyp; 695 long *attrp; 696 { 697 struct tga_softc *sc = v; 698 long defattr; 699 700 if (sc->nscreens > 0) 701 return (ENOMEM); 702 703 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 704 *curxp = 0; 705 *curyp = 0; 706 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 707 0, 0, 0, &defattr); 708 *attrp = defattr; 709 sc->nscreens++; 710 return (0); 711 } 712 713 static void 714 tga_free_screen(v, cookie) 715 void *v; 716 void *cookie; 717 { 718 struct tga_softc *sc = v; 719 720 if (sc->sc_dc == &tga_console_dc) 721 panic("tga_free_screen: console"); 722 723 sc->nscreens--; 724 } 725 726 static int 727 tga_show_screen(v, cookie, waitok, cb, cbarg) 728 void *v; 729 void *cookie; 730 int waitok; 731 void (*cb) __P((void *, int, int)); 732 void *cbarg; 733 { 734 735 return (0); 736 } 737 738 int 739 tga_cnattach(iot, memt, pc, bus, device, function) 740 bus_space_tag_t iot, memt; 741 pci_chipset_tag_t pc; 742 int bus, device, function; 743 { 744 struct tga_devconfig *dcp = &tga_console_dc; 745 long defattr; 746 747 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 748 749 /* sanity checks */ 750 if (dcp->dc_vaddr == NULL) 751 panic("tga_console(%d, %d): couldn't map memory space", 752 device, function); 753 if (dcp->dc_tgaconf == NULL) 754 panic("tga_console(%d, %d): unknown board configuration", 755 device, function); 756 757 /* 758 * Initialize the RAMDAC but DO NOT allocate any private storage. 759 * Initialization includes disabling cursor, setting a sane 760 * colormap, etc. It will be reinitialized in tgaattach(). 761 */ 762 if (dcp->dc_tga2) { 763 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 764 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 765 tga2_ramdac_rd); 766 else 767 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 768 tga2_ramdac_rd, tga_getdotclock(dcp)); 769 } else { 770 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 771 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 772 tga_ramdac_rd); 773 else { 774 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 775 tga_bt463_rd); 776 } 777 } 778 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 779 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 780 781 return(0); 782 } 783 784 /* 785 * Functions to blank and unblank the display. 786 */ 787 static void 788 tga_blank(dc) 789 struct tga_devconfig *dc; 790 { 791 792 if (!dc->dc_blanked) { 793 dc->dc_blanked = 1; 794 /* XXX */ 795 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 796 } 797 } 798 799 static void 800 tga_unblank(dc) 801 struct tga_devconfig *dc; 802 { 803 804 if (dc->dc_blanked) { 805 dc->dc_blanked = 0; 806 /* XXX */ 807 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 808 } 809 } 810 811 /* 812 * Functions to manipulate the built-in cursor handing hardware. 813 */ 814 int 815 tga_builtin_set_cursor(dc, cursorp) 816 struct tga_devconfig *dc; 817 struct wsdisplay_cursor *cursorp; 818 { 819 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 820 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 821 u_int count, v; 822 int error; 823 824 v = cursorp->which; 825 if (v & WSDISPLAY_CURSOR_DOCMAP) { 826 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 827 if (error) 828 return (error); 829 } 830 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 831 if ((u_int)cursorp->size.x != 64 || 832 (u_int)cursorp->size.y > 64) 833 return (EINVAL); 834 /* The cursor is 2 bits deep, and there is no mask */ 835 count = (cursorp->size.y * 64 * 2) / NBBY; 836 if (!uvm_useracc(cursorp->image, count, B_READ)) 837 return (EFAULT); 838 } 839 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 840 return EINVAL; 841 842 /* parameters are OK; do it */ 843 if (v & WSDISPLAY_CURSOR_DOCUR) { 844 if (cursorp->enable) 845 /* XXX */ 846 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 847 else 848 /* XXX */ 849 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 850 } 851 if (v & WSDISPLAY_CURSOR_DOPOS) { 852 TGAWREG(dc, TGA_REG_CXYR, 853 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 854 } 855 if (v & WSDISPLAY_CURSOR_DOCMAP) { 856 /* can't fail. */ 857 dcrf->ramdac_set_curcmap(dcrc, cursorp); 858 } 859 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 860 count = ((64 * 2) / NBBY) * cursorp->size.y; 861 TGAWREG(dc, TGA_REG_CCBR, 862 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 863 copyin(cursorp->image, (char *)(dc->dc_vaddr + 864 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 865 count); /* can't fail. */ 866 } 867 return (0); 868 } 869 870 int 871 tga_builtin_get_cursor(dc, cursorp) 872 struct tga_devconfig *dc; 873 struct wsdisplay_cursor *cursorp; 874 { 875 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 876 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 877 int count, error; 878 879 cursorp->which = WSDISPLAY_CURSOR_DOALL & 880 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 881 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 882 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 883 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 884 cursorp->size.x = 64; 885 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 886 887 if (cursorp->image != NULL) { 888 count = (cursorp->size.y * 64 * 2) / NBBY; 889 error = copyout((char *)(dc->dc_vaddr + 890 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 891 cursorp->image, count); 892 if (error) 893 return (error); 894 /* No mask */ 895 } 896 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 897 return (error); 898 } 899 900 int 901 tga_builtin_set_curpos(dc, curposp) 902 struct tga_devconfig *dc; 903 struct wsdisplay_curpos *curposp; 904 { 905 906 TGAWREG(dc, TGA_REG_CXYR, 907 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 908 return (0); 909 } 910 911 int 912 tga_builtin_get_curpos(dc, curposp) 913 struct tga_devconfig *dc; 914 struct wsdisplay_curpos *curposp; 915 { 916 917 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 918 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 919 return (0); 920 } 921 922 int 923 tga_builtin_get_curmax(dc, curposp) 924 struct tga_devconfig *dc; 925 struct wsdisplay_curpos *curposp; 926 { 927 928 curposp->x = curposp->y = 64; 929 return (0); 930 } 931 932 /* 933 * Copy columns (characters) in a row (line). 934 */ 935 static void 936 tga_copycols(id, row, srccol, dstcol, ncols) 937 void *id; 938 int row, srccol, dstcol, ncols; 939 { 940 struct rasops_info *ri = id; 941 int y, srcx, dstx, nx; 942 943 y = ri->ri_font->fontheight * row; 944 srcx = ri->ri_font->fontwidth * srccol; 945 dstx = ri->ri_font->fontwidth * dstcol; 946 nx = ri->ri_font->fontwidth * ncols; 947 948 tga_rop(ri, dstx, y, 949 nx, ri->ri_font->fontheight, RAS_SRC, 950 ri, srcx, y); 951 } 952 953 /* 954 * Copy rows (lines). 955 */ 956 static void 957 tga_copyrows(id, srcrow, dstrow, nrows) 958 void *id; 959 int srcrow, dstrow, nrows; 960 { 961 struct rasops_info *ri = id; 962 int srcy, dsty, ny; 963 964 srcy = ri->ri_font->fontheight * srcrow; 965 dsty = ri->ri_font->fontheight * dstrow; 966 ny = ri->ri_font->fontheight * nrows; 967 968 tga_rop(ri, 0, dsty, 969 ri->ri_emuwidth, ny, RAS_SRC, 970 ri, 0, srcy); 971 } 972 973 /* Do we need the src? */ 974 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 975 976 /* A mapping between our API and the TGA card */ 977 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 978 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 979 }; 980 981 /* 982 * Generic TGA raster op. 983 * This covers all possible raster ops, and 984 * clips the sizes and all of that. 985 */ 986 static int 987 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 988 struct rasops_info *dst; 989 int dx, dy, w, h, rop; 990 struct rasops_info *src; 991 int sx, sy; 992 { 993 if (!dst) 994 return -1; 995 if (needsrc[RAS_GETOP(rop)]) { 996 if (src == NULL) 997 return -1; /* We want a src */ 998 /* Clip against src */ 999 if (sx < 0) { 1000 w += sx; 1001 sx = 0; 1002 } 1003 if (sy < 0) { 1004 h += sy; 1005 sy = 0; 1006 } 1007 if (sx + w > src->ri_emuwidth) 1008 w = src->ri_emuwidth - sx; 1009 if (sy + h > src->ri_emuheight) 1010 h = src->ri_emuheight - sy; 1011 } else { 1012 if (src != NULL) 1013 return -1; /* We need no src */ 1014 } 1015 /* Clip against dst. We modify src regardless of using it, 1016 * since it really doesn't matter. 1017 */ 1018 if (dx < 0) { 1019 w += dx; 1020 sx -= dx; 1021 dx = 0; 1022 } 1023 if (dy < 0) { 1024 h += dy; 1025 sy -= dy; 1026 dy = 0; 1027 } 1028 if (dx + w > dst->ri_emuwidth) 1029 w = dst->ri_emuwidth - dx; 1030 if (dy + h > dst->ri_emuheight) 1031 h = dst->ri_emuheight - dy; 1032 if (w <= 0 || h <= 0) 1033 return 0; /* Vacuously true; */ 1034 if (!src) { 1035 /* XXX Punt! */ 1036 return -1; 1037 } 1038 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1039 } 1040 1041 1042 1043 /* 1044 * Video to Video raster ops. 1045 * This function deals with all raster ops that have a src and dst 1046 * that are on the card. 1047 */ 1048 static int 1049 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 1050 struct rasops_info *dst; 1051 int dx, dy, w, h, rop; 1052 struct rasops_info *src; 1053 int sx, sy; 1054 { 1055 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1056 int srcb, dstb, tga_srcb, tga_dstb; 1057 int x, y, wb; 1058 int xstart, xend, xdir; 1059 int ystart, yend, ydir, yinc; 1060 int xleft, lastx, lastleft; 1061 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1062 1063 /* 1064 * I don't yet want to deal with unaligned guys, really. And we don't 1065 * deal with copies from one card to another. 1066 */ 1067 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1068 /* XXX Punt! */ 1069 /* XXX should never happen, since it's only being used to 1070 * XXX copy 8-pixel-wide characters. 1071 */ 1072 return -1; 1073 } 1074 1075 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1076 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1077 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1078 (sx + src->ri_xorigin) * (src->ri_depth/8); 1079 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1080 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1081 1082 if (sy >= dy) { 1083 ystart = 0; 1084 yend = (h - 1) * dst->ri_stride; 1085 ydir = 1; 1086 } else { 1087 ystart = (h - 1) * dst->ri_stride; 1088 yend = 0; 1089 ydir = -1; 1090 } 1091 yinc = ydir * dst->ri_stride; 1092 1093 wb = w * (dst->ri_depth / 8); 1094 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1095 xstart = 0; 1096 xend = wb; 1097 xdir = 1; 1098 } else { /* copy backwards */ 1099 xstart = wb; 1100 xend = 0; 1101 xdir = -1; 1102 } 1103 1104 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1105 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1106 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1107 1108 /* 1109 * we have 3 sizes of pixels to move in X direction: 1110 * 4 * 64 (unrolled TGA ops) 1111 * 64 (single TGA op) 1112 * 4 (CPU, using long word) 1113 */ 1114 1115 if (xdir == 1) { /* move to the left */ 1116 1117 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1118 /* 4*64 byte chunks */ 1119 for (xleft = wb, x = xstart; xleft >= 4*64; 1120 x += 4*64, xleft -= 4*64) { 1121 1122 /* XXX XXX Eight writes to different addresses should fill 1123 * XXX XXX up the write buffers on 21064 and 21164 chips, 1124 * XXX XXX but later CPUs might have larger write buffers which 1125 * XXX XXX require further unrolling of this loop, or the 1126 * XXX XXX insertion of memory barriers. 1127 */ 1128 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1129 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1130 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1131 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1132 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1133 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1134 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1135 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1136 } 1137 1138 /* 64 byte chunks */ 1139 for (; xleft >= 64; x += 64, xleft -= 64) { 1140 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1141 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1142 } 1143 1144 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1145 } 1146 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1147 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1148 1149 if (lastleft) { 1150 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1151 /* 4 byte granularity */ 1152 for (x = lastx, xleft = lastleft; xleft >= 4; 1153 x += 4, xleft -= 4) { 1154 *(uint32_t *)(dst->ri_bits + dstb + y + x + 0 * 4) = 1155 *(uint32_t *)(dst->ri_bits + srcb + y + x + 0 * 4); 1156 } 1157 } 1158 } 1159 } 1160 else { /* above move to the left, below move to the right */ 1161 1162 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1163 /* 4*64 byte chunks */ 1164 for (xleft = wb, x = xstart; xleft >= 4*64; 1165 x -= 4*64, xleft -= 4*64) { 1166 1167 /* XXX XXX Eight writes to different addresses should fill 1168 * XXX XXX up the write buffers on 21064 and 21164 chips, 1169 * XXX XXX but later CPUs might have larger write buffers which 1170 * XXX XXX require further unrolling of this loop, or the 1171 * XXX XXX insertion of memory barriers. 1172 */ 1173 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1174 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1175 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x - 2 * 64); 1176 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x - 2 * 64); 1177 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x - 3 * 64); 1178 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x - 3 * 64); 1179 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x - 4 * 64); 1180 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x - 4 * 64); 1181 } 1182 1183 /* 64 byte chunks */ 1184 for (; xleft >= 64; x -= 64, xleft -= 64) { 1185 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x - 1 * 64); 1186 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x - 1 * 64); 1187 } 1188 1189 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1190 } 1191 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1192 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1193 1194 if (lastleft) { 1195 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1196 /* 4 byte granularity */ 1197 for (x = lastx, xleft = lastleft; xleft >= 4; 1198 x -= 4, xleft -= 4) { 1199 *(uint32_t *)(dst->ri_bits + dstb + y + x - 1 * 4) = 1200 *(uint32_t *)(dst->ri_bits + srcb + y + x - 1 * 4); 1201 } 1202 } 1203 } 1204 } 1205 return 0; 1206 } 1207 1208 1209 void tga_putchar (c, row, col, uc, attr) 1210 void *c; 1211 int row, col; 1212 u_int uc; 1213 long attr; 1214 { 1215 struct rasops_info *ri = c; 1216 struct tga_devconfig *dc = ri->ri_hw; 1217 int fs, height, width; 1218 u_char *fr; 1219 int32_t *rp; 1220 1221 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1222 1223 height = ri->ri_font->fontheight; 1224 width = ri->ri_font->fontwidth; 1225 1226 uc -= ri->ri_font->firstchar; 1227 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1228 fs = ri->ri_font->stride; 1229 1230 /* Set foreground and background color. XXX memoize this somehow? 1231 * The rasops code has already expanded the color entry to 32 bits 1232 * for us, even for 8-bit displays, so we don't have to do anything. 1233 */ 1234 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1235 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1236 1237 /* Set raster operation to "copy"... */ 1238 if (ri->ri_depth == 8) 1239 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1240 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1241 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1242 1243 /* Set which pixels we're drawing (of a possible 32). */ 1244 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1245 1246 /* Set drawing mode to opaque stipple. */ 1247 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1248 1249 /* Insert write barrier before actually sending data */ 1250 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1251 TGAREGWB(dc, TGA_REG_GMOR, 1); 1252 1253 while(height--) { 1254 /* The actual stipple write */ 1255 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1256 1257 fr += fs; 1258 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1259 } 1260 1261 /* Do underline */ 1262 if ((attr & 1) != 0) { 1263 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1264 *rp = 0xffffffff; 1265 } 1266 1267 /* Set grapics mode back to normal. */ 1268 TGAWREG(dc, TGA_REG_GMOR, 0); 1269 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1270 1271 } 1272 1273 static void 1274 tga_eraserows(c, row, num, attr) 1275 void *c; 1276 int row, num; 1277 long attr; 1278 { 1279 struct rasops_info *ri = c; 1280 struct tga_devconfig *dc = ri->ri_hw; 1281 int32_t color, lines, pixels; 1282 int32_t *rp; 1283 1284 color = ri->ri_devcmap[(attr >> 16) & 15]; 1285 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1286 lines = num * ri->ri_font->fontheight; 1287 pixels = ri->ri_emuwidth - 1; 1288 1289 /* Set fill color in block-color registers */ 1290 TGAWREG(dc, TGA_REG_GBCR0, color); 1291 TGAWREG(dc, TGA_REG_GBCR1, color); 1292 if (ri->ri_depth != 8) { 1293 TGAWREG(dc, TGA_REG_GBCR2, color); 1294 TGAWREG(dc, TGA_REG_GBCR3, color); 1295 TGAWREG(dc, TGA_REG_GBCR4, color); 1296 TGAWREG(dc, TGA_REG_GBCR5, color); 1297 TGAWREG(dc, TGA_REG_GBCR6, color); 1298 TGAWREG(dc, TGA_REG_GBCR7, color); 1299 } 1300 1301 /* Set raster operation to "copy"... */ 1302 if (ri->ri_depth == 8) 1303 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1304 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1305 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1306 1307 /* Set which pixels we're drawing (of a possible 32). */ 1308 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1309 1310 /* Set drawing mode to block fill. */ 1311 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1312 1313 /* Insert write barrier before actually sending data */ 1314 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1315 TGAREGWB(dc, TGA_REG_GMOR, 1); 1316 1317 while (lines--) { 1318 *rp = pixels; 1319 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1320 } 1321 1322 /* Set grapics mode back to normal. */ 1323 TGAWREG(dc, TGA_REG_GMOR, 0); 1324 1325 } 1326 1327 static void 1328 tga_erasecols (c, row, col, num, attr) 1329 void *c; 1330 int row, col, num; 1331 long attr; 1332 { 1333 struct rasops_info *ri = c; 1334 struct tga_devconfig *dc = ri->ri_hw; 1335 int32_t color, lines, pixels; 1336 int32_t *rp; 1337 1338 color = ri->ri_devcmap[(attr >> 16) & 15]; 1339 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1340 lines = ri->ri_font->fontheight; 1341 pixels = (num * ri->ri_font->fontwidth) - 1; 1342 1343 /* Set fill color in block-color registers */ 1344 TGAWREG(dc, TGA_REG_GBCR0, color); 1345 TGAWREG(dc, TGA_REG_GBCR1, color); 1346 if (ri->ri_depth != 8) { 1347 TGAWREG(dc, TGA_REG_GBCR2, color); 1348 TGAWREG(dc, TGA_REG_GBCR3, color); 1349 TGAWREG(dc, TGA_REG_GBCR4, color); 1350 TGAWREG(dc, TGA_REG_GBCR5, color); 1351 TGAWREG(dc, TGA_REG_GBCR6, color); 1352 TGAWREG(dc, TGA_REG_GBCR7, color); 1353 } 1354 1355 /* Set raster operation to "copy"... */ 1356 if (ri->ri_depth == 8) 1357 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1358 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1359 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1360 1361 /* Set which pixels we're drawing (of a possible 32). */ 1362 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1363 1364 /* Set drawing mode to block fill. */ 1365 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1366 1367 /* Insert write barrier before actually sending data */ 1368 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1369 TGAREGWB(dc, TGA_REG_GMOR, 1); 1370 1371 while (lines--) { 1372 *rp = pixels; 1373 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1374 } 1375 1376 /* Set grapics mode back to normal. */ 1377 TGAWREG(dc, TGA_REG_GMOR, 0); 1378 } 1379 1380 1381 static void 1382 tga_ramdac_wr(v, btreg, val) 1383 void *v; 1384 u_int btreg; 1385 u_int8_t val; 1386 { 1387 struct tga_devconfig *dc = v; 1388 1389 if (btreg > BT485_REG_MAX) 1390 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1391 1392 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1393 TGAREGWB(dc, TGA_REG_EPDR, 1); 1394 } 1395 1396 static void 1397 tga2_ramdac_wr(v, btreg, val) 1398 void *v; 1399 u_int btreg; 1400 u_int8_t val; 1401 { 1402 struct tga_devconfig *dc = v; 1403 bus_space_handle_t ramdac; 1404 1405 if (btreg > BT485_REG_MAX) 1406 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1407 1408 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1409 (0xe << 12) + (btreg << 8), 4, &ramdac); 1410 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1411 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1412 } 1413 1414 static u_int8_t 1415 tga_bt463_rd(v, btreg) 1416 void *v; 1417 u_int btreg; 1418 { 1419 struct tga_devconfig *dc = v; 1420 tga_reg_t rdval; 1421 1422 /* 1423 * Strobe CE# (high->low->high) since status and data are latched on 1424 * the falling and rising edges (repsectively) of this active-low signal. 1425 */ 1426 1427 TGAREGWB(dc, TGA_REG_EPSR, 1); 1428 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1429 TGAREGWB(dc, TGA_REG_EPSR, 1); 1430 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1431 1432 TGAREGRB(dc, TGA_REG_EPSR, 1); 1433 1434 rdval = TGARREG(dc, TGA_REG_EPDR); 1435 TGAREGWB(dc, TGA_REG_EPSR, 1); 1436 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1437 1438 return (rdval >> 16) & 0xff; 1439 } 1440 1441 static void 1442 tga_bt463_wr(v, btreg, val) 1443 void *v; 1444 u_int btreg; 1445 u_int8_t val; 1446 { 1447 struct tga_devconfig *dc = v; 1448 1449 /* 1450 * In spite of the 21030 documentation, to set the MPU bus bits for 1451 * a write, you set them in the upper bits of EPDR, not EPSR. 1452 */ 1453 1454 /* 1455 * Strobe CE# (high->low->high) since status and data are latched on 1456 * the falling and rising edges of this active-low signal. 1457 */ 1458 1459 TGAREGWB(dc, TGA_REG_EPDR, 1); 1460 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1461 TGAREGWB(dc, TGA_REG_EPDR, 1); 1462 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1463 TGAREGWB(dc, TGA_REG_EPDR, 1); 1464 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1465 1466 } 1467 1468 static u_int8_t 1469 tga_ramdac_rd(v, btreg) 1470 void *v; 1471 u_int btreg; 1472 { 1473 struct tga_devconfig *dc = v; 1474 tga_reg_t rdval; 1475 1476 if (btreg > BT485_REG_MAX) 1477 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1478 1479 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1480 TGAREGWB(dc, TGA_REG_EPSR, 1); 1481 1482 rdval = TGARREG(dc, TGA_REG_EPDR); 1483 return (rdval >> 16) & 0xff; /* XXX */ 1484 } 1485 1486 static u_int8_t 1487 tga2_ramdac_rd(v, btreg) 1488 void *v; 1489 u_int btreg; 1490 { 1491 struct tga_devconfig *dc = v; 1492 bus_space_handle_t ramdac; 1493 u_int8_t retval; 1494 1495 if (btreg > BT485_REG_MAX) 1496 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1497 1498 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1499 (0xe << 12) + (btreg << 8), 4, &ramdac); 1500 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1501 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1502 return retval; 1503 } 1504 1505 #include <dev/ic/decmonitors.c> 1506 void tga2_ics9110_wr __P(( 1507 struct tga_devconfig *dc, 1508 int dotclock 1509 )); 1510 1511 struct monitor *tga_getmonitor __P((struct tga_devconfig *dc)); 1512 1513 void 1514 tga2_init(dc) 1515 struct tga_devconfig *dc; 1516 { 1517 struct monitor *m = tga_getmonitor(dc); 1518 1519 /* Deal with the dot clocks. 1520 */ 1521 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1522 /* Set this up as a reference clock for the 1523 * ibm561's PLL. 1524 */ 1525 tga2_ics9110_wr(dc, 14300000); 1526 /* XXX Can't set up the dotclock properly, until such time 1527 * as the RAMDAC is configured. 1528 */ 1529 } else { 1530 /* otherwise the ics9110 is our clock. */ 1531 tga2_ics9110_wr(dc, m->dotclock); 1532 } 1533 #if 0 1534 TGAWREG(dc, TGA_REG_VHCR, 1535 ((m->hbp / 4) << 21) | 1536 ((m->hsync / 4) << 14) | 1537 (((m->hfp - 4) / 4) << 9) | 1538 ((m->cols + 4) / 4)); 1539 #else 1540 TGAWREG(dc, TGA_REG_VHCR, 1541 ((m->hbp / 4) << 21) | 1542 ((m->hsync / 4) << 14) | 1543 (((m->hfp) / 4) << 9) | 1544 ((m->cols) / 4)); 1545 #endif 1546 TGAWREG(dc, TGA_REG_VVCR, 1547 (m->vbp << 22) | 1548 (m->vsync << 16) | 1549 (m->vfp << 11) | 1550 (m->rows)); 1551 TGAWREG(dc, TGA_REG_VVBR, 1); 1552 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1553 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1554 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1555 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1556 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1557 } 1558 1559 void 1560 tga2_ics9110_wr(dc, dotclock) 1561 struct tga_devconfig *dc; 1562 int dotclock; 1563 { 1564 bus_space_handle_t clock; 1565 u_int32_t valU; 1566 int N, M, R, V, X; 1567 int i; 1568 1569 switch (dotclock) { 1570 case 130808000: 1571 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1572 case 119840000: 1573 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1574 case 108180000: 1575 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1576 case 103994000: 1577 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1578 case 175000000: 1579 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1580 case 75000000: 1581 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1582 case 74000000: 1583 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1584 case 69000000: 1585 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1586 case 65000000: 1587 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1588 case 50000000: 1589 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1590 case 40000000: 1591 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1592 case 31500000: 1593 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1594 case 25175000: 1595 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1596 case 135000000: 1597 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1598 case 110000000: 1599 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1600 case 202500000: 1601 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1602 case 14300000: /* this one is just a ref clock */ 1603 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1604 default: 1605 panic("unrecognized clock rate %d\n", dotclock); 1606 } 1607 1608 /* XXX -- hard coded, bad */ 1609 valU = N | ( M << 7 ) | (V << 14); 1610 valU |= (X << 15) | (R << 17); 1611 valU |= 0x17 << 19; 1612 1613 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1614 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1615 1616 for (i=24; i>0; i--) { 1617 u_int32_t writeval; 1618 1619 writeval = valU & 0x1; 1620 if (i == 1) 1621 writeval |= 0x2; 1622 valU >>= 1; 1623 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1624 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1625 } 1626 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1627 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1628 &clock); /* XXX */ 1629 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1630 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1631 } 1632 1633 struct monitor * 1634 tga_getmonitor(dc) 1635 struct tga_devconfig *dc; 1636 { 1637 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1638 } 1639 1640 unsigned 1641 tga_getdotclock(dc) 1642 struct tga_devconfig *dc; 1643 { 1644 return tga_getmonitor(dc)->dotclock; 1645 } 1646