1 /* $NetBSD: svwsata.c,v 1.16 2012/07/31 15:50:36 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Mark Kettenis 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.16 2012/07/31 15:50:36 bouyer Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 25 #include <dev/ata/atareg.h> 26 #include <dev/ata/satareg.h> 27 #include <dev/ata/satavar.h> 28 #include <dev/pci/pcivar.h> 29 #include <dev/pci/pcidevs.h> 30 #include <dev/pci/pciidereg.h> 31 #include <dev/pci/pciidevar.h> 32 #include <dev/pci/pciide_svwsata_reg.h> 33 34 static int svwsata_match(device_t, cfdata_t, void *); 35 static void svwsata_attach(device_t, device_t, void *); 36 37 static void svwsata_chip_map(struct pciide_softc *, 38 const struct pci_attach_args *); 39 static void svwsata_mapreg_dma(struct pciide_softc *, 40 const struct pci_attach_args *); 41 static void svwsata_mapchan(struct pciide_channel *); 42 43 CFATTACH_DECL_NEW(svwsata, sizeof(struct pciide_softc), 44 svwsata_match, svwsata_attach, NULL, NULL); 45 46 static const struct pciide_product_desc pciide_svwsata_products[] = { 47 { PCI_PRODUCT_SERVERWORKS_K2_SATA, 48 0, 49 "ServerWorks K2 SATA Controller", 50 svwsata_chip_map 51 }, 52 { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA, 53 0, 54 "ServerWorks Frodo4 SATA Controller", 55 svwsata_chip_map 56 }, 57 { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA, 58 0, 59 "ServerWorks Frodo8 SATA Controller", 60 svwsata_chip_map 61 }, 62 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_1, 63 0, 64 "ServerWorks HT-1000 SATA Controller", 65 svwsata_chip_map 66 }, 67 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_2, 68 0, 69 "ServerWorks HT-1000 SATA Controller", 70 svwsata_chip_map 71 }, 72 { 0, 73 0, 74 NULL, 75 NULL, 76 } 77 }; 78 79 static int 80 svwsata_match(device_t parent, cfdata_t match, void *aux) 81 { 82 struct pci_attach_args *pa = aux; 83 84 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 85 if (pciide_lookup_product(pa->pa_id, 86 pciide_svwsata_products)) 87 return (2); 88 } 89 return (0); 90 } 91 92 static void 93 svwsata_attach(device_t parent, device_t self, void *aux) 94 { 95 struct pci_attach_args *pa = aux; 96 struct pciide_softc *sc = device_private(self); 97 98 sc->sc_wdcdev.sc_atac.atac_dev = self; 99 100 pciide_common_attach(sc, pa, 101 pciide_lookup_product(pa->pa_id, pciide_svwsata_products)); 102 } 103 104 static void 105 svwsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 106 { 107 struct pciide_channel *cp; 108 pci_intr_handle_t intrhandle; 109 pcireg_t interface; 110 const char *intrstr; 111 int channel; 112 113 if (pciide_chipen(sc, pa) == 0) 114 return; 115 116 /* The 4-port version has a dummy second function. */ 117 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 118 PCI_MAPREG_START + 0x14) == 0) { 119 aprint_normal("\n"); 120 return; 121 } 122 123 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 124 PCI_MAPREG_TYPE_MEM | 125 PCI_MAPREG_MEM_TYPE_32BIT, 0, 126 &sc->sc_ba5_st, &sc->sc_ba5_sh, 127 NULL, &sc->sc_ba5_ss) != 0) { 128 aprint_error(": unable to map BA5 register space\n"); 129 return; 130 } 131 132 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 133 "bus-master DMA support present"); 134 svwsata_mapreg_dma(sc, pa); 135 aprint_verbose("\n"); 136 137 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 138 139 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 140 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 141 if (sc->sc_dma_ok) { 142 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 143 sc->sc_wdcdev.irqack = pciide_irqack; 144 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 145 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 146 } 147 148 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 149 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 150 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 151 152 /* We can use SControl and SStatus to probe for drives. */ 153 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 154 sc->sc_wdcdev.wdc_maxdrives = 1; 155 156 wdc_allocate_regs(&sc->sc_wdcdev); 157 158 /* Map and establish the interrupt handler. */ 159 if(pci_intr_map(pa, &intrhandle) != 0) { 160 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 161 "couldn't map native-PCI interrupt\n"); 162 return; 163 } 164 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 165 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 166 pciide_pci_intr, sc); 167 if (sc->sc_pci_ih != NULL) { 168 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 169 "using %s for native-PCI interrupt\n", 170 intrstr ? intrstr : "unknown interrupt"); 171 } else { 172 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 173 "couldn't establish native-PCI interrupt"); 174 if (intrstr != NULL) 175 aprint_error(" at %s", intrstr); 176 aprint_error("\n"); 177 return; 178 } 179 180 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 181 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 182 183 184 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 185 channel++) { 186 cp = &sc->pciide_channels[channel]; 187 188 if (pciide_chansetup(sc, channel, interface) == 0) 189 continue; 190 svwsata_mapchan(cp); 191 } 192 } 193 194 static void 195 svwsata_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 196 { 197 struct pciide_channel *pc; 198 int chan, reg; 199 bus_size_t size; 200 201 sc->sc_wdcdev.dma_arg = sc; 202 sc->sc_wdcdev.dma_init = pciide_dma_init; 203 sc->sc_wdcdev.dma_start = pciide_dma_start; 204 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 205 206 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 207 PCIIDE_OPTIONS_NODMA) { 208 aprint_normal( 209 ", but unused (forced off by config file)"); 210 sc->sc_dma_ok = 0; 211 return; 212 } 213 214 /* 215 * Slice off a subregion of BA5 for each of the channel's DMA 216 * registers. 217 */ 218 219 sc->sc_dma_iot = sc->sc_ba5_st; 220 for (chan = 0; chan < 4; chan++) { 221 pc = &sc->pciide_channels[chan]; 222 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 223 size = 4; 224 if (size > (IDEDMA_SCH_OFFSET - reg)) 225 size = IDEDMA_SCH_OFFSET - reg; 226 if (bus_space_subregion(sc->sc_ba5_st, 227 sc->sc_ba5_sh, 228 (chan << 8) + SVWSATA_DMA + reg, 229 size, &pc->dma_iohs[reg]) != 0) { 230 sc->sc_dma_ok = 0; 231 aprint_normal(", but can't subregion offset " 232 "%lu size %lu", 233 (u_long) (chan << 8) + SVWSATA_DMA + reg, 234 (u_long) size); 235 return; 236 } 237 } 238 } 239 240 /* DMA registers all set up! */ 241 sc->sc_dmat = pa->pa_dmat; 242 sc->sc_dma_ok = 1; 243 } 244 245 static void 246 svwsata_mapchan(struct pciide_channel *cp) 247 { 248 struct ata_channel *wdc_cp = &cp->ata_channel; 249 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 250 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 251 int i; 252 253 cp->compat = 0; 254 cp->ih = sc->sc_pci_ih; 255 256 wdr->cmd_iot = sc->sc_ba5_st; 257 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 258 (wdc_cp->ch_channel << 8) + SVWSATA_TF0, 259 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) { 260 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 261 "couldn't map %s cmd regs\n", cp->name); 262 goto bad; 263 } 264 265 wdr->ctl_iot = sc->sc_ba5_st; 266 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 267 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4, 268 &cp->ctl_baseioh) != 0) { 269 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 270 "couldn't map %s ctl regs\n", cp->name); 271 goto bad; 272 } 273 wdr->ctl_ioh = cp->ctl_baseioh; 274 275 for (i = 0; i < WDC_NREG; i++) { 276 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 277 i << 2, i == 0 ? 4 : 1, 278 &wdr->cmd_iohs[i]) != 0) { 279 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 280 "couldn't subregion %s channel cmd regs\n", 281 cp->name); 282 goto bad; 283 } 284 } 285 wdc_init_shadow_regs(wdc_cp); 286 wdr->data32iot = wdr->cmd_iot; 287 wdr->data32ioh = wdr->cmd_iohs[0]; 288 289 290 wdr->sata_iot = sc->sc_ba5_st; 291 wdr->sata_baseioh = sc->sc_ba5_sh; 292 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 293 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1, 294 &wdr->sata_status) != 0) { 295 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 296 "couldn't map channel %d sata_status regs\n", 297 wdc_cp->ch_channel); 298 goto bad; 299 } 300 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 301 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1, 302 &wdr->sata_error) != 0) { 303 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 304 "couldn't map channel %d sata_error regs\n", 305 wdc_cp->ch_channel); 306 goto bad; 307 } 308 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 309 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1, 310 &wdr->sata_control) != 0) { 311 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 312 "couldn't map channel %d sata_control regs\n", 313 wdc_cp->ch_channel); 314 goto bad; 315 } 316 317 wdcattach(wdc_cp); 318 return; 319 320 bad: 321 cp->ata_channel.ch_flags |= ATACH_DISABLED; 322 } 323