1 /* $NetBSD: stpcide.c,v 1.4 2004/01/03 22:56:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Toru Nishimura 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Toru Nishimura. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 static void stpc_chip_map(struct pciide_softc *, struct pci_attach_args *); 41 static void stpc_setup_channel(struct wdc_channel *); 42 43 static int stpcide_match(struct device *, struct cfdata *, void *); 44 static void stpcide_attach(struct device *, struct device *, void *); 45 46 const struct pciide_product_desc pciide_stpc_products[] = { 47 { 0x0228, 48 0, 49 "STMicroelectronics STPC IDE Controller", 50 stpc_chip_map, 51 }, 52 { 0, 0, NULL, NULL }, 53 }; 54 55 CFATTACH_DECL(stpcide, sizeof(struct pciide_softc), 56 stpcide_match, stpcide_attach, NULL, NULL); 57 58 static int 59 stpcide_match(struct device *parent, struct cfdata *match, void *aux) 60 { 61 struct pci_attach_args *pa = aux; 62 63 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SGSTHOMSON) { 64 if (pciide_lookup_product(pa->pa_id, pciide_stpc_products)) 65 return (2); 66 } 67 return (0); 68 } 69 70 static void 71 stpcide_attach(struct device *parent, struct device *self, void *aux) 72 { 73 struct pci_attach_args *pa = aux; 74 struct pciide_softc *sc = (struct pciide_softc *)self; 75 76 pciide_common_attach(sc, pa, 77 pciide_lookup_product(pa->pa_id, pciide_stpc_products)); 78 79 } 80 81 static void 82 stpc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 83 { 84 struct pciide_channel *cp; 85 int channel; 86 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 87 bus_size_t cmdsize, ctlsize; 88 89 if (pciide_chipen(sc, pa) == 0) 90 return; 91 92 aprint_normal("%s: bus-master DMA support present", 93 sc->sc_wdcdev.sc_dev.dv_xname); 94 pciide_mapreg_dma(sc, pa); 95 aprint_normal("\n"); 96 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 97 WDC_CAPABILITY_MODE; 98 if (sc->sc_dma_ok) { 99 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 100 sc->sc_wdcdev.irqack = pciide_irqack; 101 } 102 sc->sc_wdcdev.PIO_cap = 4; 103 sc->sc_wdcdev.DMA_cap = 2; 104 sc->sc_wdcdev.UDMA_cap = 0; 105 sc->sc_wdcdev.set_modes = stpc_setup_channel; 106 sc->sc_wdcdev.channels = sc->wdc_chanarray; 107 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 108 109 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 110 cp = &sc->pciide_channels[channel]; 111 if (pciide_chansetup(sc, channel, interface) == 0) 112 continue; 113 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 114 pciide_pci_intr); 115 } 116 } 117 118 /* 119 * IDE timing register (0x40, 0x42, 0x44, and 0x46) assignment. 120 * 33MHz PCI system will have; 121 * DMA0 01-11-11 122 * DMA1 00-01-10 123 * DMA2 00-00-10 124 * PIO0 111-100 125 * PIO1 100-011 126 * PIO2 011-010 127 * PIO3 010-001 128 * PIO4 000-001 129 * MISC XYZW 130 */ 131 static const u_int16_t dmatbl[] = { 0x7C00, 0x1800, 0x0800 }; 132 static const u_int16_t piotbl[] = { 0x03C0, 0x0230, 0x01A0, 0x0110, 0x0010 }; 133 134 static void 135 stpc_setup_channel(struct wdc_channel *chp) 136 { 137 struct pciide_channel *cp = (struct pciide_channel *)chp; 138 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 139 struct wdc_softc *wdc = &sc->sc_wdcdev; 140 int channel = chp->ch_channel; 141 struct ata_drive_datas *drvp; 142 u_int32_t idedma_ctl, idetim; 143 int drive, bits[2]; 144 145 /* setup DMA if needed */ 146 pciide_channel_dma_setup(cp); 147 148 idedma_ctl = 0; 149 bits[0] = bits[1] = 0x7F60; /* assume PIO2/DMA0 */ 150 151 /* Per drive settings */ 152 for (drive = 0; drive < 2; drive++) { 153 drvp = &chp->ch_drive[drive]; 154 /* If no drive, skip */ 155 if ((drvp->drive_flags & DRIVE) == 0) 156 continue; 157 /* add timing values, setup DMA if needed */ 158 if ((wdc->cap & WDC_CAPABILITY_DMA) && 159 (drvp->drive_flags & DRIVE_DMA)) { 160 /* use Multiword DMA */ 161 drvp->drive_flags &= ~DRIVE_UDMA; 162 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 163 bits[drive] = 0xe; /* IOCHRDY,wr/post,rd/prefetch */ 164 } 165 else { 166 /* PIO only */ 167 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 168 bits[drive] = 0x8; /* IOCHRDY */ 169 } 170 bits[drive] |= dmatbl[drvp->DMA_mode] | piotbl[drvp->PIO_mode]; 171 } 172 #if 0 173 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 174 (channel == 0) ? 0x40 : 0x44); 175 aprint_normal("wdc%d: IDETIM %08x -> %08x\n", 176 channel, idetim, (bits[1] << 16) | bits[0]); 177 #endif 178 idetim = (bits[1] << 16) | bits[0]; 179 pci_conf_write(sc->sc_pc, sc->sc_tag, 180 (channel == 0) ? 0x40 : 0x44, idetim); 181 182 if (idedma_ctl != 0) { 183 /* Add software bits in status register */ 184 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 185 idedma_ctl); 186 } 187 } 188