1 /* $NetBSD: siop_pci_common.c,v 1.19 2003/04/09 00:29:30 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.19 2003/04/09 00:29:30 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/kernel.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <dev/scsipi/scsipi_all.h> 53 #include <dev/scsipi/scsipiconf.h> 54 55 #include <dev/ic/siopreg.h> 56 #include <dev/ic/siopvar_common.h> 57 #include <dev/pci/siop_pci_common.h> 58 59 /* List (array, really :) of chips we know how to handle */ 60 const struct siop_product_desc siop_products[] = { 61 { PCI_PRODUCT_SYMBIOS_810, 62 0x00, 63 "Symbios Logic 53c810 (fast scsi)", 64 SF_PCI_RL | SF_CHIP_LS, 65 4, 8, 3, 250, 0 66 }, 67 { PCI_PRODUCT_SYMBIOS_810, 68 0x10, 69 "Symbios Logic 53c810a (fast scsi)", 70 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 71 4, 8, 3, 250, 0 72 }, 73 { PCI_PRODUCT_SYMBIOS_815, 74 0x00, 75 "Symbios Logic 53c815 (fast scsi)", 76 SF_PCI_RL | SF_PCI_BOF, 77 4, 8, 3, 250, 0 78 }, 79 { PCI_PRODUCT_SYMBIOS_820, 80 0x00, 81 "Symbios Logic 53c820 (fast wide scsi)", 82 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 83 4, 8, 3, 250, 0 84 }, 85 { PCI_PRODUCT_SYMBIOS_825, 86 0x00, 87 "Symbios Logic 53c825 (fast wide scsi)", 88 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 89 4, 8, 3, 250, 0 90 }, 91 { PCI_PRODUCT_SYMBIOS_825, 92 0x10, 93 "Symbios Logic 53c825a (fast wide scsi)", 94 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 95 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 96 SF_BUS_WIDE, 97 7, 8, 3, 250, 4096 98 }, 99 { PCI_PRODUCT_SYMBIOS_860, 100 0x00, 101 "Symbios Logic 53c860 (ultra scsi)", 102 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 103 SF_CHIP_PF | SF_CHIP_LS | 104 SF_BUS_ULTRA, 105 4, 8, 5, 125, 0 106 }, 107 { PCI_PRODUCT_SYMBIOS_875, 108 0x00, 109 "Symbios Logic 53c875 (ultra-wide scsi)", 110 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 111 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 112 SF_BUS_ULTRA | SF_BUS_WIDE, 113 7, 16, 5, 125, 4096 114 }, 115 { PCI_PRODUCT_SYMBIOS_875, 116 0x02, 117 "Symbios Logic 53c875 (ultra-wide scsi)", 118 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 119 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 120 SF_CHIP_LS | SF_CHIP_10REGS | 121 SF_BUS_ULTRA | SF_BUS_WIDE, 122 7, 16, 5, 125, 4096 123 }, 124 { PCI_PRODUCT_SYMBIOS_875J, 125 0x00, 126 "Symbios Logic 53c875j (ultra-wide scsi)", 127 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 128 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 129 SF_CHIP_LS | SF_CHIP_10REGS | 130 SF_BUS_ULTRA | SF_BUS_WIDE, 131 7, 16, 5, 125, 4096 132 }, 133 { PCI_PRODUCT_SYMBIOS_885, 134 0x00, 135 "Symbios Logic 53c885 (ultra-wide scsi)", 136 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 137 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 138 SF_CHIP_LS | SF_CHIP_10REGS | 139 SF_BUS_ULTRA | SF_BUS_WIDE, 140 7, 16, 5, 125, 4096 141 }, 142 { PCI_PRODUCT_SYMBIOS_895, 143 0x00, 144 "Symbios Logic 53c895 (ultra2-wide scsi)", 145 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 146 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 147 SF_CHIP_LS | SF_CHIP_10REGS | 148 SF_BUS_ULTRA2 | SF_BUS_WIDE, 149 7, 31, 7, 62, 4096 150 }, 151 { PCI_PRODUCT_SYMBIOS_896, 152 0x00, 153 "Symbios Logic 53c896 (ultra2-wide scsi)", 154 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 155 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 156 SF_CHIP_LS | SF_CHIP_10REGS | 157 SF_BUS_ULTRA2 | SF_BUS_WIDE, 158 7, 31, 7, 62, 8192 159 }, 160 { PCI_PRODUCT_SYMBIOS_895A, 161 0x00, 162 "Symbios Logic 53c895a (ultra2-wide scsi)", 163 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 164 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 165 SF_CHIP_LS | SF_CHIP_10REGS | 166 SF_BUS_ULTRA2 | SF_BUS_WIDE, 167 7, 31, 7, 62, 8192 168 }, 169 { PCI_PRODUCT_SYMBIOS_1010, 170 0x00, 171 "Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)", 172 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 173 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 174 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 175 SF_CHIP_GEBUG | 176 SF_BUS_ULTRA3 | SF_BUS_WIDE, 177 7, 31, 0, 62, 8192 178 }, 179 { PCI_PRODUCT_SYMBIOS_1010, 180 0x01, 181 "Symbios Logic 53c1010-33 (ultra3-wide scsi)", 182 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 183 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 184 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 185 SF_CHIP_GEBUG | 186 SF_BUS_ULTRA3 | SF_BUS_WIDE, 187 7, 62, 0, 62, 8192 188 }, 189 { PCI_PRODUCT_SYMBIOS_1010_2, 190 0x00, 191 "Symbios Logic 53c1010-66 (ultra3-wide scsi)", 192 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 193 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 194 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 195 SF_BUS_ULTRA3 | SF_BUS_WIDE, 196 7, 62, 0, 62, 8192 197 }, 198 { PCI_PRODUCT_SYMBIOS_1510D, 199 0x00, 200 "Symbios Logic 53c1510d (ultra2-wide scsi)", 201 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 202 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 203 SF_CHIP_LS | SF_CHIP_10REGS | 204 SF_BUS_ULTRA2 | SF_BUS_WIDE, 205 7, 31, 7, 62, 4096 206 }, 207 { 0, 208 0x00, 209 NULL, 210 0x00, 211 0, 0, 0, 0, 0 212 }, 213 }; 214 215 const struct siop_product_desc * 216 siop_lookup_product(id, rev) 217 u_int32_t id; 218 int rev; 219 { 220 const struct siop_product_desc *pp; 221 const struct siop_product_desc *rp = NULL; 222 223 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 224 return NULL; 225 226 for (pp = siop_products; pp->name != NULL; pp++) { 227 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 228 if (rp == NULL || pp->revision > rp->revision) 229 rp = pp; 230 } 231 return rp; 232 } 233 234 int 235 siop_pci_attach_common(pci_sc, siop_sc, pa, intr) 236 struct siop_pci_common_softc *pci_sc; 237 struct siop_common_softc *siop_sc; 238 struct pci_attach_args *pa; 239 int (*intr) __P((void*)); 240 241 { 242 pci_chipset_tag_t pc = pa->pa_pc; 243 pcitag_t tag = pa->pa_tag; 244 const char *intrstr; 245 pci_intr_handle_t intrhandle; 246 bus_space_tag_t iot, memt; 247 bus_space_handle_t ioh, memh; 248 pcireg_t memtype; 249 int memh_valid, ioh_valid; 250 bus_addr_t ioaddr, memaddr; 251 252 aprint_naive(": SCSI controller\n"); 253 254 pci_sc->sc_pp = 255 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 256 if (pci_sc->sc_pp == NULL) { 257 aprint_error("sym: broken match/attach!!\n"); 258 return 0; 259 } 260 /* copy interesting infos about the chip */ 261 siop_sc->features = pci_sc->sc_pp->features; 262 #ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 263 siop_sc->features |= SF_CHIP_LED0; 264 #endif 265 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 266 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 267 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 268 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 269 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 270 271 siop_sc->sc_reset = siop_pci_reset; 272 aprint_normal(": %s\n", pci_sc->sc_pp->name); 273 pci_sc->sc_pc = pc; 274 pci_sc->sc_tag = tag; 275 siop_sc->sc_dmat = pa->pa_dmat; 276 277 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 278 switch (memtype) { 279 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 280 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 281 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 282 &memt, &memh, &memaddr, NULL) == 0); 283 break; 284 default: 285 memh_valid = 0; 286 } 287 288 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 289 &iot, &ioh, &ioaddr, NULL) == 0); 290 291 if (memh_valid) { 292 siop_sc->sc_rt = memt; 293 siop_sc->sc_rh = memh; 294 siop_sc->sc_raddr = memaddr; 295 } else if (ioh_valid) { 296 siop_sc->sc_rt = iot; 297 siop_sc->sc_rh = ioh; 298 siop_sc->sc_raddr = ioaddr; 299 } else { 300 aprint_error("%s: unable to map device registers\n", 301 siop_sc->sc_dev.dv_xname); 302 return 0; 303 } 304 305 if (siop_sc->features & SF_CHIP_RAM) { 306 int bar; 307 switch (memtype) { 308 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 309 bar = 0x18; 310 break; 311 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 312 bar = 0x1c; 313 break; 314 } 315 if (pci_mapreg_map(pa, bar, memtype, 0, 316 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 317 &siop_sc->sc_scriptaddr, NULL) == 0) { 318 aprint_normal("%s: using on-board RAM\n", 319 siop_sc->sc_dev.dv_xname); 320 } else { 321 aprint_error("%s: can't map on-board RAM\n", 322 siop_sc->sc_dev.dv_xname); 323 siop_sc->features &= ~SF_CHIP_RAM; 324 } 325 } 326 327 if (pci_intr_map(pa, &intrhandle) != 0) { 328 aprint_error("%s: couldn't map interrupt\n", 329 siop_sc->sc_dev.dv_xname); 330 return 0; 331 } 332 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 333 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 334 intr, siop_sc); 335 if (pci_sc->sc_ih != NULL) { 336 aprint_normal("%s: interrupting at %s\n", 337 siop_sc->sc_dev.dv_xname, 338 intrstr ? intrstr : "unknown interrupt"); 339 } else { 340 aprint_error("%s: couldn't establish interrupt", 341 siop_sc->sc_dev.dv_xname); 342 if (intrstr != NULL) 343 aprint_normal(" at %s", intrstr); 344 aprint_normal("\n"); 345 return 0; 346 } 347 return 1; 348 } 349 350 void 351 siop_pci_reset(sc) 352 struct siop_common_softc *sc; 353 { 354 int dmode; 355 356 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 357 if (sc->features & SF_PCI_RL) 358 dmode |= DMODE_ERL; 359 if (sc->features & SF_PCI_RM) 360 dmode |= DMODE_ERMP; 361 if (sc->features & SF_PCI_BOF) 362 dmode |= DMODE_BOF; 363 if (sc->features & SF_PCI_CLS) 364 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 365 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 366 DCNTL_CLSE); 367 if (sc->features & SF_PCI_WRI) 368 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 369 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 370 CTEST3_WRIE); 371 if (sc->maxburst) { 372 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 373 SIOP_CTEST5); 374 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 375 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 376 ~CTEST4_BDIS); 377 dmode &= ~DMODE_BL_MASK; 378 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 379 ctest5 &= ~CTEST5_BBCK; 380 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 381 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 382 } else { 383 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 384 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 385 CTEST4_BDIS); 386 } 387 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 388 } 389