1 /* $NetBSD: siisata_pci.c,v 1.9 2010/11/13 13:52:08 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* 29 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: siisata_pci.c,v 1.9 2010/11/13 13:52:08 uebayasi Exp $"); 55 56 #include <sys/types.h> 57 #include <sys/malloc.h> 58 #include <sys/param.h> 59 #include <sys/kernel.h> 60 #include <sys/systm.h> 61 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 #include <dev/ic/siisatavar.h> 65 66 struct siisata_pci_softc { 67 struct siisata_softc si_sc; 68 pci_chipset_tag_t sc_pc; 69 pcitag_t sc_pcitag; 70 void * sc_ih; 71 }; 72 73 static int siisata_pci_match(device_t, cfdata_t, void *); 74 static void siisata_pci_attach(device_t, device_t, void *); 75 static int siisata_pci_detach(device_t, int); 76 static bool siisata_pci_resume(device_t, const pmf_qual_t *); 77 78 struct siisata_pci_board { 79 pci_vendor_id_t spb_vend; 80 pci_product_id_t spb_prod; 81 uint16_t spb_port; 82 uint16_t spb_chip; 83 }; 84 85 static const struct siisata_pci_board siisata_pci_boards[] = { 86 { 87 .spb_vend = PCI_VENDOR_CMDTECH, 88 .spb_prod = PCI_PRODUCT_CMDTECH_3124, 89 .spb_port = 4, 90 .spb_chip = 3124, 91 }, 92 { 93 .spb_vend = PCI_VENDOR_CMDTECH, 94 .spb_prod = PCI_PRODUCT_CMDTECH_3132, 95 .spb_port = 2, 96 .spb_chip = 3132, 97 }, 98 { 99 .spb_vend = PCI_VENDOR_CMDTECH, 100 .spb_prod = PCI_PRODUCT_CMDTECH_3531, 101 .spb_port = 1, 102 .spb_chip = 3531, 103 }, 104 }; 105 106 CFATTACH_DECL_NEW(siisata_pci, sizeof(struct siisata_pci_softc), 107 siisata_pci_match, siisata_pci_attach, siisata_pci_detach, NULL); 108 109 static const struct siisata_pci_board * 110 siisata_pci_lookup(const struct pci_attach_args * pa) 111 { 112 int i; 113 114 for (i = 0; i < __arraycount(siisata_pci_boards); i++) { 115 if (siisata_pci_boards[i].spb_vend != PCI_VENDOR(pa->pa_id)) 116 continue; 117 if (siisata_pci_boards[i].spb_prod == PCI_PRODUCT(pa->pa_id)) 118 return &siisata_pci_boards[i]; 119 } 120 121 return NULL; 122 } 123 124 static int 125 siisata_pci_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct pci_attach_args *pa = aux; 128 129 if (siisata_pci_lookup(pa) != NULL) 130 return 3; 131 132 return 0; 133 } 134 135 static void 136 siisata_pci_attach(device_t parent, device_t self, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 struct siisata_pci_softc *psc = device_private(self); 140 struct siisata_softc *sc = &psc->si_sc; 141 char devinfo[256]; 142 const char *intrstr; 143 pcireg_t csr, memtype; 144 const struct siisata_pci_board *spbp; 145 pci_intr_handle_t intrhandle; 146 bus_space_tag_t memt; 147 bus_space_handle_t memh; 148 uint32_t gcreg; 149 int memh_valid; 150 bus_size_t grsize, prsize; 151 152 sc->sc_atac.atac_dev = self; 153 154 psc->sc_pc = pa->pa_pc; 155 psc->sc_pcitag = pa->pa_tag; 156 157 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 158 aprint_naive(": SATA-II HBA\n"); 159 aprint_normal(": %s\n", devinfo); 160 161 /* map BAR 0, global registers */ 162 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0); 163 switch (memtype) { 164 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 165 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 166 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0, 167 memtype, 0, &memt, &memh, NULL, &grsize) == 0); 168 break; 169 default: 170 memh_valid = 0; 171 } 172 if (memh_valid) { 173 sc->sc_grt = memt; 174 sc->sc_grh = memh; 175 sc->sc_grs = grsize; 176 } else { 177 aprint_error_dev(self, "couldn't map global registers\n"); 178 return; 179 } 180 181 /* map BAR 1, port registers */ 182 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1); 183 switch (memtype) { 184 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 185 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 186 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1, 187 memtype, 0, &memt, &memh, NULL, &prsize) == 0); 188 break; 189 default: 190 memh_valid = 0; 191 } 192 if (memh_valid) { 193 sc->sc_prt = memt; 194 sc->sc_prh = memh; 195 sc->sc_prs = prsize; 196 } else { 197 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 198 aprint_error_dev(self, "couldn't map port registers\n"); 199 return; 200 } 201 202 if (pci_dma64_available(pa)) 203 sc->sc_dmat = pa->pa_dmat64; 204 else 205 sc->sc_dmat = pa->pa_dmat; 206 207 /* map interrupt */ 208 if (pci_intr_map(pa, &intrhandle) != 0) { 209 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 210 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 211 aprint_error_dev(self, "couldn't map interrupt\n"); 212 return; 213 } 214 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 215 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 216 IPL_BIO, siisata_intr, sc); 217 if (psc->sc_ih == NULL) { 218 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 219 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 220 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 221 intrstr); 222 return; 223 } 224 aprint_normal_dev(self, "interrupting at %s\n", 225 intrstr ? intrstr : "unknown interrupt"); 226 227 /* fill in number of ports on this device */ 228 spbp = siisata_pci_lookup(pa); 229 KASSERT(spbp != NULL); 230 sc->sc_atac.atac_nchannels = spbp->spb_port; 231 232 /* set the necessary bits in case the firmware didn't */ 233 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 234 csr |= PCI_COMMAND_MASTER_ENABLE; 235 csr |= PCI_COMMAND_MEM_ENABLE; 236 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 237 238 gcreg = GRREAD(sc, GR_GC); 239 240 aprint_verbose_dev(self, "SiI%d, %sGb/s\n", 241 spbp->spb_chip, (gcreg & GR_GC_3GBPS) ? "3.0" : "1.5" ); 242 if (spbp->spb_chip == 3124) { 243 short width; 244 short speed; 245 char pcix = 1; 246 247 width = (gcreg & GR_GC_REQ64) ? 64 : 32; 248 249 switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) { 250 case 0: 251 speed = (gcreg & GR_GC_M66EN) ? 66 : 33; 252 pcix = 0; 253 break; 254 case GR_GC_TRDY: 255 speed = 66; 256 break; 257 case GR_GC_STOP: 258 speed = 100; 259 break; 260 case GR_GC_STOP | GR_GC_TRDY: 261 speed = 133; 262 break; 263 default: 264 speed = -1; 265 break; 266 } 267 aprint_verbose_dev(self, "%hd-bit %hdMHz PCI%s\n", 268 width, speed, pcix ? "-X" : ""); 269 } 270 271 siisata_attach(sc); 272 273 if (!pmf_device_register(self, NULL, siisata_pci_resume)) 274 aprint_error_dev(self, "couldn't establish power handler\n"); 275 } 276 277 static int 278 siisata_pci_detach(device_t dv, int flags) 279 { 280 struct siisata_pci_softc *psc = device_private(dv); 281 struct siisata_softc *sc = &psc->si_sc; 282 int rv; 283 284 rv = siisata_detach(sc, flags); 285 if (rv) 286 return rv; 287 288 if (psc->sc_ih != NULL) { 289 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 290 } 291 292 bus_space_unmap(sc->sc_prt, sc->sc_prh, sc->sc_prs); 293 bus_space_unmap(sc->sc_grt, sc->sc_grh, sc->sc_grs); 294 295 return 0; 296 } 297 298 static bool 299 siisata_pci_resume(device_t dv, const pmf_qual_t *qual) 300 { 301 struct siisata_pci_softc *psc = device_private(dv); 302 struct siisata_softc *sc = &psc->si_sc; 303 int s; 304 305 s = splbio(); 306 siisata_resume(sc); 307 splx(s); 308 309 return true; 310 } 311