1 /* $NetBSD: siisata_pci.c,v 1.13 2014/03/29 19:28:25 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* 29 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: siisata_pci.c,v 1.13 2014/03/29 19:28:25 christos Exp $"); 55 56 #include <sys/types.h> 57 #include <sys/malloc.h> 58 #include <sys/param.h> 59 #include <sys/kernel.h> 60 #include <sys/systm.h> 61 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 #include <dev/ic/siisatavar.h> 65 66 struct siisata_pci_softc { 67 struct siisata_softc si_sc; 68 pci_chipset_tag_t sc_pc; 69 pcitag_t sc_pcitag; 70 void * sc_ih; 71 }; 72 73 static int siisata_pci_match(device_t, cfdata_t, void *); 74 static void siisata_pci_attach(device_t, device_t, void *); 75 static int siisata_pci_detach(device_t, int); 76 static bool siisata_pci_resume(device_t, const pmf_qual_t *); 77 78 struct siisata_pci_board { 79 pci_vendor_id_t spb_vend; 80 pci_product_id_t spb_prod; 81 uint16_t spb_port; 82 uint16_t spb_chip; 83 }; 84 85 static const struct siisata_pci_board siisata_pci_boards[] = { 86 { 87 .spb_vend = PCI_VENDOR_CMDTECH, 88 .spb_prod = PCI_PRODUCT_CMDTECH_3124, 89 .spb_port = 4, 90 .spb_chip = 3124, 91 }, 92 { 93 .spb_vend = PCI_VENDOR_CMDTECH, 94 .spb_prod = PCI_PRODUCT_CMDTECH_3132, 95 .spb_port = 2, 96 .spb_chip = 3132, 97 }, 98 { 99 .spb_vend = PCI_VENDOR_CMDTECH, 100 .spb_prod = PCI_PRODUCT_CMDTECH_3531, 101 .spb_port = 1, 102 .spb_chip = 3531, 103 }, 104 }; 105 106 CFATTACH_DECL_NEW(siisata_pci, sizeof(struct siisata_pci_softc), 107 siisata_pci_match, siisata_pci_attach, siisata_pci_detach, NULL); 108 109 static const struct siisata_pci_board * 110 siisata_pci_lookup(const struct pci_attach_args * pa) 111 { 112 int i; 113 114 for (i = 0; i < __arraycount(siisata_pci_boards); i++) { 115 if (siisata_pci_boards[i].spb_vend != PCI_VENDOR(pa->pa_id)) 116 continue; 117 if (siisata_pci_boards[i].spb_prod == PCI_PRODUCT(pa->pa_id)) 118 return &siisata_pci_boards[i]; 119 } 120 121 return NULL; 122 } 123 124 static int 125 siisata_pci_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct pci_attach_args *pa = aux; 128 129 if (siisata_pci_lookup(pa) != NULL) 130 return 3; 131 132 return 0; 133 } 134 135 static void 136 siisata_pci_attach(device_t parent, device_t self, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 struct siisata_pci_softc *psc = device_private(self); 140 struct siisata_softc *sc = &psc->si_sc; 141 const char *intrstr; 142 pcireg_t csr, memtype; 143 const struct siisata_pci_board *spbp; 144 pci_intr_handle_t intrhandle; 145 bus_space_tag_t memt; 146 bus_space_handle_t memh; 147 uint32_t gcreg; 148 int memh_valid; 149 bus_size_t grsize, prsize; 150 char intrbuf[PCI_INTRSTR_LEN]; 151 152 sc->sc_atac.atac_dev = self; 153 154 psc->sc_pc = pa->pa_pc; 155 psc->sc_pcitag = pa->pa_tag; 156 157 pci_aprint_devinfo(pa, "SATA-II HBA"); 158 159 /* map BAR 0, global registers */ 160 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0); 161 switch (memtype) { 162 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 163 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 164 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0, 165 memtype, 0, &memt, &memh, NULL, &grsize) == 0); 166 break; 167 default: 168 memh_valid = 0; 169 } 170 if (memh_valid) { 171 sc->sc_grt = memt; 172 sc->sc_grh = memh; 173 sc->sc_grs = grsize; 174 } else { 175 aprint_error_dev(self, "couldn't map global registers\n"); 176 return; 177 } 178 179 /* map BAR 1, port registers */ 180 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1); 181 switch (memtype) { 182 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 183 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 184 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1, 185 memtype, 0, &memt, &memh, NULL, &prsize) == 0); 186 break; 187 default: 188 memh_valid = 0; 189 } 190 if (memh_valid) { 191 sc->sc_prt = memt; 192 sc->sc_prh = memh; 193 sc->sc_prs = prsize; 194 } else { 195 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 196 aprint_error_dev(self, "couldn't map port registers\n"); 197 return; 198 } 199 200 if (pci_dma64_available(pa)) 201 sc->sc_dmat = pa->pa_dmat64; 202 else 203 sc->sc_dmat = pa->pa_dmat; 204 205 /* map interrupt */ 206 if (pci_intr_map(pa, &intrhandle) != 0) { 207 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 208 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 209 aprint_error_dev(self, "couldn't map interrupt\n"); 210 return; 211 } 212 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 213 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, 214 IPL_BIO, siisata_intr, sc); 215 if (psc->sc_ih == NULL) { 216 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 217 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 218 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 219 intrstr); 220 return; 221 } 222 aprint_normal_dev(self, "interrupting at %s\n", 223 intrstr ? intrstr : "unknown interrupt"); 224 225 /* fill in number of ports on this device */ 226 spbp = siisata_pci_lookup(pa); 227 KASSERT(spbp != NULL); 228 sc->sc_atac.atac_nchannels = spbp->spb_port; 229 230 /* set the necessary bits in case the firmware didn't */ 231 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 csr |= PCI_COMMAND_MASTER_ENABLE; 233 csr |= PCI_COMMAND_MEM_ENABLE; 234 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 235 236 gcreg = GRREAD(sc, GR_GC); 237 238 aprint_verbose_dev(self, "SiI%d, %sGb/s\n", 239 spbp->spb_chip, (gcreg & GR_GC_3GBPS) ? "3.0" : "1.5" ); 240 if (spbp->spb_chip == 3124) { 241 short width; 242 short speed; 243 char pcix = 1; 244 245 width = (gcreg & GR_GC_REQ64) ? 64 : 32; 246 247 switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) { 248 case 0: 249 speed = (gcreg & GR_GC_M66EN) ? 66 : 33; 250 pcix = 0; 251 break; 252 case GR_GC_TRDY: 253 speed = 66; 254 break; 255 case GR_GC_STOP: 256 speed = 100; 257 break; 258 case GR_GC_STOP | GR_GC_TRDY: 259 speed = 133; 260 break; 261 default: 262 speed = -1; 263 break; 264 } 265 aprint_verbose_dev(self, "%hd-bit %hdMHz PCI%s\n", 266 width, speed, pcix ? "-X" : ""); 267 } 268 269 siisata_attach(sc); 270 271 if (!pmf_device_register(self, NULL, siisata_pci_resume)) 272 aprint_error_dev(self, "couldn't establish power handler\n"); 273 } 274 275 static int 276 siisata_pci_detach(device_t dv, int flags) 277 { 278 struct siisata_pci_softc *psc = device_private(dv); 279 struct siisata_softc *sc = &psc->si_sc; 280 int rv; 281 282 rv = siisata_detach(sc, flags); 283 if (rv) 284 return rv; 285 286 if (psc->sc_ih != NULL) { 287 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 288 } 289 290 bus_space_unmap(sc->sc_prt, sc->sc_prh, sc->sc_prs); 291 bus_space_unmap(sc->sc_grt, sc->sc_grh, sc->sc_grs); 292 293 return 0; 294 } 295 296 static bool 297 siisata_pci_resume(device_t dv, const pmf_qual_t *qual) 298 { 299 struct siisata_pci_softc *psc = device_private(dv); 300 struct siisata_softc *sc = &psc->si_sc; 301 int s; 302 303 s = splbio(); 304 siisata_resume(sc); 305 splx(s); 306 307 return true; 308 } 309