xref: /netbsd-src/sys/dev/pci/siisata_pci.c (revision 181254a7b1bdde6873432bffef2d2decc4b5c22f)
1 /* $NetBSD: siisata_pci.c,v 1.20 2018/10/25 21:03:19 jdolecek Exp $ */
2 
3 /*
4  * Copyright (c) 2006 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  */
27 
28 /*
29  * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch.
30  * All rights reserved.
31  *
32  * Redistribution and use in source and binary forms, with or without
33  * modification, are permitted provided that the following conditions
34  * are met:
35  * 1. Redistributions of source code must retain the above copyright
36  *    notice, this list of conditions and the following disclaimer.
37  * 2. Redistributions in binary form must reproduce the above copyright
38  *    notice, this list of conditions and the following disclaimer in the
39  *    documentation and/or other materials provided with the distribution.
40  *
41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
42  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
45  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
46  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51  */
52 
53 #include <sys/cdefs.h>
54 __KERNEL_RCSID(0, "$NetBSD: siisata_pci.c,v 1.20 2018/10/25 21:03:19 jdolecek Exp $");
55 
56 #include <sys/types.h>
57 #include <sys/malloc.h>
58 #include <sys/param.h>
59 #include <sys/kernel.h>
60 #include <sys/systm.h>
61 
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pcidevs.h>
64 #include <dev/ic/siisatavar.h>
65 
66 struct siisata_pci_softc {
67 	struct siisata_softc si_sc;
68 	pci_chipset_tag_t sc_pc;
69 	pcitag_t sc_pcitag;
70 	pci_intr_handle_t *sc_pihp;
71 	void *sc_ih;
72 };
73 
74 static int siisata_pci_match(device_t, cfdata_t, void *);
75 static void siisata_pci_attach(device_t, device_t, void *);
76 static int siisata_pci_detach(device_t, int);
77 static void siisata_pci_childdetached(device_t, device_t);
78 static bool siisata_pci_resume(device_t, const pmf_qual_t *);
79 
80 struct siisata_pci_board {
81 	pci_vendor_id_t		spb_vend;
82 	pci_product_id_t	spb_prod;
83 	uint16_t		spb_port;
84 	uint16_t		spb_chip;
85 };
86 
87 static const struct siisata_pci_board siisata_pci_boards[] = {
88 	{
89 		.spb_vend = PCI_VENDOR_CMDTECH,
90 		.spb_prod = PCI_PRODUCT_CMDTECH_3124,
91 		.spb_port = 4,
92 		.spb_chip = 3124,
93 	},
94 	{
95 		.spb_vend = PCI_VENDOR_CMDTECH,
96 		.spb_prod = PCI_PRODUCT_CMDTECH_3132,
97 		.spb_port = 2,
98 		.spb_chip = 3132,
99 	},
100 	{
101 		.spb_vend = PCI_VENDOR_CMDTECH,
102 		.spb_prod = PCI_PRODUCT_CMDTECH_AAR_1220SA,
103 		.spb_port = 2,
104 		.spb_chip = 3132,
105 	},
106 	{
107 		.spb_vend = PCI_VENDOR_CMDTECH,
108 		.spb_prod = PCI_PRODUCT_CMDTECH_3531,
109 		.spb_port = 1,
110 		.spb_chip = 3531,
111 	},
112 };
113 
114 CFATTACH_DECL3_NEW(siisata_pci, sizeof(struct siisata_pci_softc),
115     siisata_pci_match, siisata_pci_attach, siisata_pci_detach, NULL,
116     NULL, siisata_pci_childdetached, DVF_DETACH_SHUTDOWN);
117 
118 static const struct siisata_pci_board *
119 siisata_pci_lookup(const struct pci_attach_args * pa)
120 {
121 	int i;
122 
123 	for (i = 0; i < __arraycount(siisata_pci_boards); i++) {
124 		if (siisata_pci_boards[i].spb_vend != PCI_VENDOR(pa->pa_id))
125 			continue;
126 		if (siisata_pci_boards[i].spb_prod == PCI_PRODUCT(pa->pa_id))
127 			return &siisata_pci_boards[i];
128 	}
129 
130 	return NULL;
131 }
132 
133 static int
134 siisata_pci_match(device_t parent, cfdata_t match, void *aux)
135 {
136 	struct pci_attach_args *pa = aux;
137 
138 	if (siisata_pci_lookup(pa) != NULL)
139 		return 3;
140 
141 	return 0;
142 }
143 
144 static void
145 siisata_pci_attach(device_t parent, device_t self, void *aux)
146 {
147 	struct pci_attach_args *pa = aux;
148 	struct siisata_pci_softc *psc = device_private(self);
149 	struct siisata_softc *sc = &psc->si_sc;
150 	const char *intrstr;
151 	pcireg_t csr, memtype;
152 	const struct siisata_pci_board *spbp;
153 	bus_space_tag_t memt;
154 	bus_space_handle_t memh;
155 	uint32_t gcreg;
156 	int memh_valid;
157 	bus_size_t grsize, prsize;
158 	char intrbuf[PCI_INTRSTR_LEN];
159 
160 	sc->sc_atac.atac_dev = self;
161 
162 	psc->sc_pc = pa->pa_pc;
163 	psc->sc_pcitag = pa->pa_tag;
164 
165 	pci_aprint_devinfo(pa, "SATA-II HBA");
166 
167 	/* map BAR 0, global registers */
168 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0);
169 	switch (memtype) {
170 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
171 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
172 		memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0,
173 			memtype, 0, &memt, &memh, NULL, &grsize) == 0);
174 		break;
175 	default:
176 		memh_valid = 0;
177 	}
178 	if (memh_valid) {
179 		sc->sc_grt = memt;
180 		sc->sc_grh = memh;
181 		sc->sc_grs = grsize;
182 	} else {
183 		aprint_error_dev(self, "couldn't map global registers\n");
184 		return;
185 	}
186 
187 	/* map BAR 1, port registers */
188 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1);
189 	switch (memtype) {
190 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
191 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
192 		memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1,
193 			memtype, 0, &memt, &memh, NULL, &prsize) == 0);
194 		break;
195 	default:
196 		memh_valid = 0;
197 	}
198 	if (memh_valid) {
199 		sc->sc_prt = memt;
200 		sc->sc_prh = memh;
201 		sc->sc_prs = prsize;
202 	} else {
203 		bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
204 		aprint_error_dev(self, "couldn't map port registers\n");
205 		return;
206 	}
207 
208 	if (pci_dma64_available(pa))
209 		sc->sc_dmat = pa->pa_dmat64;
210 	else
211 		sc->sc_dmat = pa->pa_dmat;
212 
213 	/* map interrupt */
214 	if (pci_intr_alloc(pa, &psc->sc_pihp, NULL, 0) != 0) {
215 		bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
216 		bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize);
217 		aprint_error_dev(self, "couldn't map interrupt\n");
218 		return;
219 	}
220 	intrstr = pci_intr_string(pa->pa_pc, psc->sc_pihp[0], intrbuf,
221 	    sizeof(intrbuf));
222 	psc->sc_ih = pci_intr_establish_xname(pa->pa_pc, psc->sc_pihp[0],
223 	    IPL_BIO, siisata_intr, sc, device_xname(self));
224 	if (psc->sc_ih == NULL) {
225 		pci_intr_release(psc->sc_pc, psc->sc_pihp, 1);
226 		psc->sc_pihp = NULL;
227 
228 		bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize);
229 		bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize);
230 		aprint_error_dev(self, "couldn't establish interrupt at %s\n",
231 			intrstr);
232 		return;
233 	}
234 	aprint_normal_dev(self, "interrupting at %s\n",
235 		intrstr ? intrstr : "unknown interrupt");
236 
237 	/* fill in number of ports on this device */
238 	spbp = siisata_pci_lookup(pa);
239 	KASSERT(spbp != NULL);
240 	sc->sc_atac.atac_nchannels = spbp->spb_port;
241 
242 	/* set the necessary bits in case the firmware didn't */
243 	csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
244 	csr |= PCI_COMMAND_MASTER_ENABLE;
245 	csr |= PCI_COMMAND_MEM_ENABLE;
246 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
247 
248 	gcreg = GRREAD(sc, GR_GC);
249 
250 	aprint_verbose_dev(self, "SiI%d, %sGb/s\n",
251 		spbp->spb_chip, (gcreg & GR_GC_3GBPS) ? "3.0" : "1.5" );
252 	if (spbp->spb_chip == 3124) {
253 		short width;
254 		short speed;
255 		char pcix = 1;
256 
257 		width = (gcreg & GR_GC_REQ64) ? 64 : 32;
258 
259 		switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) {
260 		case 0:
261 			speed = (gcreg & GR_GC_M66EN) ? 66 : 33;
262 			pcix = 0;
263 			break;
264 		case GR_GC_TRDY:
265 			speed = 66;
266 			break;
267 		case GR_GC_STOP:
268 			speed = 100;
269 			break;
270 		case GR_GC_STOP | GR_GC_TRDY:
271 			speed = 133;
272 			break;
273 		default:
274 			speed = -1;
275 			break;
276 		}
277 		aprint_verbose_dev(self, "%hd-bit %hdMHz PCI%s\n",
278 			width, speed, pcix ? "-X" : "");
279 	}
280 
281 	siisata_attach(sc);
282 
283 	if (!pmf_device_register(self, NULL, siisata_pci_resume))
284 		aprint_error_dev(self, "couldn't establish power handler\n");
285 }
286 
287 static int
288 siisata_pci_detach(device_t dv, int flags)
289 {
290 	struct siisata_pci_softc *psc = device_private(dv);
291 	struct siisata_softc *sc = &psc->si_sc;
292 	int rv;
293 
294 	rv = siisata_detach(sc, flags);
295 	if (rv)
296 		return rv;
297 
298 	if (psc->sc_ih != NULL) {
299 		pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
300 		psc->sc_ih = NULL;
301 	}
302 
303 	if (psc->sc_pihp != NULL) {
304 		pci_intr_release(psc->sc_pc, psc->sc_pihp, 1);
305 		psc->sc_pihp = NULL;
306 	}
307 
308 	bus_space_unmap(sc->sc_prt, sc->sc_prh, sc->sc_prs);
309 	bus_space_unmap(sc->sc_grt, sc->sc_grh, sc->sc_grs);
310 
311 	return 0;
312 }
313 
314 static void
315 siisata_pci_childdetached(device_t dv, device_t child)
316 {
317 	struct siisata_pci_softc *psc = device_private(dv);
318 	struct siisata_softc *sc = &psc->si_sc;
319 
320 	siisata_childdetached(sc, child);
321 }
322 
323 static bool
324 siisata_pci_resume(device_t dv, const pmf_qual_t *qual)
325 {
326 	struct siisata_pci_softc *psc = device_private(dv);
327 	struct siisata_softc *sc = &psc->si_sc;
328 	int s;
329 
330 	s = splbio();
331 	siisata_resume(sc);
332 	splx(s);
333 
334 	return true;
335 }
336