1 /* $NetBSD: sdhc_pci.c,v 1.4 2011/02/02 04:18:14 jakllsch Exp $ */ 2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.4 2011/02/02 04:18:14 jakllsch Exp $"); 22 23 #include <sys/param.h> 24 #include <sys/device.h> 25 #include <sys/systm.h> 26 #include <sys/malloc.h> 27 #include <sys/pmf.h> 28 29 #include <dev/pci/pcivar.h> 30 #include <dev/pci/pcidevs.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcvar.h> 35 36 /* PCI base address registers */ 37 #define SDHC_PCI_BAR_START PCI_MAPREG_START 38 #define SDHC_PCI_BAR_END PCI_MAPREG_END 39 40 /* PCI interface classes */ 41 #define SDHC_PCI_INTERFACE_NO_DMA 0x00 42 #define SDHC_PCI_INTERFACE_DMA 0x01 43 #define SDHC_PCI_INTERFACE_VENDOR 0x02 44 45 /* 46 * 8-bit PCI configuration register that tells us how many slots there 47 * are and which BAR entry corresponds to the first slot. 48 */ 49 #define SDHC_PCI_CONF_SLOT_INFO 0x40 50 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1) 51 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7) 52 53 struct sdhc_pci_softc { 54 struct sdhc_softc sc; 55 void *sc_ih; 56 }; 57 58 static int sdhc_pci_match(device_t, cfdata_t, void *); 59 static void sdhc_pci_attach(device_t, device_t, void *); 60 61 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc), 62 sdhc_pci_match, sdhc_pci_attach, NULL, NULL); 63 64 #ifdef SDHC_DEBUG 65 #define DPRINTF(s) printf s 66 #else 67 #define DPRINTF(s) /**/ 68 #endif 69 70 static const struct sdhc_pci_quirk { 71 pci_vendor_id_t vendor; 72 pci_product_id_t product; 73 pci_vendor_id_t subvendor; 74 pci_product_id_t subproduct; 75 u_int function; 76 77 uint32_t flags; 78 #define SDHC_PCI_QUIRK_FORCE_DMA (1U << 0) 79 #define SDHC_PCI_QUIRK_TI_HACK (1U << 1) 80 #define SDHC_PCI_QUIRK_NO_PWR0 (1U << 2) 81 } sdhc_pci_quirk_table[] = { 82 { 83 PCI_VENDOR_TI, 84 PCI_PRODUCT_TI_PCI72111SD, 85 0xffff, 86 0xffff, 87 4, 88 SDHC_PCI_QUIRK_TI_HACK 89 }, 90 91 { 92 PCI_VENDOR_TI, 93 PCI_PRODUCT_TI_PCIXX12SD, 94 0xffff, 95 0xffff, 96 3, 97 SDHC_PCI_QUIRK_TI_HACK 98 }, 99 100 { 101 PCI_VENDOR_ENE, 102 PCI_PRODUCT_ENE_CB712, 103 0xffff, 104 0xffff, 105 0, 106 SDHC_PCI_QUIRK_NO_PWR0 107 }, 108 }; 109 110 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *); 111 112 static uint32_t 113 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa) 114 { 115 const struct sdhc_pci_quirk *q; 116 pcireg_t id; 117 pci_vendor_id_t vendor; 118 pci_product_id_t product; 119 int i; 120 121 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) { 122 q = &sdhc_pci_quirk_table[i]; 123 124 if ((PCI_VENDOR(pa->pa_id) == q->vendor) 125 && (PCI_PRODUCT(pa->pa_id) == q->product)) { 126 if ((q->function != ~0) 127 && (pa->pa_function != q->function)) 128 continue; 129 130 if ((q->subvendor == 0xffff) 131 && (q->subproduct == 0xffff)) 132 return q->flags; 133 134 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 135 PCI_SUBSYS_ID_REG); 136 vendor = PCI_VENDOR(id); 137 product = PCI_PRODUCT(id); 138 139 if ((q->subvendor != 0xffff) 140 && (q->subproduct != 0xffff)) { 141 if ((vendor == q->subvendor) 142 && (product == q->subproduct)) 143 return q->flags; 144 } else if (q->subvendor != 0xffff) { 145 if (product == q->subproduct) 146 return q->flags; 147 } else { 148 if (vendor == q->subvendor) 149 return q->flags; 150 } 151 } 152 } 153 154 return 0; 155 } 156 157 static int 158 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 162 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM && 163 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC) 164 return 1; 165 166 return 0; 167 } 168 169 static void 170 sdhc_pci_attach(device_t parent, device_t self, void *aux) 171 { 172 struct sdhc_pci_softc *sc = device_private(self); 173 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 174 pci_chipset_tag_t pc = pa->pa_pc; 175 pcitag_t tag = pa->pa_tag; 176 pci_intr_handle_t ih; 177 pcireg_t csr; 178 pcireg_t slotinfo; 179 char devinfo[256]; 180 char const *intrstr; 181 int nslots; 182 int reg; 183 int cnt; 184 bus_space_tag_t iot; 185 bus_space_handle_t ioh; 186 bus_size_t size; 187 uint32_t flags; 188 189 sc->sc.sc_dev = self; 190 sc->sc.sc_dmat = pa->pa_dmat; 191 sc->sc.sc_host = NULL; 192 193 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 194 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 195 PCI_REVISION(pa->pa_class)); 196 aprint_naive("\n"); 197 198 /* Some controllers needs special treatment. */ 199 flags = sdhc_pci_lookup_quirk_flags(pa); 200 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK)) 201 sdhc_pci_quirk_ti_hack(pa); 202 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA)) 203 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA); 204 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0)) 205 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0); 206 207 /* 208 * Map and attach all hosts supported by the host controller. 209 */ 210 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO); 211 nslots = SDHC_PCI_NUM_SLOTS(slotinfo); 212 213 /* Allocate an array big enough to hold all the possible hosts */ 214 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots, 215 M_DEVBUF, M_NOWAIT | M_ZERO); 216 if (sc->sc.sc_host == NULL) { 217 aprint_error_dev(self, "couldn't alloc memory\n"); 218 goto err; 219 } 220 221 /* Enable the device. */ 222 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 223 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 224 csr | PCI_COMMAND_MASTER_ENABLE); 225 226 /* Map and establish the interrupt. */ 227 if (pci_intr_map(pa, &ih)) { 228 aprint_error_dev(self, "couldn't map interrupt\n"); 229 goto err; 230 } 231 232 intrstr = pci_intr_string(pc, ih); 233 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SDMMC, sdhc_intr, &sc->sc); 234 if (sc->sc_ih == NULL) { 235 aprint_error_dev(self, "couldn't establish interrupt\n"); 236 goto err; 237 } 238 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 239 240 /* Enable use of DMA if supported by the interface. */ 241 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA)) 242 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA); 243 244 /* XXX: handle 64-bit BARs */ 245 cnt = 0; 246 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 247 sizeof(uint32_t); 248 reg < SDHC_PCI_BAR_END && nslots > 0; 249 reg += sizeof(uint32_t), nslots--) { 250 if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0, 251 &iot, &ioh, NULL, &size)) { 252 continue; 253 } 254 255 cnt++; 256 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) { 257 /* XXX: sc->sc_host leak */ 258 aprint_error_dev(self, 259 "couldn't initialize host (0x%x)\n", reg); 260 } 261 } 262 if (cnt == 0) { 263 aprint_error_dev(self, "couldn't map register\n"); 264 goto err; 265 } 266 267 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume, 268 sdhc_shutdown)) { 269 aprint_error_dev(self, "couldn't establish powerhook\n"); 270 } 271 272 return; 273 274 err: 275 if (sc->sc.sc_host != NULL) 276 free(sc->sc.sc_host, M_DEVBUF); 277 } 278 279 /* TI specific register */ 280 #define SDHC_PCI_GENERAL_CTL 0x4c 281 #define MMC_SD_DIS 0x02 282 283 static void 284 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa) 285 { 286 pci_chipset_tag_t pc = pa->pa_pc; 287 pcitag_t tag; 288 pcireg_t id, reg; 289 290 /* Look at func - 1 for the flash device */ 291 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1); 292 id = pci_conf_read(pc, tag, PCI_ID_REG); 293 if (PCI_VENDOR(id) != PCI_VENDOR_TI) { 294 return; 295 } 296 switch (PCI_PRODUCT(id)) { 297 case PCI_PRODUCT_TI_PCI72111FM: 298 case PCI_PRODUCT_TI_PCIXX12FM: 299 break; 300 default: 301 return; 302 } 303 304 /* 305 * Disable MMC/SD on the flash media controller so the 306 * SD host takes over. 307 */ 308 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL); 309 reg |= MMC_SD_DIS; 310 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg); 311 } 312