1 /* $NetBSD: rdcide.c,v 1.2 2011/04/04 22:13:58 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rdcide.c,v 1.2 2011/04/04 22:13:58 dyoung Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/rdcide_reg.h> 38 39 static void rdcide_chip_map(struct pciide_softc *, 40 const struct pci_attach_args *); 41 static void rdcide_setup_channel(struct ata_channel *); 42 43 static bool rdcide_resume(device_t, const pmf_qual_t *); 44 static bool rdcide_suspend(device_t, const pmf_qual_t *); 45 static int rdcide_match(device_t, cfdata_t, void *); 46 static void rdcide_attach(device_t, device_t, void *); 47 48 static const struct pciide_product_desc pciide_intel_products[] = { 49 { PCI_PRODUCT_RDC_IDE, 50 0, 51 "RDC IDE controller", 52 rdcide_chip_map, 53 }, 54 }; 55 56 CFATTACH_DECL_NEW(rdcide, sizeof(struct pciide_softc), 57 rdcide_match, rdcide_attach, NULL, NULL); 58 59 static int 60 rdcide_match(device_t parent, cfdata_t match, void *aux) 61 { 62 struct pci_attach_args *pa = aux; 63 64 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC) { 65 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 66 return (2); 67 } 68 return (0); 69 } 70 71 static void 72 rdcide_attach(device_t parent, device_t self, void *aux) 73 { 74 struct pci_attach_args *pa = aux; 75 struct pciide_softc *sc = device_private(self); 76 77 sc->sc_wdcdev.sc_atac.atac_dev = self; 78 79 pciide_common_attach(sc, pa, 80 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 81 82 if (!pmf_device_register(self, rdcide_suspend, rdcide_resume)) 83 aprint_error_dev(self, "couldn't establish power handler\n"); 84 } 85 86 static bool 87 rdcide_resume(device_t dv, const pmf_qual_t *qual) 88 { 89 struct pciide_softc *sc = device_private(dv); 90 91 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, 92 sc->sc_pm_reg[0]); 93 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, 94 sc->sc_pm_reg[1]); 95 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, 96 sc->sc_pm_reg[2]); 97 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, 98 sc->sc_pm_reg[3]); 99 100 return true; 101 } 102 103 static bool 104 rdcide_suspend(device_t dv, const pmf_qual_t *qual) 105 { 106 struct pciide_softc *sc = device_private(dv); 107 108 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 109 RDCIDE_PATR); 110 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 111 RDCIDE_PSD1ATR); 112 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, 113 RDCIDE_UDCCR); 114 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, 115 RDCIDE_IIOCR); 116 117 return true; 118 } 119 120 static void 121 rdcide_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 122 { 123 struct pciide_channel *cp; 124 int channel; 125 u_int32_t patr; 126 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 127 128 if (pciide_chipen(sc, pa) == 0) 129 return; 130 131 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 132 "bus-master DMA support present"); 133 pciide_mapreg_dma(sc, pa); 134 aprint_verbose("\n"); 135 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 136 if (sc->sc_dma_ok) { 137 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 138 sc->sc_wdcdev.irqack = pciide_irqack; 139 sc->sc_wdcdev.dma_init = pciide_dma_init; 140 } 141 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 142 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 143 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 144 sc->sc_wdcdev.sc_atac.atac_set_modes = rdcide_setup_channel; 145 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 146 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 147 148 ATADEBUG_PRINT(("rdcide_setup_chip: old PATR=0x%x", 149 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)), 150 DEBUG_PROBE); 151 ATADEBUG_PRINT((", PSD1ATR=0x%x", 152 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)), 153 DEBUG_PROBE); 154 ATADEBUG_PRINT((", UDCCR 0x%x", 155 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)), 156 DEBUG_PROBE); 157 ATADEBUG_PRINT((", IIOCR 0x%x", 158 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 159 DEBUG_PROBE); 160 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 161 162 wdc_allocate_regs(&sc->sc_wdcdev); 163 164 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 165 channel++) { 166 cp = &sc->pciide_channels[channel]; 167 if (pciide_chansetup(sc, channel, interface) == 0) 168 continue; 169 patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 170 if ((patr & RDCIDE_PATR_EN(channel)) == 0) { 171 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 172 "%s channel ignored (disabled)\n", cp->name); 173 cp->ata_channel.ch_flags |= ATACH_DISABLED; 174 continue; 175 } 176 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 177 } 178 ATADEBUG_PRINT(("rdcide_setup_chip: PATR=0x%x", 179 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)), 180 DEBUG_PROBE); 181 ATADEBUG_PRINT((", PSD1ATR=0x%x", 182 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)), 183 DEBUG_PROBE); 184 ATADEBUG_PRINT((", UDCCR 0x%x", 185 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)), 186 DEBUG_PROBE); 187 ATADEBUG_PRINT((", IIOCR 0x%x", 188 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 189 DEBUG_PROBE); 190 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 191 192 } 193 194 static void 195 rdcide_setup_channel(struct ata_channel *chp) 196 { 197 u_int8_t drive; 198 u_int32_t patr, psd1atr, udccr, iiocr; 199 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 200 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 201 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 202 203 patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 204 psd1atr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR); 205 udccr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR); 206 iiocr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR); 207 208 /* setup DMA */ 209 pciide_channel_dma_setup(cp); 210 211 /* clear modes */ 212 patr = patr & (RDCIDE_PATR_EN(0) | RDCIDE_PATR_EN(1)); 213 psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->ch_channel); 214 psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->ch_channel); 215 for (drive = 0; drive < 2; drive++) { 216 udccr &= ~RDCIDE_UDCCR_EN(chp->ch_channel, drive); 217 udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->ch_channel, drive); 218 iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->ch_channel, drive); 219 } 220 /* now setup modes */ 221 for (drive = 0; drive < 2; drive++) { 222 if ((drvp[drive].drive_flags & DRIVE) == 0) 223 continue; 224 if ((drvp[drive].drive_flags & DRIVE_ATAPI) == 0) 225 patr |= RDCIDE_PATR_ATA(chp->ch_channel, drive); 226 if (drive == 0) { 227 patr |= RDCIDE_PATR_SETUP( 228 rdcide_setup[drvp[drive].PIO_mode], 229 chp->ch_channel); 230 patr |= RDCIDE_PATR_HOLD( 231 rdcide_hold[drvp[drive].PIO_mode], 232 chp->ch_channel); 233 } else { 234 patr |= RDCIDE_PATR_DEV1_TEN(chp->ch_channel); 235 psd1atr |= RDCIDE_PSD1ATR_SETUP( 236 rdcide_setup[drvp[drive].PIO_mode], 237 chp->ch_channel); 238 psd1atr |= RDCIDE_PSD1ATR_HOLD( 239 rdcide_hold[drvp[drive].PIO_mode], 240 chp->ch_channel); 241 } 242 if (drvp[drive].PIO_mode > 0) { 243 patr |= RDCIDE_PATR_FTIM(chp->ch_channel, drive); 244 patr |= RDCIDE_PATR_IORDY(chp->ch_channel, drive); 245 } 246 if (drvp[drive].drive_flags & DRIVE_DMA) { 247 patr |= RDCIDE_PATR_DMAEN(chp->ch_channel, drive); 248 } 249 if ((drvp[drive].drive_flags & DRIVE_UDMA) == 0) 250 continue; 251 252 if ((iiocr & RDCIDE_IIOCR_CABLE(chp->ch_channel, drive)) == 0 253 && drvp[drive].UDMA_mode > 2) 254 drvp[drive].UDMA_mode = 2; 255 udccr |= RDCIDE_UDCCR_EN(chp->ch_channel, drive); 256 udccr |= RDCIDE_UDCCR_TIM( 257 rdcide_udmatim[drvp[drive].UDMA_mode], 258 chp->ch_channel, drive); 259 iiocr |= RDCIDE_IIOCR_CLK( 260 rdcide_udmaclk[drvp[drive].UDMA_mode], 261 chp->ch_channel, drive); 262 } 263 264 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, patr); 265 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, psd1atr); 266 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, udccr); 267 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, iiocr); 268 } 269