1 /* $NetBSD: rccide.c,v 1.17 2007/10/24 23:08:07 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.17 2007/10/24 23:08:07 xtraeme Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 static void serverworks_chip_map(struct pciide_softc *, 41 struct pci_attach_args *); 42 static void serverworks_setup_channel(struct ata_channel *); 43 static int serverworks_pci_intr(void *); 44 static int serverworkscsb6_pci_intr(void *); 45 46 static int rccide_match(struct device *, struct cfdata *, void *); 47 static void rccide_attach(struct device *, struct device *, void *); 48 49 CFATTACH_DECL(rccide, sizeof(struct pciide_softc), 50 rccide_match, rccide_attach, NULL, NULL); 51 52 static const struct pciide_product_desc pciide_serverworks_products[] = { 53 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 54 0, 55 "ServerWorks OSB4 IDE Controller", 56 serverworks_chip_map, 57 }, 58 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 59 0, 60 "ServerWorks CSB5 IDE Controller", 61 serverworks_chip_map, 62 }, 63 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 64 0, 65 "ServerWorks CSB6 RAID/IDE Controller", 66 serverworks_chip_map, 67 }, 68 { PCI_PRODUCT_SERVERWORKS_CSB6_RAID, 69 0, 70 "ServerWorks CSB6 RAID/IDE Controller", 71 serverworks_chip_map, 72 }, 73 { PCI_PRODUCT_SERVERWORKS_HT1000_IDE, 74 0, 75 "ServerWorks HT-1000 IDE Controller", 76 serverworks_chip_map, 77 }, 78 { 0, 79 0, 80 NULL, 81 NULL, 82 } 83 }; 84 85 static int 86 rccide_match(struct device *parent, struct cfdata *match, 87 void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 91 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS && 92 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 93 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 94 if (pciide_lookup_product(pa->pa_id, 95 pciide_serverworks_products)) 96 return (2); 97 } 98 return (0); 99 } 100 101 static void 102 rccide_attach(struct device *parent, struct device *self, void *aux) 103 { 104 struct pci_attach_args *pa = aux; 105 struct pciide_softc *sc = (void *)self; 106 107 pciide_common_attach(sc, pa, 108 pciide_lookup_product(pa->pa_id, pciide_serverworks_products)); 109 } 110 111 static void 112 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 113 { 114 struct pciide_channel *cp; 115 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 116 pcitag_t pcib_tag; 117 int channel; 118 bus_size_t cmdsize, ctlsize; 119 120 if (pciide_chipen(sc, pa) == 0) 121 return; 122 123 aprint_verbose("%s: bus-master DMA support present", 124 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 125 pciide_mapreg_dma(sc, pa); 126 aprint_verbose("\n"); 127 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 128 129 if (sc->sc_dma_ok) { 130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 131 sc->sc_wdcdev.irqack = pciide_irqack; 132 } 133 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 134 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 135 switch (sc->sc_pp->ide_product) { 136 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 138 break; 139 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 140 if (PCI_REVISION(pa->pa_class) < 0x92) 141 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 142 else 143 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 144 break; 145 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 146 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 147 case PCI_PRODUCT_SERVERWORKS_HT1000_IDE: 148 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 149 break; 150 } 151 152 sc->sc_wdcdev.sc_atac.atac_set_modes = serverworks_setup_channel; 153 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 154 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 155 156 wdc_allocate_regs(&sc->sc_wdcdev); 157 158 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 159 channel++) { 160 cp = &sc->pciide_channels[channel]; 161 if (pciide_chansetup(sc, channel, interface) == 0) 162 continue; 163 switch (sc->sc_pp->ide_product) { 164 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 165 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 166 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 167 serverworkscsb6_pci_intr); 168 break; 169 default: 170 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 171 serverworks_pci_intr); 172 } 173 } 174 175 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 176 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 177 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 178 } 179 180 static void 181 serverworks_setup_channel(struct ata_channel *chp) 182 { 183 struct ata_drive_datas *drvp; 184 struct atac_softc *atac = chp->ch_atac; 185 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 186 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 187 int channel = chp->ch_channel; 188 int drive, unit, s; 189 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 190 u_int32_t idedma_ctl; 191 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 192 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 193 194 /* setup DMA if needed */ 195 pciide_channel_dma_setup(cp); 196 197 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 198 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 199 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 200 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 201 202 pio_time &= ~(0xffff << (16 * channel)); 203 dma_time &= ~(0xffff << (16 * channel)); 204 pio_mode &= ~(0xff << (8 * channel + 16)); 205 udma_mode &= ~(0xff << (8 * channel + 16)); 206 udma_mode &= ~(3 << (2 * channel)); 207 208 idedma_ctl = 0; 209 210 /* Per drive settings */ 211 for (drive = 0; drive < 2; drive++) { 212 drvp = &chp->ch_drive[drive]; 213 /* If no drive, skip */ 214 if ((drvp->drive_flags & DRIVE) == 0) 215 continue; 216 unit = drive + 2 * channel; 217 /* add timing values, setup DMA if needed */ 218 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 219 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 220 if ((atac->atac_cap & ATAC_CAP_UDMA) && 221 (drvp->drive_flags & DRIVE_UDMA)) { 222 /* use Ultra/DMA, check for 80-pin cable */ 223 if (drvp->UDMA_mode > 2 && 224 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 225 PCI_SUBSYS_ID_REG)) 226 & (1 << (14 + channel))) == 0) 227 drvp->UDMA_mode = 2; 228 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 229 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 230 udma_mode |= 1 << unit; 231 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 232 } else if ((atac->atac_cap & ATAC_CAP_DMA) && 233 (drvp->drive_flags & DRIVE_DMA)) { 234 /* use Multiword DMA */ 235 s = splbio(); 236 drvp->drive_flags &= ~DRIVE_UDMA; 237 splx(s); 238 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 239 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 240 } else { 241 /* PIO only */ 242 s = splbio(); 243 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 244 splx(s); 245 } 246 } 247 248 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 249 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 250 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 251 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 252 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 253 254 if (idedma_ctl != 0) { 255 /* Add software bits in status register */ 256 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 257 idedma_ctl); 258 } 259 } 260 261 static int 262 serverworks_pci_intr(arg) 263 void *arg; 264 { 265 struct pciide_softc *sc = arg; 266 struct pciide_channel *cp; 267 struct ata_channel *wdc_cp; 268 int rv = 0; 269 int dmastat, i, crv; 270 271 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 272 cp = &sc->pciide_channels[i]; 273 dmastat = bus_space_read_1(sc->sc_dma_iot, 274 cp->dma_iohs[IDEDMA_CTL], 0); 275 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 276 IDEDMA_CTL_INTR) 277 continue; 278 wdc_cp = &cp->ata_channel; 279 crv = wdcintr(wdc_cp); 280 if (crv == 0) { 281 printf("%s:%d: bogus intr\n", 282 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 283 bus_space_write_1(sc->sc_dma_iot, 284 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 285 } else 286 rv = 1; 287 } 288 return rv; 289 } 290 291 static int 292 serverworkscsb6_pci_intr(arg) 293 void *arg; 294 { 295 struct pciide_softc *sc = arg; 296 struct pciide_channel *cp; 297 struct ata_channel *wdc_cp; 298 int rv = 0; 299 int i, crv; 300 301 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 302 cp = &sc->pciide_channels[i]; 303 wdc_cp = &cp->ata_channel; 304 /* 305 * The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands. 306 * Until we find a way to know if the controller posted an 307 * interrupt, always call wdcintr(), which will try to guess 308 * if the interrupt was for us or not (and checks 309 * IDEDMA_CTL_INTR for DMA commands only). 310 */ 311 crv = wdcintr(wdc_cp); 312 if (crv != 0) 313 rv = 1; 314 } 315 return rv; 316 } 317