1 /* $NetBSD: radeonfbvar.h,v 1.2 2006/08/29 17:09:33 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 #ifndef _DEV_PCI_RADEONFBVAR_H 42 #define _DEV_PCI_RADEONFBVAR_H 43 44 #include "opt_splash.h" 45 46 #include <sys/param.h> 47 #include <sys/types.h> 48 #include <sys/device.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/wscons/wsdisplayvar.h> 51 #include <dev/wscons/wsconsio.h> 52 #include <dev/wsfont/wsfont.h> 53 #include <dev/rasops/rasops.h> 54 #include <dev/wscons/wsdisplay_vconsvar.h> 55 #include <dev/videomode/videomode.h> 56 #include <dev/videomode/edidvar.h> 57 #ifdef SPLASHSCREEN 58 #include <dev/splash/splash.h> 59 #endif 60 #include <dev/i2c/i2cvar.h> 61 62 /* XXX: change this when we complete the support for multi HEAD */ 63 #define RADEON_NDISPLAYS (1) 64 #define RADEON_MAXX (2048) 65 #define RADEON_MAXY (1536) 66 #define RADEON_MAXBPP (32) 67 #define RADEON_STRIDEALIGN (64) 68 #define RADEON_CURSORMAXX (64) 69 #define RADEON_CURSORMAXY (64) 70 #define RADEON_PANINCREMENT (1) 71 72 struct radeonfb_softc; 73 74 struct radeonfb_port { 75 int rp_number; 76 int rp_mon_type; 77 int rp_conn_type; 78 int rp_dac_type; 79 int rp_ddc_type; 80 int rp_tmds_type; 81 int rp_edid_valid; 82 struct edid_info rp_edid; 83 }; 84 85 /* connector values used by legacy bios */ 86 #define RADEON_CONN_NONE 0 87 #define RADEON_CONN_PROPRIETARY 1 /* think LVDS ribbon cable */ 88 #define RADEON_CONN_CRT 2 89 #define RADEON_CONN_DVI_I 3 90 #define RADEON_CONN_DVI_D 4 91 #define RADEON_CONN_CTV 5 92 #define RADEON_CONN_STV 6 93 #define RADEON_CONN_UNSUPPORTED 7 94 95 /* connector values used by atom bios */ 96 #define ATOM_CONN_NONE 0 97 #define ATOM_CONN_VGA 1 98 #define ATOM_CONN_DVI_I 2 99 #define ATOM_CONN_DVI_D 3 100 #define ATOM_CONN_DVI_A 4 101 #define ATOM_CONN_STV 5 102 #define ATOM_CONN_CTV 6 103 #define ATOM_CONN_LVDS 7 104 #define ATOM_CONN_DIGITAL 8 105 #define ATOM_CONN_UNSUPPORTED 9 106 107 #define RADEON_DDC_NONE 0 108 #define RADEON_DDC_MONID 1 109 #define RADEON_DDC_DVI 2 110 #define RADEON_DDC_VGA 3 111 #define RADEON_DDC_CRT2 4 112 113 #define RADEON_DAC_UNKNOWN -1 114 #define RADEON_DAC_PRIMARY 0 115 #define RADEON_DAC_TVDAC 1 116 117 #define RADEON_TMDS_UNKNOWN -1 118 #define RADEON_TMDS_INT 0 119 #define RADEON_TMDS_EXT 1 120 121 #define RADEON_MT_UNKNOWN -1 122 #define RADEON_MT_NONE 0 123 #define RADEON_MT_CRT 1 124 #define RADEON_MT_LCD 2 /* LVDS */ 125 #define RADEON_MT_DFP 3 /* TMDS */ 126 #define RADEON_MT_CTV 4 127 #define RADEON_MT_STV 5 128 129 struct radeonfb_i2c { 130 struct radeonfb_softc *ric_softc; 131 int ric_register; 132 struct i2c_controller ric_controller; 133 }; 134 135 struct radeonfb_crtc { 136 int rc_number; 137 struct videomode rc_videomode; 138 uint16_t rc_xoffset; 139 uint16_t rc_yoffset; 140 141 struct radeonfb_port *rc_port; 142 }; 143 144 struct radeonfb_cursor { 145 int rc_visible; 146 struct wsdisplay_curpos rc_pos; 147 struct wsdisplay_curpos rc_hot; 148 struct wsdisplay_curpos rc_size; 149 uint32_t rc_cmap[2]; 150 uint8_t rc_image[512]; /* 64x64x1 bit */ 151 uint8_t rc_mask[512]; /* 64x64x1 bit */ 152 }; 153 154 struct radeonfb_display { 155 struct radeonfb_softc *rd_softc; 156 int rd_number; /* 0 .. RADEON_NDISPLAYS */ 157 158 bus_size_t rd_offset; /* offset within FB memory */ 159 vaddr_t rd_fbptr; /* framebuffer pointer */ 160 vaddr_t rd_curptr; /* cursor data pointer */ 161 size_t rd_curoff; /* cursor offset */ 162 163 uint16_t rd_bpp; 164 uint16_t rd_virtx; 165 uint16_t rd_virty; 166 uint16_t rd_stride; 167 uint16_t rd_format; /* chip pixel format */ 168 169 uint16_t rd_xoffset; 170 uint16_t rd_yoffset; 171 172 int rd_bg; /* background */ 173 int rd_console; 174 175 int rd_wsmode; 176 177 int rd_ncrtcs; 178 struct radeonfb_crtc rd_crtcs[2]; 179 180 struct radeonfb_cursor rd_cursor; 181 /* XXX: this should probaby be an array for CRTCs */ 182 //struct videomode rd_videomode; 183 184 struct wsscreen_list rd_wsscreenlist; 185 struct wsscreen_descr rd_wsscreens_storage[1]; 186 struct wsscreen_descr *rd_wsscreens; 187 struct vcons_screen rd_vscreen; 188 struct vcons_data rd_vd; 189 190 191 #if 0 192 uint8_t rd_cmap_red[256]; 193 uint8_t rd_cmap_green[256]; 194 uint8_t rd_cmap_blue[256]; 195 #endif 196 197 #ifdef SPLASHSCREEN 198 struct splash_info rd_splash; 199 #endif 200 201 #ifdef SPLASHSCREEN_PROGRESS 202 struct splash_progress rd_progress; 203 #endif 204 }; 205 206 struct radeon_tmds_pll { 207 uint32_t rtp_freq; 208 uint32_t rtp_pll; 209 }; 210 211 struct radeonfb_softc { 212 struct device sc_dev; 213 uint16_t sc_family; 214 uint16_t sc_flags; 215 pcireg_t sc_id; 216 217 char sc_devinfo[256]; 218 219 bus_space_tag_t sc_regt; 220 bus_space_handle_t sc_regh; 221 bus_size_t sc_regsz; 222 bus_addr_t sc_regaddr; 223 224 bus_space_tag_t sc_memt; 225 bus_space_handle_t sc_memh; 226 bus_size_t sc_memsz; 227 bus_addr_t sc_memaddr; 228 229 bus_space_tag_t sc_iot; 230 bus_space_handle_t sc_ioh; 231 bus_size_t sc_iosz; 232 bus_addr_t sc_ioaddr; 233 234 /* size of a single display */ 235 int sc_maxx; 236 int sc_maxy; 237 int sc_maxbpp; 238 int sc_fboffset; 239 int sc_fbsize; 240 241 bus_space_tag_t sc_romt; 242 bus_space_handle_t sc_romh; 243 bus_size_t sc_romsz; 244 bus_space_handle_t sc_biosh; 245 246 bus_dma_tag_t sc_dmat; 247 248 uint16_t sc_refclk; 249 uint16_t sc_refdiv; 250 uint32_t sc_minpll; 251 uint32_t sc_maxpll; 252 253 pci_chipset_tag_t sc_pc; 254 pcitag_t sc_pt; 255 256 /* card's idea of addresses, internally */ 257 uint32_t sc_aperbase; 258 259 int sc_ndisplays; 260 struct radeonfb_display sc_displays[RADEON_NDISPLAYS]; 261 262 int sc_nports; 263 struct radeonfb_port sc_ports[2]; 264 265 struct radeon_tmds_pll sc_tmds_pll[4]; 266 267 struct radeonfb_i2c sc_i2c[4]; 268 269 uint8_t *sc_bios; 270 bus_size_t sc_biossz; 271 272 char *sc_modebuf; 273 const char *sc_defaultmode; 274 }; 275 276 /* chip families */ 277 #define RADEON_R100 1 278 #define RADEON_RV100 2 279 #define RADEON_RS100 3 280 #define RADEON_RV200 4 281 #define RADEON_RS200 5 282 #define RADEON_R200 6 283 #define RADEON_RV250 7 284 #define RADEON_RS300 8 285 #define RADEON_RV280 9 286 #define RADEON_R300 10 287 #define RADEON_R350 11 288 #define RADEON_RV350 12 289 #define RADEON_RV380 13 290 #define RADEON_R420 14 291 #define RADEON_FAMILIES 15 292 293 /* feature flags */ 294 #define RFB_MOB (1 << 0) /* Mobility */ 295 #define RFB_NCRTC2 (1 << 1) /* No CRTC2 */ 296 #define RFB_IGP (1 << 2) 297 #define RFB_R300CG (1 << 3) 298 #define RFB_SDAC (1 << 4) /* Single DAC */ 299 #define RFB_R300 (1 << 5) /* R300 variants -- newer parts */ 300 #define RFB_RV100 (1 << 6) /* RV100 variants -- previous gen */ 301 #define RFB_ATOM (1 << 7) /* ATOM bios */ 302 303 #define IS_MOBILITY(sc) ((sc)->sc_flags & RFB_MOB) 304 #define HAS_CRTC2(sc) (((sc)->sc_flags & RFB_NCRTC2) == 0) 305 306 #define IS_R300(sc) ((sc)->sc_flags & RFB_R300) 307 #define HAS_R300CG(sc) ((sc)->sc_flags & RFB_R300CG) 308 #define HAS_SDAC(sc) ((sc)->sc_flags & RFB_SDAC) 309 #define IS_RV100(sc) ((sc)->sc_flags & RFB_RV100) 310 #define IS_IGP(sc) ((sc)->sc_flags & RFB_IGP) 311 #define IS_ATOM(sc) ((sc)->sc_flags & RFB_ATOM) 312 313 #define RADEON_TIMEOUT 2000000 314 315 #define GET32(sc, r) radeonfb_get32(sc, r) 316 #define PUT32(sc, r, v) radeonfb_put32(sc, r, v) 317 #define SET32(sc, r, v) PUT32(sc, r, GET32(sc, r) | (v)) 318 #define CLR32(sc, r, v) PUT32(sc, r, GET32(sc, r) & ~(v)) 319 #define PATCH32(sc, r, v, m) PUT32(sc, r, (GET32(sc, r) & (m)) | (v)) 320 321 322 #define GETPLL(sc, r) radeonfb_getpll(sc, r) 323 #define PUTPLL(sc, r, v) radeonfb_putpll(sc, r, v) 324 #define SETPLL(sc, r, v) PUTPLL(sc, r, GETPLL(sc, r) | (v)) 325 #define CLRPLL(sc, r, v) PUTPLL(sc, r, GETPLL(sc, r) & ~(v)) 326 #define PATCHPLL(sc, r, v, m) PUTPLL(sc, r, (GETPLL(sc, r) & (m)) | (v)) 327 328 #define GETROM32(sc, r) bus_space_read_4(sc->sc_romt, sc->sc_romh, r) 329 #define GETROM16(sc, r) bus_space_read_2(sc->sc_romt, sc->sc_romh, r) 330 #define GETROM8(sc, r) bus_space_read_1(sc->sc_romt, sc->sc_romh, r) 331 332 /* 333 * Some values in BIOS are misaligned... 334 */ 335 #define GETBIOS8(sc, r) ((sc)->sc_bios[(r)]) 336 337 #define GETBIOS16(sc, r) \ 338 ((GETBIOS8(sc, (r) + 1) << 8) | GETBIOS8(sc, (r))) 339 340 #define GETBIOS32(sc, r) \ 341 ((GETBIOS16(sc, (r) + 2) << 16) | GETBIOS16(sc, (r))) 342 343 #define XNAME(sc) device_xname(&sc->sc_dev) 344 345 #define DIVIDE(x,y) (((x) + (y / 2)) / (y)) 346 347 uint32_t radeonfb_get32(struct radeonfb_softc *, uint32_t); 348 void radeonfb_put32(struct radeonfb_softc *, uint32_t, uint32_t); 349 void radeonfb_mask32(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t); 350 351 uint32_t radeonfb_getindex(struct radeonfb_softc *, uint32_t); 352 void radeonfb_putindex(struct radeonfb_softc *, uint32_t, uint32_t); 353 void radeonfb_maskindex(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t); 354 355 uint32_t radeonfb_getpll(struct radeonfb_softc *, uint32_t); 356 void radeonfb_putpll(struct radeonfb_softc *, uint32_t, uint32_t); 357 void radeonfb_maskpll(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t); 358 359 #ifdef RADEON_BIOS_INIT 360 int radeonfb_bios_init(struct radeonfb_softc *); 361 #endif 362 363 void radeonfb_i2c_init(struct radeonfb_softc *); 364 int radeonfb_i2c_read_edid(struct radeonfb_softc *, int, uint8_t *); 365 366 #endif /* _DEV_PCI_RADEONFBVAR_H */ 367