1 /* $NetBSD: radeonfb.c,v 1.41 2011/01/22 15:14:28 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.41 2011/01/22 15:14:28 cegger Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 8 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 #include <dev/pci/wsdisplay_pci.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 103 static int radeonfb_match(device_t, cfdata_t, void *); 104 static void radeonfb_attach(device_t, device_t, void *); 105 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 106 struct lwp *); 107 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 108 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 109 static void radeonfb_loadbios(struct radeonfb_softc *, 110 struct pci_attach_args *); 111 112 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 113 uintmax_t); 114 static int radeonfb_getclocks(struct radeonfb_softc *); 115 static int radeonfb_gettmds(struct radeonfb_softc *); 116 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 117 uint32_t *, uint32_t *); 118 static int radeonfb_getconnectors(struct radeonfb_softc *); 119 static const struct videomode *radeonfb_modelookup(const char *); 120 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 121 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 122 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 123 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 124 static void radeonfb_modeswitch(struct radeonfb_display *); 125 static void radeonfb_setcrtc(struct radeonfb_display *, int); 126 static void radeonfb_init_misc(struct radeonfb_softc *); 127 static void radeonfb_set_fbloc(struct radeonfb_softc *); 128 static void radeonfb_init_palette(struct radeonfb_softc *, int); 129 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 130 131 static int radeonfb_isblank(struct radeonfb_display *); 132 static void radeonfb_blank(struct radeonfb_display *, int); 133 static int radeonfb_set_cursor(struct radeonfb_display *, 134 struct wsdisplay_cursor *); 135 static int radeonfb_set_curpos(struct radeonfb_display *, 136 struct wsdisplay_curpos *); 137 138 /* acceleration support */ 139 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 140 int width, int height, uint32_t color); 141 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 142 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 143 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 144 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 145 int, uint32_t, uint32_t); 146 147 /* hw cursor support */ 148 static void radeonfb_cursor_cmap(struct radeonfb_display *); 149 static void radeonfb_cursor_shape(struct radeonfb_display *); 150 static void radeonfb_cursor_position(struct radeonfb_display *); 151 static void radeonfb_cursor_visible(struct radeonfb_display *); 152 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 153 154 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 155 static void radeonfb_engine_idle(struct radeonfb_softc *); 156 static void radeonfb_engine_flush(struct radeonfb_softc *); 157 static void radeonfb_engine_reset(struct radeonfb_softc *); 158 static void radeonfb_engine_init(struct radeonfb_display *); 159 static inline void radeonfb_unclip(struct radeonfb_softc *); 160 161 static void radeonfb_eraserows(void *, int, int, long); 162 static void radeonfb_erasecols(void *, int, int, int, long); 163 static void radeonfb_copyrows(void *, int, int, int); 164 static void radeonfb_copycols(void *, int, int, int, int); 165 static void radeonfb_cursor(void *, int, int, int); 166 static void radeonfb_putchar(void *, int, int, unsigned, long); 167 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 168 static int radeonfb_allocattr(void *, int, int, int, long *); 169 170 static int radeonfb_get_backlight(struct radeonfb_display *); 171 static int radeonfb_set_backlight(struct radeonfb_display *, int); 172 static void radeonfb_lvds_callout(void *); 173 174 static void radeonfb_brightness_up(device_t); 175 static void radeonfb_brightness_down(device_t); 176 177 static struct videomode *radeonfb_best_refresh(struct videomode *, 178 struct videomode *); 179 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 180 uint16_t *, int); 181 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 182 struct radeonfb_port *, int, int); 183 184 static int radeonfb_drm_print(void *, const char *); 185 186 #ifdef RADEONFB_DEBUG 187 int radeon_debug = 1; 188 #define DPRINTF(x) \ 189 if (radeon_debug) printf x 190 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 191 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 192 #else 193 #define DPRINTF(x) 194 #define PRINTREG(r) 195 #define PRINTPLL(r) 196 #endif 197 198 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 199 200 #ifndef RADEON_DEFAULT_MODE 201 /* any reasonably modern display should handle this */ 202 #define RADEON_DEFAULT_MODE "1024x768x60" 203 #endif 204 205 extern const u_char rasops_cmap[768]; 206 207 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 208 209 static struct { 210 int size; /* minimum memory size (MB) */ 211 int maxx; /* maximum x dimension */ 212 int maxy; /* maximum y dimension */ 213 int maxbpp; /* maximum bpp */ 214 int maxdisp; /* maximum logical display count */ 215 } radeonfb_limits[] = { 216 { 32, 2048, 1536, 32, 2 }, 217 { 16, 1600, 1200, 32, 2 }, 218 { 8, 1600, 1200, 32, 1 }, 219 { 0, 0, 0, 0, 0 }, 220 }; 221 222 static struct wsscreen_descr radeonfb_stdscreen = { 223 "fb", /* name */ 224 0, 0, /* ncols, nrows */ 225 NULL, /* textops */ 226 8, 16, /* fontwidth, fontheight */ 227 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 228 0, /* modecookie */ 229 }; 230 231 struct wsdisplay_accessops radeonfb_accessops = { 232 radeonfb_ioctl, 233 radeonfb_mmap, 234 NULL, /* vcons_alloc_screen */ 235 NULL, /* vcons_free_screen */ 236 NULL, /* vcons_show_screen */ 237 NULL, /* load_font */ 238 NULL, /* pollc */ 239 NULL, /* scroll */ 240 }; 241 242 static struct { 243 uint16_t devid; 244 uint16_t family; 245 uint16_t flags; 246 } radeonfb_devices[] = 247 { 248 /* R100 family */ 249 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 252 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 253 254 /* RV100 family */ 255 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 256 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 257 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 259 260 /* RS100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 263 264 /* RS200/RS250 family */ 265 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 266 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 269 270 /* R200 family */ 271 /* add more R200 products? , 5148 */ 272 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 277 278 /* RV200 family */ 279 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 283 284 /* RV250 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 290 291 /* RS300 family */ 292 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 296 297 /* RV280 family */ 298 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 305 306 /* R300 family */ 307 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 315 316 /* RV350/RV360 family */ 317 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 329 330 /* R350/R360 family */ 331 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 339 340 /* RV380/RV370 family */ 341 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 350 351 /* R420/R423 family */ 352 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 369 370 { 0, 0, 0 } 371 }; 372 373 static struct { 374 int divider; 375 int mask; 376 } radeonfb_dividers[] = { 377 { 1, 0 }, 378 { 2, 1 }, 379 { 3, 4 }, 380 { 4, 2 }, 381 { 6, 6 }, 382 { 8, 3 }, 383 { 12, 7 }, 384 { 0, 0 } 385 }; 386 387 /* 388 * This table taken from X11. 389 */ 390 static const struct { 391 int family; 392 struct radeon_tmds_pll plls[4]; 393 } radeonfb_tmds_pll[] = { 394 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 395 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 396 { RADEON_RS100, {{0, 0}}}, 397 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 400 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 401 { RADEON_RS300, {{0, 0}}}, 402 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 403 { RADEON_R300, {{-1, 0xb01cb}}}, 404 { RADEON_R350, {{-1, 0xb01cb}}}, 405 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 406 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 407 { RADEON_R420, {{-1, 0xb01cb}}}, 408 }; 409 410 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 411 412 413 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 414 radeonfb_match, radeonfb_attach, NULL, NULL); 415 416 static int 417 radeonfb_match(device_t parent, cfdata_t match, void *aux) 418 { 419 struct pci_attach_args *pa = aux; 420 int i; 421 422 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 423 return 0; 424 425 for (i = 0; radeonfb_devices[i].devid; i++) { 426 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 427 return 100; /* high to defeat VGA/VESA */ 428 } 429 430 return 0; 431 } 432 433 static void 434 radeonfb_attach(device_t parent, device_t dev, void *aux) 435 { 436 struct radeonfb_softc *sc = device_private(dev); 437 struct pci_attach_args *pa = aux; 438 const char *mptr; 439 bus_size_t bsz; 440 pcireg_t screg; 441 int i, j, fg, bg, ul, flags; 442 uint32_t v; 443 444 sc->sc_id = pa->pa_id; 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 447 break; 448 } 449 450 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 451 sizeof(sc->sc_devinfo)); 452 453 aprint_naive("\n"); 454 aprint_normal(": %s\n", sc->sc_devinfo); 455 456 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 457 458 KASSERT(radeonfb_devices[i].devid != 0); 459 sc->sc_pt = pa->pa_tag; 460 sc->sc_iot = pa->pa_iot; 461 sc->sc_pc = pa->pa_pc; 462 sc->sc_family = radeonfb_devices[i].family; 463 sc->sc_flags = radeonfb_devices[i].flags; 464 465 /* enable memory and IO access */ 466 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 467 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 468 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 469 470 /* 471 * Some flags are general to entire chip families, and rather 472 * than clutter up the table with them, we go ahead and set 473 * them here. 474 */ 475 switch (sc->sc_family) { 476 case RADEON_RS100: 477 case RADEON_RS200: 478 sc->sc_flags |= RFB_IGP | RFB_RV100; 479 break; 480 481 case RADEON_RV100: 482 case RADEON_RV200: 483 case RADEON_RV250: 484 case RADEON_RV280: 485 sc->sc_flags |= RFB_RV100; 486 break; 487 488 case RADEON_RS300: 489 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_R300: 493 case RADEON_RV350: 494 case RADEON_R350: 495 case RADEON_RV380: 496 case RADEON_R420: 497 /* newer chips */ 498 sc->sc_flags |= RFB_R300; 499 break; 500 501 case RADEON_R100: 502 sc->sc_flags |= RFB_NCRTC2; 503 break; 504 } 505 506 if ((sc->sc_family == RADEON_RV200) || 507 (sc->sc_family == RADEON_RV250) || 508 (sc->sc_family == RADEON_RV280) || 509 (sc->sc_family == RADEON_RV350)) { 510 bool inverted = 0; 511 /* backlight level is linear */ 512 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 513 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 514 "backlight_level_reverted", &inverted); 515 if (inverted) { 516 DPRINTF(("nope, it's inverted\n")); 517 sc->sc_flags |= RFB_INV_BLIGHT; 518 } 519 } else 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 522 /* 523 * XXX: to support true multihead, this must change. 524 */ 525 sc->sc_ndisplays = 1; 526 527 /* XXX: */ 528 if (!HAS_CRTC2(sc)) { 529 sc->sc_ndisplays = 1; 530 } 531 532 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 533 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 534 &sc->sc_regsz) != 0) { 535 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 536 goto error; 537 } 538 539 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 540 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 541 { 542 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 543 goto error; 544 } 545 sc->sc_romt = sc->sc_memt; 546 547 /* scratch register test... */ 548 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 549 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 550 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 551 goto error; 552 } 553 554 PRINTREG(RADEON_BIOS_4_SCRATCH); 555 PRINTREG(RADEON_FP_GEN_CNTL); 556 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 557 PRINTREG(RADEON_FP2_GEN_CNTL); 558 PRINTREG(RADEON_TMDS_CNTL); 559 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 560 PRINTREG(RADEON_TMDS_PLL_CNTL); 561 PRINTREG(RADEON_LVDS_GEN_CNTL); 562 PRINTREG(RADEON_FP_HORZ_STRETCH); 563 PRINTREG(RADEON_FP_VERT_STRETCH); 564 565 /* XXX: RV100 specific */ 566 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 567 568 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 569 RADEON_TMDS_TRANSMITTER_PLLEN, 570 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 571 572 radeonfb_i2c_init(sc); 573 574 radeonfb_loadbios(sc, pa); 575 576 #ifdef RADEONFB_BIOS_INIT 577 if (radeonfb_bios_init(sc)) { 578 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 579 } 580 #endif 581 582 if (radeonfb_getclocks(sc)) { 583 aprint_error("%s: Unable to get reference clocks from BIOS\n", 584 XNAME(sc)); 585 goto error; 586 } 587 588 if (radeonfb_gettmds(sc)) { 589 aprint_error("%s: Unable to identify TMDS PLL settings\n", 590 XNAME(sc)); 591 goto error; 592 } 593 594 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 595 "minpll = %d, maxpll = %d\n", XNAME(sc), 596 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 597 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 598 599 radeonfb_getconnectors(sc); 600 601 radeonfb_set_fbloc(sc); 602 603 for (i = 0; radeonfb_limits[i].size; i++) { 604 if (sc->sc_memsz >= radeonfb_limits[i].size) { 605 sc->sc_maxx = radeonfb_limits[i].maxx; 606 sc->sc_maxy = radeonfb_limits[i].maxy; 607 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 608 /* framebuffer offset, start at a 4K page */ 609 sc->sc_fboffset = sc->sc_memsz / 610 radeonfb_limits[i].maxdisp; 611 /* 612 * we use the fbsize to figure out where we can store 613 * things like cursor data. 614 */ 615 sc->sc_fbsize = 616 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 617 RADEON_STRIDEALIGN) * sc->sc_maxy, 618 4096); 619 break; 620 } 621 } 622 623 624 radeonfb_init_misc(sc); 625 radeonfb_init_palette(sc, 0); 626 if (HAS_CRTC2(sc)) 627 radeonfb_init_palette(sc, 1); 628 629 /* program the DAC wirings */ 630 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 631 switch (sc->sc_ports[i].rp_dac_type) { 632 case RADEON_DAC_PRIMARY: 633 PATCH32(sc, RADEON_DAC_CNTL2, 634 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 635 ~RADEON_DAC2_DAC_CLK_SEL); 636 break; 637 case RADEON_DAC_TVDAC: 638 /* we always use the TVDAC to drive a secondary analog 639 * CRT for now. if we ever support TV-out this will 640 * have to change. 641 */ 642 SET32(sc, RADEON_DAC_CNTL2, 643 RADEON_DAC2_DAC2_CLK_SEL); 644 PATCH32(sc, RADEON_DISP_HW_DEBUG, 645 i ? 0 : RADEON_CRT2_DISP1_SEL, 646 ~RADEON_CRT2_DISP1_SEL); 647 break; 648 } 649 } 650 PRINTREG(RADEON_DAC_CNTL2); 651 PRINTREG(RADEON_DISP_HW_DEBUG); 652 653 /* other DAC programming */ 654 v = GET32(sc, RADEON_DAC_CNTL); 655 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 656 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 657 PUT32(sc, RADEON_DAC_CNTL, v); 658 PRINTREG(RADEON_DAC_CNTL); 659 660 /* XXX: this may need more investigation */ 661 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 662 PRINTREG(RADEON_TV_DAC_CNTL); 663 664 /* enable TMDS */ 665 SET32(sc, RADEON_FP_GEN_CNTL, 666 RADEON_FP_TMDS_EN | 667 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 668 RADEON_FP_CRTC_DONT_SHADOW_HEND); 669 /* 670 * XXX 671 * no idea why this is necessary - if I do not clear this bit on my 672 * iBook G4 the screen remains black, even though it's already clear. 673 * It needs to be set on my Sun XVR-100 for the DVI port to work 674 */ 675 676 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 677 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 678 } else 679 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 681 if (HAS_CRTC2(sc)) 682 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 683 684 /* 685 * we use bus_space_map instead of pci_mapreg, because we don't 686 * need the full aperature space. no point in wasting virtual 687 * address space we don't intend to use, right? 688 */ 689 if ((sc->sc_memsz < (4096 * 1024)) || 690 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 691 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 692 (bsz < sc->sc_memsz)) { 693 sc->sc_memsz = 0; 694 aprint_error("%s: Bad frame buffer configuration\n", 695 XNAME(sc)); 696 goto error; 697 } 698 699 /* 64 MB should be enough -- more just wastes map entries */ 700 if (sc->sc_memsz > (64 << 20)) 701 sc->sc_memsz = (64 << 20); 702 703 sc->sc_memt = pa->pa_memt; 704 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 705 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 706 sc->sc_memsz = 0; 707 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 708 goto error; 709 } 710 711 aprint_normal("%s: %d MB aperture at 0x%08x, " 712 "%d KB registers at 0x%08x\n", XNAME(sc), 713 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 714 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 715 716 /* setup default video mode from devprop (allows PROM override) */ 717 sc->sc_defaultmode = radeonfb_default_mode; 718 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 719 "videomode", &mptr)) { 720 721 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 722 sc->sc_defaultmode = sc->sc_modebuf; 723 } 724 725 /* initialize some basic display parameters */ 726 for (i = 0; i < sc->sc_ndisplays; i++) { 727 struct radeonfb_display *dp = &sc->sc_displays[i]; 728 struct rasops_info *ri; 729 long defattr; 730 struct wsemuldisplaydev_attach_args aa; 731 732 /* 733 * Figure out how many "displays" (desktops) we are going to 734 * support. If more than one, then each CRTC gets its own 735 * programming. 736 * 737 * XXX: this code needs to change to support mergedfb. 738 * XXX: would be nice to allow this to be overridden 739 */ 740 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 741 DPRINTF(("dual crtcs!\n")); 742 dp->rd_ncrtcs = 2; 743 dp->rd_crtcs[0].rc_number = 0; 744 dp->rd_crtcs[1].rc_number = 1; 745 } else { 746 dp->rd_ncrtcs = 1; 747 dp->rd_crtcs[0].rc_number = i; 748 } 749 750 /* set up port pointer */ 751 for (j = 0; j < dp->rd_ncrtcs; j++) { 752 dp->rd_crtcs[j].rc_port = 753 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 754 } 755 756 dp->rd_softc = sc; 757 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 758 dp->rd_bg = WS_DEFAULT_BG; 759 #if 0 760 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 761 #else 762 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 763 #endif 764 /* for text mode, we pick a resolution that won't 765 * require panning */ 766 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 767 768 aprint_normal("%s: display %d: " 769 "initial virtual resolution %dx%d at %d bpp\n", 770 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 771 772 /* now select the *video mode* that we will use */ 773 for (j = 0; j < dp->rd_ncrtcs; j++) { 774 const struct videomode *vmp; 775 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 776 dp->rd_virtx, dp->rd_virty); 777 778 /* 779 * virtual resolution should be at least as high as 780 * physical 781 */ 782 if (dp->rd_virtx < vmp->hdisplay || 783 dp->rd_virty < vmp->vdisplay) { 784 dp->rd_virtx = vmp->hdisplay; 785 dp->rd_virty = vmp->vdisplay; 786 } 787 788 dp->rd_crtcs[j].rc_videomode = *vmp; 789 printf("%s: port %d: physical %dx%d %dHz\n", 790 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 791 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 792 vmp->htotal), vmp->vtotal)); 793 } 794 795 /* N.B.: radeon wants 64-byte aligned stride */ 796 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 797 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 798 799 dp->rd_offset = sc->sc_fboffset * i; 800 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 801 sc->sc_memh) + dp->rd_offset; 802 dp->rd_curoff = sc->sc_fbsize; 803 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 804 805 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 806 807 switch (dp->rd_bpp) { 808 case 8: 809 dp->rd_format = 2; 810 break; 811 case 32: 812 dp->rd_format = 6; 813 break; 814 default: 815 aprint_error("%s: bad depth %d\n", XNAME(sc), 816 dp->rd_bpp); 817 goto error; 818 } 819 820 DPRINTF("init engine\n"); 821 /* XXX: this seems suspicious - per display engine 822 initialization? */ 823 radeonfb_engine_init(dp); 824 825 /* copy the template into place */ 826 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 827 dp->rd_wsscreens = dp->rd_wsscreens_storage; 828 829 /* and make up the list */ 830 dp->rd_wsscreenlist.nscreens = 1; 831 dp->rd_wsscreenlist.screens = 832 (const struct wsscreen_descr **)&dp->rd_wsscreens; 833 834 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 835 &radeonfb_accessops); 836 837 dp->rd_vd.init_screen = radeonfb_init_screen; 838 839 dp->rd_console = 0; 840 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 841 "is_console", &dp->rd_console); 842 843 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 844 845 846 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 847 dp->rd_console, &defattr); 848 849 ri = &dp->rd_vscreen.scr_ri; 850 851 /* clear the screen */ 852 rasops_unpack_attr(defattr, &fg, &bg, &ul); 853 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 854 ri->ri_devcmap[bg & 0xf]); 855 856 dp->rd_wsscreens->textops = &ri->ri_ops; 857 dp->rd_wsscreens->capabilities = ri->ri_caps; 858 dp->rd_wsscreens->nrows = ri->ri_rows; 859 dp->rd_wsscreens->ncols = ri->ri_cols; 860 861 #ifdef SPLASHSCREEN 862 dp->rd_splash.si_depth = ri->ri_depth; 863 dp->rd_splash.si_bits = ri->ri_bits; 864 dp->rd_splash.si_hwbits = ri->ri_hwbits; 865 dp->rd_splash.si_width = ri->ri_width; 866 dp->rd_splash.si_height = ri->ri_height; 867 dp->rd_splash.si_stride = ri->ri_stride; 868 dp->rd_splash.si_fillrect = NULL; 869 #endif 870 if (dp->rd_console) { 871 872 radeonfb_modeswitch(dp); 873 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 874 defattr); 875 #ifdef SPLASHSCREEN 876 splash_render(&dp->rd_splash, 877 SPLASH_F_CENTER|SPLASH_F_FILL); 878 #else 879 vcons_replay_msgbuf(&dp->rd_vscreen); 880 #endif 881 882 #ifdef SPLASHSCREEN_PROGRESS 883 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 884 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 885 dp->rd_progress.sp_left = (dp->rd_virtx - 886 dp->rd_progress.sp_width) / 2; 887 dp->rd_progress.sp_height = 20; 888 dp->rd_progress.sp_state = -1; 889 dp->rd_progress.sp_si = &dp->rd_splash; 890 splash_progress_init(&dp->rd_progress); 891 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 892 #endif 893 894 } else { 895 896 /* 897 * since we're not the console we can postpone 898 * the rest until someone actually allocates a 899 * screen for us. but we do clear the screen 900 * at least. 901 */ 902 memset(ri->ri_bits, 0, 1024); 903 904 radeonfb_modeswitch(dp); 905 #ifdef SPLASHSCREEN 906 splash_render(&dp->rd_splash, 907 SPLASH_F_CENTER|SPLASH_F_FILL); 908 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 909 #endif 910 } 911 912 aa.console = dp->rd_console; 913 aa.scrdata = &dp->rd_wsscreenlist; 914 aa.accessops = &radeonfb_accessops; 915 aa.accesscookie = &dp->rd_vd; 916 917 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 918 919 radeonfb_blank(dp, 0); 920 921 /* Initialise delayed lvds operations for backlight. */ 922 callout_init(&dp->rd_bl_lvds_co, 0); 923 callout_setfunc(&dp->rd_bl_lvds_co, 924 radeonfb_lvds_callout, dp); 925 } 926 927 /* 928 * if we have console output via firmware like on sparc64 it may 929 * interfere with DAC programming so program the palette again 930 * here after we took over 931 */ 932 radeonfb_init_palette(sc, 0); 933 if (HAS_CRTC2(sc)) 934 radeonfb_init_palette(sc, 1); 935 936 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 937 radeonfb_brightness_up, TRUE); 938 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 939 radeonfb_brightness_down, TRUE); 940 941 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 942 943 return; 944 945 error: 946 if (sc->sc_biossz) 947 free(sc->sc_bios, M_DEVBUF); 948 949 if (sc->sc_regsz) 950 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 951 952 if (sc->sc_memsz) 953 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 954 } 955 956 static int 957 radeonfb_drm_print(void *aux, const char *pnp) 958 { 959 if (pnp) 960 aprint_normal("drm at %s", pnp); 961 return (UNCONF); 962 } 963 964 int 965 radeonfb_ioctl(void *v, void *vs, 966 unsigned long cmd, void *d, int flag, struct lwp *l) 967 { 968 struct vcons_data *vd; 969 struct radeonfb_display *dp; 970 struct radeonfb_softc *sc; 971 struct wsdisplay_param *param; 972 973 vd = (struct vcons_data *)v; 974 dp = (struct radeonfb_display *)vd->cookie; 975 sc = dp->rd_softc; 976 977 switch (cmd) { 978 case WSDISPLAYIO_GTYPE: 979 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 980 return 0; 981 982 case WSDISPLAYIO_GINFO: 983 if (vd->active != NULL) { 984 struct wsdisplay_fbinfo *fb; 985 fb = (struct wsdisplay_fbinfo *)d; 986 fb->width = dp->rd_virtx; 987 fb->height = dp->rd_virty; 988 fb->depth = dp->rd_bpp; 989 fb->cmsize = 256; 990 return 0; 991 } else 992 return ENODEV; 993 case WSDISPLAYIO_GVIDEO: 994 if (radeonfb_isblank(dp)) 995 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 996 else 997 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 998 return 0; 999 1000 case WSDISPLAYIO_SVIDEO: 1001 radeonfb_blank(dp, 1002 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1003 return 0; 1004 1005 case WSDISPLAYIO_GETCMAP: 1006 #if 0 1007 if (dp->rd_bpp == 8) 1008 return radeonfb_getcmap(sc, 1009 (struct wsdisplay_cmap *)d); 1010 #endif 1011 return EINVAL; 1012 1013 case WSDISPLAYIO_PUTCMAP: 1014 #if 0 1015 if (dp->rd_bpp == 8) 1016 return radeonfb_putcmap(sc, 1017 (struct wsdisplay_cmap *)d); 1018 #endif 1019 return EINVAL; 1020 1021 case WSDISPLAYIO_LINEBYTES: 1022 *(unsigned *)d = dp->rd_stride; 1023 return 0; 1024 1025 case WSDISPLAYIO_SMODE: 1026 if (*(int *)d != dp->rd_wsmode) { 1027 dp->rd_wsmode = *(int *)d; 1028 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1029 (dp->rd_vd.active)) { 1030 radeonfb_engine_init(dp); 1031 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1032 radeonfb_modeswitch(dp); 1033 vcons_redraw_screen(dp->rd_vd.active); 1034 } 1035 } 1036 return 0; 1037 1038 case WSDISPLAYIO_GCURMAX: 1039 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1040 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1041 return 0; 1042 1043 case WSDISPLAYIO_SCURSOR: 1044 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1045 1046 case WSDISPLAYIO_GCURSOR: 1047 return EPASSTHROUGH; 1048 1049 case WSDISPLAYIO_GCURPOS: 1050 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1051 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1052 return 0; 1053 1054 case WSDISPLAYIO_SCURPOS: 1055 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1056 1057 case WSDISPLAYIO_SSPLASH: 1058 #if defined(SPLASHSCREEN) 1059 if (*(int *)d == 1) { 1060 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1061 splash_render(&dp->rd_splash, 1062 SPLASH_F_CENTER|SPLASH_F_FILL); 1063 } else 1064 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1065 return 0; 1066 #else 1067 return ENODEV; 1068 #endif 1069 case WSDISPLAYIO_SPROGRESS: 1070 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1071 dp->rd_progress.sp_force = 1; 1072 splash_progress_update(&dp->rd_progress); 1073 dp->rd_progress.sp_force = 0; 1074 return 0; 1075 #else 1076 return ENODEV; 1077 #endif 1078 case WSDISPLAYIO_GETPARAM: 1079 param = (struct wsdisplay_param *)d; 1080 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1081 param->min = 0; 1082 param->max = RADEONFB_BACKLIGHT_MAX; 1083 param->curval = radeonfb_get_backlight(dp); 1084 return 0; 1085 } 1086 return EPASSTHROUGH; 1087 1088 case WSDISPLAYIO_SETPARAM: 1089 param = (struct wsdisplay_param *)d; 1090 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1091 return radeonfb_set_backlight(dp, param->curval); 1092 } 1093 return EPASSTHROUGH; 1094 1095 /* PCI config read/write passthrough. */ 1096 case PCI_IOC_CFGREAD: 1097 case PCI_IOC_CFGWRITE: 1098 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1099 1100 case WSDISPLAYIO_GET_BUSID: 1101 return wsdisplayio_busid_pci(&sc->sc_dev, sc->sc_pc, 1102 sc->sc_pt, d); 1103 1104 default: 1105 return EPASSTHROUGH; 1106 } 1107 } 1108 1109 paddr_t 1110 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1111 { 1112 struct vcons_data *vd; 1113 struct radeonfb_display *dp; 1114 struct radeonfb_softc *sc; 1115 paddr_t pa; 1116 1117 vd = (struct vcons_data *)v; 1118 dp = (struct radeonfb_display *)vd->cookie; 1119 sc = dp->rd_softc; 1120 1121 /* XXX: note that we don't allow mapping of registers right now */ 1122 /* XXX: this means that the XFree86 radeon driver won't work */ 1123 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1124 pa = bus_space_mmap(sc->sc_memt, 1125 sc->sc_memaddr + dp->rd_offset + offset, 0, 1126 prot, BUS_SPACE_MAP_LINEAR); 1127 return pa; 1128 } 1129 1130 #ifdef RADEONFB_MMAP_BARS 1131 /* 1132 * restrict all other mappings to processes with superuser privileges 1133 * or the kernel itself 1134 */ 1135 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1136 NULL) != 0) { 1137 aprint_error_dev(&sc->sc_dev, "mmap() rejected.\n"); 1138 return -1; 1139 } 1140 1141 if ((offset >= sc->sc_regaddr) && 1142 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1143 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1144 BUS_SPACE_MAP_LINEAR); 1145 } 1146 1147 if ((offset >= sc->sc_memaddr) && 1148 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1149 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1150 BUS_SPACE_MAP_LINEAR); 1151 } 1152 1153 if ((offset >= sc->sc_romaddr) && 1154 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1155 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1156 BUS_SPACE_MAP_LINEAR); 1157 } 1158 1159 #ifdef PCI_MAGIC_IO_RANGE 1160 /* allow mapping of IO space */ 1161 if ((offset >= PCI_MAGIC_IO_RANGE) && 1162 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1163 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1164 0, prot, 0); 1165 return pa; 1166 } 1167 #endif /* macppc */ 1168 1169 #endif /* RADEONFB_MMAP_BARS */ 1170 1171 return -1; 1172 } 1173 1174 static void 1175 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1176 { 1177 bus_space_tag_t romt; 1178 bus_space_handle_t romh, biosh; 1179 bus_size_t romsz; 1180 bus_addr_t ptr; 1181 1182 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1183 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1184 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1185 return; 1186 } 1187 1188 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1189 &sc->sc_biossz); 1190 if (sc->sc_biossz == 0) { 1191 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1192 return; 1193 } 1194 1195 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1196 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1197 1198 /* unmap the PCI expansion rom */ 1199 bus_space_unmap(romt, romh, romsz); 1200 1201 /* turn off rom decoder now */ 1202 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1203 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1204 ~PCI_MAPREG_ROM_ENABLE); 1205 1206 ptr = GETBIOS16(sc, 0x48); 1207 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1208 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1209 sc->sc_flags |= RFB_ATOM; 1210 } 1211 1212 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1213 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1214 } 1215 1216 1217 uint32_t 1218 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1219 { 1220 1221 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1222 } 1223 1224 void 1225 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1226 { 1227 1228 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1229 } 1230 1231 void 1232 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1233 uint32_t andmask, uint32_t ormask) 1234 { 1235 int s; 1236 uint32_t val; 1237 1238 s = splhigh(); 1239 val = radeonfb_get32(sc, reg); 1240 val = (val & andmask) | ormask; 1241 radeonfb_put32(sc, reg, val); 1242 splx(s); 1243 } 1244 1245 uint32_t 1246 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1247 { 1248 int s; 1249 uint32_t val; 1250 1251 s = splhigh(); 1252 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1253 val = radeonfb_get32(sc, RADEON_MM_DATA); 1254 splx(s); 1255 1256 return (val); 1257 } 1258 1259 void 1260 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1261 { 1262 int s; 1263 1264 s = splhigh(); 1265 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1266 radeonfb_put32(sc, RADEON_MM_DATA, val); 1267 splx(s); 1268 } 1269 1270 void 1271 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1272 uint32_t andmask, uint32_t ormask) 1273 { 1274 int s; 1275 uint32_t val; 1276 1277 s = splhigh(); 1278 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1279 val = radeonfb_get32(sc, RADEON_MM_DATA); 1280 val = (val & andmask) | ormask; 1281 radeonfb_put32(sc, RADEON_MM_DATA, val); 1282 splx(s); 1283 } 1284 1285 uint32_t 1286 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1287 { 1288 int s; 1289 uint32_t val; 1290 1291 s = splhigh(); 1292 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1293 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1294 if (HAS_R300CG(sc)) 1295 radeonfb_r300cg_workaround(sc); 1296 splx(s); 1297 1298 return (val); 1299 } 1300 1301 void 1302 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1303 { 1304 int s; 1305 1306 s = splhigh(); 1307 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1308 RADEON_PLL_WR_EN); 1309 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1310 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1311 splx(s); 1312 } 1313 1314 void 1315 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1316 uint32_t andmask, uint32_t ormask) 1317 { 1318 int s; 1319 uint32_t val; 1320 1321 s = splhigh(); 1322 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1323 RADEON_PLL_WR_EN); 1324 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1325 val = (val & andmask) | ormask; 1326 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1327 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1328 splx(s); 1329 } 1330 1331 int 1332 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1333 { 1334 uint32_t saved; 1335 1336 saved = GET32(sc, reg); 1337 PUT32(sc, reg, v); 1338 if (GET32(sc, reg) != v) { 1339 return -1; 1340 } 1341 PUT32(sc, reg, saved); 1342 return 0; 1343 } 1344 1345 uintmax_t 1346 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1347 uintmax_t defval) 1348 { 1349 prop_number_t pn; 1350 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1351 if (pn == NULL) { 1352 return defval; 1353 } 1354 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1355 return (prop_number_integer_value(pn)); 1356 } 1357 1358 int 1359 radeonfb_getclocks(struct radeonfb_softc *sc) 1360 { 1361 bus_addr_t ptr; 1362 int refclk = 0; 1363 int refdiv = 0; 1364 int minpll = 0; 1365 int maxpll = 0; 1366 1367 /* load initial property values if port/board provides them */ 1368 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1369 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1370 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1371 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1372 1373 if (refclk && refdiv && minpll && maxpll) 1374 goto dontprobe; 1375 1376 if (!sc->sc_biossz) { 1377 /* no BIOS */ 1378 aprint_verbose("%s: No video BIOS, using default clocks\n", 1379 XNAME(sc)); 1380 if (IS_IGP(sc)) 1381 refclk = refclk ? refclk : 1432; 1382 else 1383 refclk = refclk ? refclk : 2700; 1384 refdiv = refdiv ? refdiv : 12; 1385 minpll = minpll ? minpll : 12500; 1386 maxpll = maxpll ? maxpll : 35000; 1387 } else if (IS_ATOM(sc)) { 1388 /* ATOM BIOS */ 1389 ptr = GETBIOS16(sc, 0x48); 1390 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1391 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1392 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1393 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1394 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1395 /* 1396 * ATOM BIOS doesn't supply a reference divider, so we 1397 * have to probe for it. 1398 */ 1399 if (refdiv < 2) 1400 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1401 RADEON_PPLL_REF_DIV_MASK; 1402 /* 1403 * if probe is zero, just assume one that should work 1404 * for most parts 1405 */ 1406 if (refdiv < 2) 1407 refdiv = 12; 1408 1409 } else { 1410 /* Legacy BIOS */ 1411 ptr = GETBIOS16(sc, 0x48); 1412 ptr = GETBIOS16(sc, ptr + 0x30); 1413 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1414 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1415 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1416 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1417 } 1418 1419 1420 dontprobe: 1421 sc->sc_refclk = refclk * 10; 1422 sc->sc_refdiv = refdiv; 1423 sc->sc_minpll = minpll * 10; 1424 sc->sc_maxpll = maxpll * 10; 1425 return 0; 1426 } 1427 1428 int 1429 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1430 uint32_t *postdivbit, uint32_t *feedbackdiv) 1431 { 1432 int i; 1433 uint32_t outfreq; 1434 int div; 1435 1436 DPRINTF(("dot clock: %u\n", dotclock)); 1437 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1438 outfreq = div * dotclock; 1439 if ((outfreq >= sc->sc_minpll) && 1440 (outfreq <= sc->sc_maxpll)) { 1441 DPRINTF(("outfreq: %u\n", outfreq)); 1442 *postdivbit = 1443 ((uint32_t)radeonfb_dividers[i].mask << 16); 1444 DPRINTF(("post divider: %d (mask %x)\n", div, 1445 *postdivbit)); 1446 break; 1447 } 1448 } 1449 1450 if (div == 0) 1451 return 1; 1452 1453 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1454 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1455 return 0; 1456 } 1457 1458 #if 0 1459 #ifdef RADEONFB_DEBUG 1460 static void 1461 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1462 { 1463 char asc[17]; 1464 unsigned ptr = (unsigned)buffer; 1465 char *start = (char *)(ptr & ~0xf); 1466 char *end = (char *)(ptr + size); 1467 1468 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1469 1470 if (pfx == NULL) { 1471 pfx = ""; 1472 } 1473 1474 while (start < end) { 1475 unsigned offset = (unsigned)start & 0xf; 1476 if (offset == 0) { 1477 printf("%s%x: ", pfx, (unsigned)start); 1478 } 1479 if (((unsigned)start < ptr) || 1480 ((unsigned)start >= (ptr + size))) { 1481 printf(" "); 1482 asc[offset] = ' '; 1483 } else { 1484 printf("%02x", *(unsigned char *)start); 1485 if ((*start >= ' ') && (*start <= '~')) { 1486 asc[offset] = *start; 1487 } else { 1488 asc[offset] = '.'; 1489 } 1490 } 1491 asc[offset + 1] = 0; 1492 if (offset % 2) { 1493 printf(" "); 1494 } 1495 if (offset == 15) { 1496 printf(" %s\n", asc); 1497 } 1498 start++; 1499 } 1500 } 1501 #endif 1502 #endif 1503 1504 int 1505 radeonfb_getconnectors(struct radeonfb_softc *sc) 1506 { 1507 int i; 1508 int found = 0; 1509 1510 for (i = 0; i < 2; i++) { 1511 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1512 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1513 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1514 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1515 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1516 } 1517 1518 /* 1519 * This logic is borrowed from Xorg's radeon driver. 1520 */ 1521 if (!sc->sc_biossz) 1522 goto nobios; 1523 1524 if (IS_ATOM(sc)) { 1525 /* not done yet */ 1526 } else { 1527 uint16_t ptr; 1528 int port = 0; 1529 1530 ptr = GETBIOS16(sc, 0x48); 1531 ptr = GETBIOS16(sc, ptr + 0x50); 1532 for (i = 1; i < 4; i++) { 1533 uint16_t entry; 1534 uint8_t conn, ddc, dac, tmds; 1535 1536 /* 1537 * Parse the connector table. From reading the code, 1538 * it appears to made up of 16-bit entries for each 1539 * connector. The 16-bits are defined as: 1540 * 1541 * bits 12-15 - connector type (0 == end of table) 1542 * bits 8-11 - DDC type 1543 * bits 5-7 - ??? 1544 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1545 * bits 1-3 - ??? 1546 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1547 */ 1548 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1549 break; 1550 entry = GETBIOS16(sc, ptr + i * 2); 1551 1552 conn = (entry >> 12) & 0xf; 1553 ddc = (entry >> 8) & 0xf; 1554 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1555 RADEON_DAC_PRIMARY; 1556 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1557 RADEON_TMDS_INT; 1558 1559 if (conn == RADEON_CONN_NONE) 1560 continue; /* no connector */ 1561 1562 if ((found > 0) && 1563 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1564 /* duplicate entry for same connector */ 1565 continue; 1566 } 1567 1568 /* internal DDC_DVI port gets priority */ 1569 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1570 port = 0; 1571 else 1572 port = 1; 1573 1574 sc->sc_ports[port].rp_ddc_type = 1575 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1576 sc->sc_ports[port].rp_dac_type = dac; 1577 sc->sc_ports[port].rp_conn_type = 1578 min(conn, RADEON_CONN_UNSUPPORTED) ; 1579 1580 sc->sc_ports[port].rp_tmds_type = tmds; 1581 1582 if ((conn != RADEON_CONN_DVI_I) && 1583 (conn != RADEON_CONN_DVI_D) && 1584 (tmds == RADEON_TMDS_INT)) 1585 sc->sc_ports[port].rp_tmds_type = 1586 RADEON_TMDS_UNKNOWN; 1587 1588 found += (port + 1); 1589 } 1590 } 1591 1592 nobios: 1593 if (!found) { 1594 DPRINTF(("No connector info in BIOS!\n")); 1595 /* default, port 0 = internal TMDS, port 1 = CRT */ 1596 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1597 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1598 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1599 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1600 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1601 1602 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1603 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1604 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1605 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1606 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1607 } 1608 1609 /* 1610 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1611 * these chips should use TVDAC for the VGA port. 1612 */ 1613 if (HAS_SDAC(sc)) { 1614 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1615 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1616 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1617 } else { 1618 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1619 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1620 } 1621 } else if (!HAS_CRTC2(sc)) { 1622 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1623 } 1624 1625 for (i = 0; i < 2; i++) { 1626 char edid[128]; 1627 uint8_t ddc; 1628 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1629 prop_data_t edid_data; 1630 1631 DPRINTF(("Port #%d:\n", i)); 1632 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1633 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1634 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1635 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1636 1637 sc->sc_ports[i].rp_edid_valid = 0; 1638 /* first look for static EDID data */ 1639 if ((edid_data = prop_dictionary_get(device_properties( 1640 &sc->sc_dev), "EDID")) != NULL) { 1641 1642 aprint_normal_dev(&sc->sc_dev, "using static EDID\n"); 1643 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1644 if (edid_parse(edid, eip) == 0) { 1645 1646 sc->sc_ports[i].rp_edid_valid = 1; 1647 } 1648 } 1649 /* if we didn't find any we'll try to talk to the monitor */ 1650 if (sc->sc_ports[i].rp_edid_valid != 1) { 1651 1652 ddc = sc->sc_ports[i].rp_ddc_type; 1653 if (ddc != RADEON_DDC_NONE) { 1654 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1655 == 0) && (edid_parse(edid, eip) == 0)) { 1656 1657 sc->sc_ports[i].rp_edid_valid = 1; 1658 edid_print(eip); 1659 } 1660 } 1661 } 1662 } 1663 1664 return found; 1665 } 1666 1667 int 1668 radeonfb_gettmds(struct radeonfb_softc *sc) 1669 { 1670 int i; 1671 1672 if (!sc->sc_biossz) { 1673 goto nobios; 1674 } 1675 1676 if (IS_ATOM(sc)) { 1677 /* XXX: not done yet */ 1678 } else { 1679 uint16_t ptr; 1680 int n; 1681 1682 ptr = GETBIOS16(sc, 0x48); 1683 ptr = GETBIOS16(sc, ptr + 0x34); 1684 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1685 if (GETBIOS8(sc, ptr) == 3) { 1686 /* revision three table */ 1687 n = GETBIOS8(sc, ptr + 5) + 1; 1688 n = min(n, 4); 1689 1690 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1691 for (i = 0; i < n; i++) { 1692 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1693 ptr + i * 10 + 8); 1694 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1695 ptr + i * 10 + 0x10); 1696 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1697 sc->sc_tmds_pll[i].rtp_freq, 1698 sc->sc_tmds_pll[i].rtp_pll)); 1699 } 1700 return 0; 1701 } 1702 } 1703 1704 nobios: 1705 DPRINTF(("no suitable DFP table present\n")); 1706 for (i = 0; 1707 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1708 i++) { 1709 int j; 1710 1711 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1712 continue; 1713 1714 for (j = 0; j < 4; j++) { 1715 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1716 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1717 sc->sc_tmds_pll[j].rtp_freq, 1718 sc->sc_tmds_pll[j].rtp_pll)); 1719 } 1720 return 0; 1721 } 1722 1723 return -1; 1724 } 1725 1726 const struct videomode * 1727 radeonfb_modelookup(const char *name) 1728 { 1729 int i; 1730 1731 for (i = 0; i < videomode_count; i++) 1732 if (!strcmp(name, videomode_list[i].name)) 1733 return &videomode_list[i]; 1734 1735 return NULL; 1736 } 1737 1738 void 1739 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1740 { 1741 if (crtc) { 1742 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1743 RADEON_P2PLL_ATOMIC_UPDATE_R); 1744 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1745 } else { 1746 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1747 RADEON_PPLL_ATOMIC_UPDATE_R); 1748 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1749 } 1750 } 1751 1752 void 1753 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1754 { 1755 int i; 1756 1757 for (i = 10000; i; i--) { 1758 if (crtc) { 1759 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1760 RADEON_P2PLL_ATOMIC_UPDATE_R) 1761 break; 1762 } else { 1763 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1764 RADEON_PPLL_ATOMIC_UPDATE_R) 1765 break; 1766 } 1767 } 1768 } 1769 1770 void 1771 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1772 { 1773 uint32_t pbit = 0; 1774 uint32_t feed = 0; 1775 uint32_t data; 1776 #if 1 1777 int i; 1778 #endif 1779 1780 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1781 1782 if (crtc == 0) { 1783 1784 /* XXXX: mobility workaround missing */ 1785 /* XXXX: R300 stuff missing */ 1786 1787 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1788 RADEON_VCLK_SRC_SEL_CPUCLK, 1789 ~RADEON_VCLK_SRC_SEL_MASK); 1790 1791 /* put vclk into reset, use atomic updates */ 1792 SETPLL(sc, RADEON_PPLL_CNTL, 1793 RADEON_PPLL_REFCLK_SEL | 1794 RADEON_PPLL_FBCLK_SEL | 1795 RADEON_PPLL_RESET | 1796 RADEON_PPLL_ATOMIC_UPDATE_EN | 1797 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1798 1799 /* select clock 3 */ 1800 #if 0 1801 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1802 ~RADEON_PLL_DIV_SEL); 1803 #else 1804 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1805 ~RADEON_PLL_DIV_SEL); 1806 #endif 1807 1808 /* XXX: R300 family -- program divider differently? */ 1809 1810 /* program reference divider */ 1811 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1812 ~RADEON_PPLL_REF_DIV_MASK); 1813 PRINTPLL(RADEON_PPLL_REF_DIV); 1814 1815 #if 0 1816 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1817 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1818 RADEON_PPLL_POST3_DIV_MASK); 1819 data |= pbit; 1820 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1821 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1822 #else 1823 for (i = 0; i < 4; i++) { 1824 } 1825 #endif 1826 1827 /* use the atomic update */ 1828 radeonfb_pllwriteupdate(sc, crtc); 1829 1830 /* and wait for it to complete */ 1831 radeonfb_pllwaitatomicread(sc, crtc); 1832 1833 /* program HTOTAL (why?) */ 1834 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1835 1836 /* drop reset */ 1837 CLRPLL(sc, RADEON_PPLL_CNTL, 1838 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1839 RADEON_PPLL_ATOMIC_UPDATE_EN | 1840 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1841 1842 PRINTPLL(RADEON_PPLL_CNTL); 1843 1844 /* give clock time to lock */ 1845 delay(50000); 1846 1847 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1848 RADEON_VCLK_SRC_SEL_PPLLCLK, 1849 ~RADEON_VCLK_SRC_SEL_MASK); 1850 1851 } else { 1852 1853 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1854 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1855 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1856 1857 /* put vclk into reset, use atomic updates */ 1858 SETPLL(sc, RADEON_P2PLL_CNTL, 1859 RADEON_P2PLL_RESET | 1860 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1861 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1862 1863 /* XXX: R300 family -- program divider differently? */ 1864 1865 /* program reference divider */ 1866 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1867 ~RADEON_P2PLL_REF_DIV_MASK); 1868 1869 /* program feedback and post dividers */ 1870 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1871 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1872 RADEON_P2PLL_POST0_DIV_MASK); 1873 data |= pbit; 1874 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1875 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1876 1877 /* use the atomic update */ 1878 radeonfb_pllwriteupdate(sc, crtc); 1879 1880 /* and wait for it to complete */ 1881 radeonfb_pllwaitatomicread(sc, crtc); 1882 1883 /* program HTOTAL (why?) */ 1884 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1885 1886 /* drop reset */ 1887 CLRPLL(sc, RADEON_P2PLL_CNTL, 1888 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1889 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1890 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1891 1892 /* allow time for clock to lock */ 1893 delay(50000); 1894 1895 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1896 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1897 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1898 } 1899 PRINTREG(RADEON_CRTC_MORE_CNTL); 1900 } 1901 1902 void 1903 radeonfb_modeswitch(struct radeonfb_display *dp) 1904 { 1905 struct radeonfb_softc *sc = dp->rd_softc; 1906 int i; 1907 1908 /* blank the display while we switch modes */ 1909 radeonfb_blank(dp, 1); 1910 1911 #if 0 1912 SET32(sc, RADEON_CRTC_EXT_CNTL, 1913 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1914 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1915 #endif 1916 1917 /* these registers might get in the way... */ 1918 PUT32(sc, RADEON_OVR_CLR, 0); 1919 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1920 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1921 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1922 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1923 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1924 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1925 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1926 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1927 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1928 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1929 1930 for (i = 0; i < dp->rd_ncrtcs; i++) 1931 radeonfb_setcrtc(dp, i); 1932 1933 /* activate the display */ 1934 radeonfb_blank(dp, 0); 1935 } 1936 1937 void 1938 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1939 { 1940 int crtc; 1941 struct videomode *mode; 1942 struct radeonfb_softc *sc; 1943 struct radeonfb_crtc *cp; 1944 uint32_t v; 1945 uint32_t gencntl; 1946 uint32_t htotaldisp; 1947 uint32_t hsyncstrt; 1948 uint32_t vtotaldisp; 1949 uint32_t vsyncstrt; 1950 uint32_t fphsyncstrt; 1951 uint32_t fpvsyncstrt; 1952 uint32_t fphtotaldisp; 1953 uint32_t fpvtotaldisp; 1954 uint32_t pitch; 1955 1956 sc = dp->rd_softc; 1957 cp = &dp->rd_crtcs[index]; 1958 crtc = cp->rc_number; 1959 mode = &cp->rc_videomode; 1960 1961 #if 1 1962 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1963 (dp->rd_bpp * 8)); 1964 #else 1965 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1966 (sc->sc_maxbpp * 8)); 1967 #endif 1968 //pitch = pitch | (pitch << 16); 1969 1970 switch (crtc) { 1971 case 0: 1972 gencntl = RADEON_CRTC_GEN_CNTL; 1973 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1974 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1975 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1976 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1977 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1978 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1979 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1980 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1981 break; 1982 case 1: 1983 gencntl = RADEON_CRTC2_GEN_CNTL; 1984 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1985 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1986 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1987 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1988 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1989 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1990 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1991 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1992 break; 1993 default: 1994 panic("Bad CRTC!"); 1995 break; 1996 } 1997 1998 /* 1999 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2000 */ 2001 /* only bother with 32bpp and 8bpp */ 2002 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2003 2004 if (crtc == 1) { 2005 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2006 } else { 2007 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2008 } 2009 2010 if (mode->flags & VID_DBLSCAN) 2011 v |= RADEON_CRTC2_DBL_SCAN_EN; 2012 2013 if (mode->flags & VID_INTERLACE) 2014 v |= RADEON_CRTC2_INTERLACE_EN; 2015 2016 if (mode->flags & VID_CSYNC) { 2017 v |= RADEON_CRTC2_CSYNC_EN; 2018 if (crtc == 1) 2019 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2020 } 2021 2022 PUT32(sc, gencntl, v); 2023 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2024 2025 /* 2026 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2027 */ 2028 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2029 if (crtc == 0) { 2030 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2031 RADEON_CRTC_DISPLAY_DIS); 2032 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2033 if (mode->flags & VID_CSYNC) 2034 v |= RADEON_CRTC_VSYNC_TRISTAT; 2035 } 2036 /* unconditional turn on CRT, in case first CRTC is DFP */ 2037 v |= RADEON_CRTC_CRT_ON; 2038 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2039 PRINTREG(RADEON_CRTC_EXT_CNTL); 2040 2041 /* 2042 * H_TOTAL_DISP 2043 */ 2044 v = ((mode->hdisplay / 8) - 1) << 16; 2045 v |= (mode->htotal / 8) - 1; 2046 PUT32(sc, htotaldisp, v); 2047 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2048 PUT32(sc, fphtotaldisp, v); 2049 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2050 2051 /* 2052 * H_SYNC_STRT_WID 2053 */ 2054 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2055 v |= mode->hsync_start; 2056 if (mode->flags & VID_NHSYNC) 2057 v |= RADEON_CRTC_H_SYNC_POL; 2058 PUT32(sc, hsyncstrt, v); 2059 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2060 PUT32(sc, fphsyncstrt, v); 2061 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2062 2063 /* 2064 * V_TOTAL_DISP 2065 */ 2066 v = ((mode->vdisplay - 1) << 16); 2067 v |= (mode->vtotal - 1); 2068 PUT32(sc, vtotaldisp, v); 2069 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2070 PUT32(sc, fpvtotaldisp, v); 2071 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2072 2073 /* 2074 * V_SYNC_STRT_WID 2075 */ 2076 v = ((mode->vsync_end - mode->vsync_start) << 16); 2077 v |= (mode->vsync_start - 1); 2078 if (mode->flags & VID_NVSYNC) 2079 v |= RADEON_CRTC_V_SYNC_POL; 2080 PUT32(sc, vsyncstrt, v); 2081 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2082 PUT32(sc, fpvsyncstrt, v); 2083 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2084 2085 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2086 2087 switch (crtc) { 2088 case 0: 2089 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2090 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2091 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2092 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2093 2094 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2095 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2096 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2097 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2098 PRINTREG(RADEON_CRTC_EXT_CNTL); 2099 PRINTREG(RADEON_CRTC_GEN_CNTL); 2100 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2101 break; 2102 2103 case 1: 2104 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2105 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2106 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2107 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2108 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2109 RADEON_CRTC2_VSYNC_DIS | 2110 RADEON_CRTC2_HSYNC_DIS | 2111 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2112 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2113 break; 2114 } 2115 } 2116 2117 int 2118 radeonfb_isblank(struct radeonfb_display *dp) 2119 { 2120 uint32_t reg, mask; 2121 2122 if (dp->rd_crtcs[0].rc_number) { 2123 reg = RADEON_CRTC2_GEN_CNTL; 2124 mask = RADEON_CRTC2_DISP_DIS; 2125 } else { 2126 reg = RADEON_CRTC_EXT_CNTL; 2127 mask = RADEON_CRTC_DISPLAY_DIS; 2128 } 2129 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2130 } 2131 2132 void 2133 radeonfb_blank(struct radeonfb_display *dp, int blank) 2134 { 2135 struct radeonfb_softc *sc = dp->rd_softc; 2136 uint32_t reg, mask; 2137 uint32_t fpreg, fpval; 2138 int i; 2139 2140 for (i = 0; i < dp->rd_ncrtcs; i++) { 2141 2142 if (dp->rd_crtcs[i].rc_number) { 2143 reg = RADEON_CRTC2_GEN_CNTL; 2144 mask = RADEON_CRTC2_DISP_DIS; 2145 fpreg = RADEON_FP2_GEN_CNTL; 2146 fpval = RADEON_FP2_ON; 2147 } else { 2148 reg = RADEON_CRTC_EXT_CNTL; 2149 mask = RADEON_CRTC_DISPLAY_DIS; 2150 fpreg = RADEON_FP_GEN_CNTL; 2151 fpval = RADEON_FP_FPON; 2152 } 2153 2154 if (blank) { 2155 SET32(sc, reg, mask); 2156 CLR32(sc, fpreg, fpval); 2157 } else { 2158 CLR32(sc, reg, mask); 2159 SET32(sc, fpreg, fpval); 2160 } 2161 } 2162 PRINTREG(RADEON_FP_GEN_CNTL); 2163 PRINTREG(RADEON_FP2_GEN_CNTL); 2164 } 2165 2166 void 2167 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2168 long *defattr) 2169 { 2170 struct radeonfb_display *dp = cookie; 2171 struct rasops_info *ri = &scr->scr_ri; 2172 2173 /* initialize font subsystem */ 2174 wsfont_init(); 2175 2176 DPRINTF(("init screen called, existing %d\n", existing)); 2177 2178 ri->ri_depth = dp->rd_bpp; 2179 ri->ri_width = dp->rd_virtx; 2180 ri->ri_height = dp->rd_virty; 2181 ri->ri_stride = dp->rd_stride; 2182 ri->ri_flg = RI_CENTER; 2183 ri->ri_bits = (void *)dp->rd_fbptr; 2184 2185 /* XXX: 32 bpp only */ 2186 /* this is rgb in "big-endian order..." */ 2187 ri->ri_rnum = 8; 2188 ri->ri_gnum = 8; 2189 ri->ri_bnum = 8; 2190 ri->ri_rpos = 16; 2191 ri->ri_gpos = 8; 2192 ri->ri_bpos = 0; 2193 2194 if (existing) { 2195 ri->ri_flg |= RI_CLEAR; 2196 2197 /* start a modeswitch now */ 2198 radeonfb_modeswitch(dp); 2199 } 2200 2201 /* 2202 * XXX: font selection should be based on properties, with some 2203 * normal/reasonable default. 2204 */ 2205 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2206 2207 /* initialize and look for an initial font */ 2208 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2209 2210 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2211 dp->rd_virtx / ri->ri_font->fontwidth); 2212 2213 /* enable acceleration */ 2214 dp->rd_putchar = ri->ri_ops.putchar; 2215 ri->ri_ops.copyrows = radeonfb_copyrows; 2216 ri->ri_ops.copycols = radeonfb_copycols; 2217 ri->ri_ops.eraserows = radeonfb_eraserows; 2218 ri->ri_ops.erasecols = radeonfb_erasecols; 2219 ri->ri_ops.allocattr = radeonfb_allocattr; 2220 if (!IS_R300(dp->rd_softc)) { 2221 ri->ri_ops.putchar = radeonfb_putchar; 2222 } else { 2223 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2224 } 2225 ri->ri_ops.cursor = radeonfb_cursor; 2226 } 2227 2228 void 2229 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2230 { 2231 uint32_t gen, ext, gen2 = 0; 2232 uint32_t agploc, aperbase, apersize, mcfbloc; 2233 2234 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2235 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2236 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2237 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2238 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2239 2240 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2241 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2242 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2243 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2244 2245 if (HAS_CRTC2(sc)) { 2246 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2247 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2248 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2249 } 2250 2251 delay(100000); 2252 2253 mcfbloc = (aperbase >> 16) | 2254 ((aperbase + (apersize - 1)) & 0xffff0000); 2255 2256 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2257 sc->sc_memsz = apersize; 2258 2259 if (((agploc & 0xffff) << 16) != 2260 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2261 agploc = mcfbloc & 0xffff0000U; 2262 agploc |= ((agploc + 0x10000) >> 16); 2263 } 2264 2265 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2266 2267 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2268 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2269 2270 DPRINTF(("aperbase = %u\n", aperbase)); 2271 PRINTREG(RADEON_MC_FB_LOCATION); 2272 PRINTREG(RADEON_MC_AGP_LOCATION); 2273 2274 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2275 2276 if (HAS_CRTC2(sc)) 2277 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2278 2279 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2280 2281 #if 0 2282 /* XXX: what is this AGP garbage? :-) */ 2283 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2284 #endif 2285 2286 delay(100000); 2287 2288 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2289 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2290 2291 if (HAS_CRTC2(sc)) 2292 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2293 } 2294 2295 void 2296 radeonfb_init_misc(struct radeonfb_softc *sc) 2297 { 2298 PUT32(sc, RADEON_BUS_CNTL, 2299 RADEON_BUS_MASTER_DIS | 2300 RADEON_BUS_PREFETCH_MODE_ACT | 2301 RADEON_BUS_PCI_READ_RETRY_EN | 2302 RADEON_BUS_PCI_WRT_RETRY_EN | 2303 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2304 RADEON_BUS_MSTR_RD_MULT | 2305 RADEON_BUS_MSTR_RD_LINE | 2306 RADEON_BUS_RD_DISCARD_EN | 2307 RADEON_BUS_MSTR_DISCONNECT_EN | 2308 RADEON_BUS_READ_BURST); 2309 2310 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2311 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2312 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2313 PUT32(sc, RADEON_RBBM_CNTL, 2314 (3 << RADEON_RB_SETTLE_SHIFT) | 2315 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2316 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2317 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2318 2319 /* XXX: figure out what these mean! */ 2320 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2321 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2322 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2323 2324 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2325 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2326 } 2327 2328 /* 2329 * This loads a linear color map for true color. 2330 */ 2331 void 2332 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2333 { 2334 int i; 2335 uint32_t vclk; 2336 2337 #define DAC_WIDTH ((1 << 10) - 1) 2338 #define CLUT_WIDTH ((1 << 8) - 1) 2339 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2340 2341 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2342 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2343 2344 if (crtc) 2345 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2346 else 2347 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2348 2349 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2350 if (sc->sc_displays[crtc].rd_bpp == 0) 2351 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2352 2353 if (sc->sc_displays[crtc].rd_bpp == 8) { 2354 /* ANSI palette */ 2355 int j = 0; 2356 2357 for (i = 0; i <= CLUT_WIDTH; ++i) { 2358 PUT32(sc, RADEON_PALETTE_30_DATA, 2359 (rasops_cmap[j] << 22) | 2360 (rasops_cmap[j + 1] << 12) | 2361 (rasops_cmap[j + 2] << 2)); 2362 j += 3; 2363 } 2364 } else { 2365 /* linear ramp */ 2366 for (i = 0; i <= CLUT_WIDTH; ++i) { 2367 PUT32(sc, RADEON_PALETTE_30_DATA, 2368 (CLUT_COLOR(i) << 10) | 2369 (CLUT_COLOR(i) << 20) | 2370 (CLUT_COLOR(i))); 2371 } 2372 } 2373 2374 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2375 PRINTREG(RADEON_DAC_CNTL2); 2376 2377 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2378 } 2379 2380 /* 2381 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2382 */ 2383 void 2384 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2385 { 2386 uint32_t tmp, save; 2387 2388 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2389 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2390 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2391 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2392 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2393 } 2394 2395 /* 2396 * Acceleration entry points. 2397 */ 2398 static void 2399 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2400 { 2401 struct rasops_info *ri = cookie; 2402 struct vcons_screen *scr = ri->ri_hw; 2403 struct radeonfb_display *dp = scr->scr_cookie; 2404 struct wsdisplay_font *font = PICK_FONT(ri, c); 2405 uint32_t x, y, w, h; 2406 uint32_t bg, fg, flg; 2407 uint8_t *data; 2408 2409 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2410 return; 2411 2412 if (!CHAR_IN_FONT(c, font)) 2413 return; 2414 2415 w = font->fontwidth; 2416 h = font->fontheight; 2417 2418 flg = attr & 0xff; 2419 if (flg & WSATTR_REVERSE) { 2420 fg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2421 bg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2422 } else { 2423 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2424 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2425 } 2426 2427 x = ri->ri_xorigin + col * w; 2428 y = ri->ri_yorigin + row * h; 2429 2430 if (c == 0x20) { 2431 radeonfb_rectfill(dp, x, y, w, h, bg); 2432 } else { 2433 data = (uint8_t *)font->data + 2434 (c - font->firstchar) * ri->ri_fontscale; 2435 2436 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2437 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2438 } 2439 } 2440 2441 /* 2442 * wrapper for software character drawing 2443 * just sync the engine and call rasops*_putchar() 2444 */ 2445 2446 static void 2447 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2448 { 2449 struct rasops_info *ri = cookie; 2450 struct vcons_screen *scr = ri->ri_hw; 2451 struct radeonfb_display *dp = scr->scr_cookie; 2452 2453 radeonfb_engine_idle(dp->rd_softc); 2454 dp->rd_putchar(ri, row, col, c, attr); 2455 } 2456 2457 static void 2458 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2459 { 2460 struct rasops_info *ri = cookie; 2461 struct vcons_screen *scr = ri->ri_hw; 2462 struct radeonfb_display *dp = scr->scr_cookie; 2463 uint32_t x, y, w, h, fg, bg, ul; 2464 2465 /* XXX: check for full emulation mode? */ 2466 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2467 x = ri->ri_xorigin; 2468 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2469 w = ri->ri_emuwidth; 2470 h = ri->ri_font->fontheight * nrows; 2471 2472 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2473 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2474 } 2475 } 2476 2477 static void 2478 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2479 { 2480 struct rasops_info *ri = cookie; 2481 struct vcons_screen *scr = ri->ri_hw; 2482 struct radeonfb_display *dp = scr->scr_cookie; 2483 uint32_t x, ys, yd, w, h; 2484 2485 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2486 x = ri->ri_xorigin; 2487 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2488 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2489 w = ri->ri_emuwidth; 2490 h = ri->ri_font->fontheight * nrows; 2491 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2492 RADEON_ROP3_S, 0xffffffff); 2493 } 2494 } 2495 2496 static void 2497 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2498 { 2499 struct rasops_info *ri = cookie; 2500 struct vcons_screen *scr = ri->ri_hw; 2501 struct radeonfb_display *dp = scr->scr_cookie; 2502 uint32_t xs, xd, y, w, h; 2503 2504 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2505 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2506 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2507 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2508 w = ri->ri_font->fontwidth * ncols; 2509 h = ri->ri_font->fontheight; 2510 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2511 RADEON_ROP3_S, 0xffffffff); 2512 } 2513 } 2514 2515 static void 2516 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2517 long fillattr) 2518 { 2519 struct rasops_info *ri = cookie; 2520 struct vcons_screen *scr = ri->ri_hw; 2521 struct radeonfb_display *dp = scr->scr_cookie; 2522 uint32_t x, y, w, h, fg, bg, ul; 2523 2524 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2525 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2526 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2527 w = ri->ri_font->fontwidth * ncols; 2528 h = ri->ri_font->fontheight; 2529 2530 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2531 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2532 } 2533 } 2534 2535 static void 2536 radeonfb_cursor(void *cookie, int on, int row, int col) 2537 { 2538 struct rasops_info *ri = cookie; 2539 struct vcons_screen *scr = ri->ri_hw; 2540 struct radeonfb_display *dp = scr->scr_cookie; 2541 int x, y, wi, he; 2542 2543 wi = ri->ri_font->fontwidth; 2544 he = ri->ri_font->fontheight; 2545 2546 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2547 x = ri->ri_ccol * wi + ri->ri_xorigin; 2548 y = ri->ri_crow * he + ri->ri_yorigin; 2549 /* first turn off the old cursor */ 2550 if (ri->ri_flg & RI_CURSOR) { 2551 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2552 RADEON_ROP3_Dn, 0xffffffff); 2553 ri->ri_flg &= ~RI_CURSOR; 2554 } 2555 ri->ri_crow = row; 2556 ri->ri_ccol = col; 2557 /* then (possibly) turn on the new one */ 2558 if (on) { 2559 x = ri->ri_ccol * wi + ri->ri_xorigin; 2560 y = ri->ri_crow * he + ri->ri_yorigin; 2561 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2562 RADEON_ROP3_Dn, 0xffffffff); 2563 ri->ri_flg |= RI_CURSOR; 2564 } 2565 } else { 2566 scr->scr_ri.ri_crow = row; 2567 scr->scr_ri.ri_ccol = col; 2568 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2569 } 2570 } 2571 2572 static int 2573 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2574 { 2575 if ((fg == 0) && (bg == 0)) { 2576 fg = WS_DEFAULT_FG; 2577 bg = WS_DEFAULT_BG; 2578 } 2579 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2580 return 0; 2581 } 2582 2583 /* 2584 * Underlying acceleration support. 2585 */ 2586 static void 2587 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2588 int height, uint32_t fg, uint32_t bg) 2589 { 2590 struct radeonfb_softc *sc = dp->rd_softc; 2591 uint32_t gmc; 2592 uint32_t padded_width = (width+7) & 0xfff8; 2593 uint32_t topleft, bottomright; 2594 2595 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2596 2597 if (width != padded_width) { 2598 2599 radeonfb_wait_fifo(sc, 2); 2600 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2601 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2602 ((xd + width) & 0x1fff); 2603 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2604 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2605 } 2606 2607 radeonfb_wait_fifo(sc, 5); 2608 2609 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2610 RADEON_GMC_BRUSH_NONE | 2611 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2612 //RADEON_GMC_BYTE_LSB_TO_MSB | 2613 RADEON_GMC_DST_CLIPPING | 2614 RADEON_ROP3_S | 2615 RADEON_DP_SRC_SOURCE_HOST_DATA | 2616 RADEON_GMC_CLR_CMP_CNTL_DIS | 2617 RADEON_GMC_WR_MSK_DIS | 2618 gmc); 2619 2620 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2621 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2622 2623 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2624 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2625 2626 } 2627 2628 static void 2629 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2630 { 2631 struct radeonfb_softc *sc = dp->rd_softc; 2632 int i; 2633 uint32_t latch = 0; 2634 int shift = 0; 2635 2636 for (i = 0; i < count; i++) { 2637 latch |= (data[i] << shift); 2638 if (shift == 24) { 2639 radeonfb_wait_fifo(sc, 1); 2640 PUT32(sc, RADEON_HOST_DATA0, latch); 2641 latch = 0; 2642 shift = 0; 2643 } else 2644 shift += 8; 2645 } 2646 if (shift != 0) { 2647 radeonfb_wait_fifo(sc, 1); 2648 PUT32(sc, RADEON_HOST_DATA0, latch); 2649 } 2650 radeonfb_unclip(sc); 2651 } 2652 2653 static void 2654 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2655 int width, int height, uint32_t color) 2656 { 2657 struct radeonfb_softc *sc = dp->rd_softc; 2658 uint32_t gmc; 2659 2660 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2661 2662 radeonfb_wait_fifo(sc, 6); 2663 2664 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2665 RADEON_GMC_BRUSH_SOLID_COLOR | 2666 RADEON_GMC_SRC_DATATYPE_COLOR | 2667 RADEON_GMC_CLR_CMP_CNTL_DIS | 2668 RADEON_ROP3_P | gmc); 2669 2670 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2671 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2672 PUT32(sc, RADEON_DP_CNTL, 2673 RADEON_DST_X_LEFT_TO_RIGHT | 2674 RADEON_DST_Y_TOP_TO_BOTTOM); 2675 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2676 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2677 2678 /* 2679 * XXX: we don't wait for the fifo to empty -- that would slow 2680 * things down! The linux radeonfb driver waits, but xfree doesn't 2681 */ 2682 /* XXX: for now we do, to make it safe for direct drawing */ 2683 radeonfb_engine_idle(sc); 2684 } 2685 2686 static void 2687 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2688 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2689 { 2690 struct radeonfb_softc *sc = dp->rd_softc; 2691 uint32_t gmc; 2692 uint32_t dir; 2693 2694 if (dsty < srcy) { 2695 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2696 } else { 2697 srcy += height - 1; 2698 dsty += height - 1; 2699 dir = 0; 2700 } 2701 if (dstx < srcx) { 2702 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2703 } else { 2704 srcx += width - 1; 2705 dstx += width - 1; 2706 } 2707 2708 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2709 2710 radeonfb_wait_fifo(sc, 6); 2711 2712 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2713 //RADEON_GMC_SRC_CLIPPING | 2714 RADEON_GMC_BRUSH_SOLID_COLOR | 2715 RADEON_GMC_SRC_DATATYPE_COLOR | 2716 RADEON_GMC_CLR_CMP_CNTL_DIS | 2717 RADEON_DP_SRC_SOURCE_MEMORY | 2718 rop | gmc); 2719 2720 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2721 PUT32(sc, RADEON_DP_CNTL, dir); 2722 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2723 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2724 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2725 2726 /* 2727 * XXX: we don't wait for the fifo to empty -- that would slow 2728 * things down! The linux radeonfb driver waits, but xfree doesn't 2729 */ 2730 /* XXX: for now we do, to make it safe for direct drawing */ 2731 radeonfb_engine_idle(sc); 2732 } 2733 2734 static void 2735 radeonfb_engine_idle(struct radeonfb_softc *sc) 2736 { 2737 int i; 2738 2739 radeonfb_wait_fifo(sc, 64); 2740 for (i = RADEON_TIMEOUT; i; i--) { 2741 if ((GET32(sc, RADEON_RBBM_STATUS) & 2742 RADEON_RBBM_ACTIVE) == 0) { 2743 radeonfb_engine_flush(sc); 2744 break; 2745 } 2746 } 2747 } 2748 2749 static void 2750 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2751 { 2752 int i; 2753 2754 for (i = RADEON_TIMEOUT; i; i--) { 2755 if ((GET32(sc, RADEON_RBBM_STATUS) & 2756 RADEON_RBBM_FIFOCNT_MASK) >= n) 2757 return; 2758 } 2759 #ifdef DIAGNOSTIC 2760 if (!i) 2761 printf("%s: timed out waiting for fifo (%x)\n", 2762 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2763 #endif 2764 } 2765 2766 static void 2767 radeonfb_engine_flush(struct radeonfb_softc *sc) 2768 { 2769 int i; 2770 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2771 for (i = RADEON_TIMEOUT; i; i--) { 2772 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2773 RADEON_RB2D_DC_BUSY) == 0) 2774 break; 2775 } 2776 #ifdef DIAGNOSTIC 2777 if (!i) 2778 printf("%s: engine flush timed out!\n", XNAME(sc)); 2779 #endif 2780 } 2781 2782 static inline void 2783 radeonfb_unclip(struct radeonfb_softc *sc) 2784 { 2785 2786 radeonfb_wait_fifo(sc, 2); 2787 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2788 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2789 } 2790 2791 static void 2792 radeonfb_engine_init(struct radeonfb_display *dp) 2793 { 2794 struct radeonfb_softc *sc = dp->rd_softc; 2795 uint32_t pitch; 2796 volatile uint32_t junk; 2797 2798 /* no 3D */ 2799 PUT32(sc, RADEON_RB3D_CNTL, 0); 2800 2801 radeonfb_engine_reset(sc); 2802 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2803 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2804 2805 radeonfb_wait_fifo(sc, 1); 2806 if (!IS_R300(sc)) 2807 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2808 2809 radeonfb_wait_fifo(sc, 3); 2810 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2811 (pitch << 22) | (sc->sc_aperbase >> 10)); 2812 2813 2814 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2815 (pitch << 22) | (sc->sc_aperbase >> 10)); 2816 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2817 (pitch << 22) | (sc->sc_aperbase >> 10)); 2818 2819 radeonfb_wait_fifo(sc, 1); 2820 #if _BYTE_ORDER == _BIG_ENDIAN 2821 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2822 #else 2823 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2824 #endif 2825 junk = GET32(sc, RADEON_DP_DATATYPE); 2826 2827 /* default scissors -- no clipping */ 2828 radeonfb_wait_fifo(sc, 1); 2829 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2830 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2831 2832 radeonfb_wait_fifo(sc, 1); 2833 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2834 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2835 RADEON_GMC_CLR_CMP_CNTL_DIS | 2836 RADEON_GMC_BRUSH_SOLID_COLOR | 2837 RADEON_GMC_SRC_DATATYPE_COLOR); 2838 2839 radeonfb_wait_fifo(sc, 7); 2840 PUT32(sc, RADEON_DST_LINE_START, 0); 2841 PUT32(sc, RADEON_DST_LINE_END, 0); 2842 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2843 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2844 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2845 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2846 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2847 2848 radeonfb_engine_idle(sc); 2849 } 2850 2851 static void 2852 radeonfb_engine_reset(struct radeonfb_softc *sc) 2853 { 2854 uint32_t hpc, rbbm, mclkcntl, clkindex; 2855 2856 radeonfb_engine_flush(sc); 2857 2858 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2859 if (HAS_R300CG(sc)) 2860 radeonfb_r300cg_workaround(sc); 2861 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2862 2863 /* 2864 * According to comments in XFree code, resetting the HDP via 2865 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2866 * So we use HOST_PATH_CNTL instead. 2867 */ 2868 2869 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2870 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2871 if (IS_R300(sc)) { 2872 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2873 RADEON_SOFT_RESET_CP | 2874 RADEON_SOFT_RESET_HI | 2875 RADEON_SOFT_RESET_E2); 2876 GET32(sc, RADEON_RBBM_SOFT_RESET); 2877 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2878 /* 2879 * XXX: this bit is not defined in any ATI docs I have, 2880 * nor in the XFree code, but XFree does it. Why? 2881 */ 2882 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2883 } else { 2884 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2885 RADEON_SOFT_RESET_CP | 2886 RADEON_SOFT_RESET_SE | 2887 RADEON_SOFT_RESET_RE | 2888 RADEON_SOFT_RESET_PP | 2889 RADEON_SOFT_RESET_E2 | 2890 RADEON_SOFT_RESET_RB); 2891 GET32(sc, RADEON_RBBM_SOFT_RESET); 2892 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2893 ~(RADEON_SOFT_RESET_CP | 2894 RADEON_SOFT_RESET_SE | 2895 RADEON_SOFT_RESET_RE | 2896 RADEON_SOFT_RESET_PP | 2897 RADEON_SOFT_RESET_E2 | 2898 RADEON_SOFT_RESET_RB)); 2899 GET32(sc, RADEON_RBBM_SOFT_RESET); 2900 } 2901 2902 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2903 GET32(sc, RADEON_HOST_PATH_CNTL); 2904 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2905 2906 if (IS_R300(sc)) 2907 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2908 2909 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2910 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2911 2912 if (HAS_R300CG(sc)) 2913 radeonfb_r300cg_workaround(sc); 2914 } 2915 2916 static int 2917 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2918 { 2919 int x, y; 2920 2921 x = pos->x; 2922 y = pos->y; 2923 2924 /* 2925 * This doesn't let a cursor move off the screen. I'm not 2926 * sure if this will have negative effects for e.g. Xinerama. 2927 * I'd guess Xinerama handles it by changing the cursor shape, 2928 * but that needs verification. 2929 */ 2930 if (x >= dp->rd_virtx) 2931 x = dp->rd_virtx - 1; 2932 if (x < 0) 2933 x = 0; 2934 if (y >= dp->rd_virty) 2935 y = dp->rd_virty - 1; 2936 if (y < 0) 2937 y = 0; 2938 2939 dp->rd_cursor.rc_pos.x = x; 2940 dp->rd_cursor.rc_pos.y = y; 2941 2942 radeonfb_cursor_position(dp); 2943 return 0; 2944 } 2945 2946 static int 2947 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2948 { 2949 unsigned flags; 2950 2951 uint8_t r[2], g[2], b[2]; 2952 unsigned index, count; 2953 int i, err; 2954 int pitch, size; 2955 struct radeonfb_cursor nc; 2956 2957 flags = wc->which; 2958 2959 /* copy old values */ 2960 nc = dp->rd_cursor; 2961 2962 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2963 index = wc->cmap.index; 2964 count = wc->cmap.count; 2965 2966 if (index >= 2 || (index + count) > 2) 2967 return EINVAL; 2968 2969 err = copyin(wc->cmap.red, &r[index], count); 2970 if (err) 2971 return err; 2972 err = copyin(wc->cmap.green, &g[index], count); 2973 if (err) 2974 return err; 2975 err = copyin(wc->cmap.blue, &b[index], count); 2976 if (err) 2977 return err; 2978 2979 for (i = index; i < index + count; i++) { 2980 nc.rc_cmap[i] = 2981 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2982 } 2983 } 2984 2985 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2986 if ((wc->size.x > RADEON_CURSORMAXX) || 2987 (wc->size.y > RADEON_CURSORMAXY)) 2988 return EINVAL; 2989 2990 /* figure bytes per line */ 2991 pitch = (wc->size.x + 7) / 8; 2992 size = pitch * wc->size.y; 2993 2994 /* clear the old cursor and mask */ 2995 memset(nc.rc_image, 0, 512); 2996 memset(nc.rc_mask, 0, 512); 2997 2998 nc.rc_size = wc->size; 2999 3000 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3001 return err; 3002 3003 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3004 return err; 3005 } 3006 3007 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3008 nc.rc_hot = wc->hot; 3009 if (nc.rc_hot.x >= nc.rc_size.x) 3010 nc.rc_hot.x = nc.rc_size.x - 1; 3011 if (nc.rc_hot.y >= nc.rc_size.y) 3012 nc.rc_hot.y = nc.rc_size.y - 1; 3013 } 3014 3015 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3016 nc.rc_pos = wc->pos; 3017 if (nc.rc_pos.x >= dp->rd_virtx) 3018 nc.rc_pos.x = dp->rd_virtx - 1; 3019 #if 0 3020 if (nc.rc_pos.x < 0) 3021 nc.rc_pos.x = 0; 3022 #endif 3023 if (nc.rc_pos.y >= dp->rd_virty) 3024 nc.rc_pos.y = dp->rd_virty - 1; 3025 #if 0 3026 if (nc.rc_pos.y < 0) 3027 nc.rc_pos.y = 0; 3028 #endif 3029 } 3030 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3031 nc.rc_visible = wc->enable; 3032 } 3033 3034 dp->rd_cursor = nc; 3035 radeonfb_cursor_update(dp, wc->which); 3036 3037 return 0; 3038 } 3039 3040 /* 3041 * Change the cursor shape. Call this with the cursor locked to avoid 3042 * flickering/tearing. 3043 */ 3044 static void 3045 radeonfb_cursor_shape(struct radeonfb_display *dp) 3046 { 3047 uint8_t and[512], xor[512]; 3048 int i, j, src, dst, pitch; 3049 const uint8_t *msk = dp->rd_cursor.rc_mask; 3050 const uint8_t *img = dp->rd_cursor.rc_image; 3051 3052 /* 3053 * Radeon cursor data interleaves one line of AND data followed 3054 * by a line of XOR data. (Each line corresponds to a whole hardware 3055 * pitch - i.e. 64 pixels or 8 bytes.) 3056 * 3057 * The cursor is displayed using the following table: 3058 * 3059 * AND XOR Result 3060 * ---------------------- 3061 * 0 0 Cursor color 0 3062 * 0 1 Cursor color 1 3063 * 1 0 Transparent 3064 * 1 1 Complement of background 3065 * 3066 * Our masks are therefore different from what we were passed. 3067 * Passed in, I'm assuming the data represents either color 0 or 1, 3068 * and a mask, so the passed in table looks like: 3069 * 3070 * IMG Mask Result 3071 * ----------------------- 3072 * 0 0 Transparent 3073 * 0 1 Cursor color 0 3074 * 1 0 Transparent 3075 * 1 1 Cursor color 1 3076 * 3077 * IF mask bit == 1, AND = 0, XOR = color. 3078 * IF mask bit == 0, AND = 1, XOR = 0. 3079 * 3080 * hence: AND = ~(mask); XOR = color & ~(mask); 3081 */ 3082 3083 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3084 3085 /* start by assuming all bits are transparent */ 3086 memset(and, 0xff, 512); 3087 memset(xor, 0x00, 512); 3088 3089 src = 0; 3090 dst = 0; 3091 for (i = 0; i < 64; i++) { 3092 for (j = 0; j < 64; j += 8) { 3093 if ((i < dp->rd_cursor.rc_size.y) && 3094 (j < dp->rd_cursor.rc_size.x)) { 3095 3096 /* take care to leave odd bits alone */ 3097 and[dst] &= ~(msk[src]); 3098 xor[dst] = img[src] & msk[src]; 3099 src++; 3100 } 3101 dst++; 3102 } 3103 } 3104 3105 /* copy the image into place */ 3106 for (i = 0; i < 64; i++) { 3107 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3108 &and[i * 8], 8); 3109 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3110 &xor[i * 8], 8); 3111 } 3112 } 3113 3114 static void 3115 radeonfb_cursor_position(struct radeonfb_display *dp) 3116 { 3117 struct radeonfb_softc *sc = dp->rd_softc; 3118 uint32_t offset, hvoff, hvpos; /* registers */ 3119 uint32_t coff; /* cursor offset */ 3120 int i, x, y, xoff, yoff, crtcoff; 3121 3122 /* 3123 * XXX: this also needs to handle pan/scan 3124 */ 3125 for (i = 0; i < dp->rd_ncrtcs; i++) { 3126 3127 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3128 3129 if (rcp->rc_number) { 3130 offset = RADEON_CUR2_OFFSET; 3131 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3132 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3133 crtcoff = RADEON_CRTC2_OFFSET; 3134 } else { 3135 offset = RADEON_CUR_OFFSET; 3136 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3137 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3138 crtcoff = RADEON_CRTC_OFFSET; 3139 } 3140 3141 x = dp->rd_cursor.rc_pos.x; 3142 y = dp->rd_cursor.rc_pos.y; 3143 3144 while (y < rcp->rc_yoffset) { 3145 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3146 } 3147 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3148 rcp->rc_yoffset += RADEON_PANINCREMENT; 3149 } 3150 while (x < rcp->rc_xoffset) { 3151 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3152 } 3153 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3154 rcp->rc_xoffset += RADEON_PANINCREMENT; 3155 } 3156 3157 /* adjust for the cursor's hotspot */ 3158 x -= dp->rd_cursor.rc_hot.x; 3159 y -= dp->rd_cursor.rc_hot.y; 3160 xoff = yoff = 0; 3161 3162 if (x >= dp->rd_virtx) 3163 x = dp->rd_virtx - 1; 3164 if (y >= dp->rd_virty) 3165 y = dp->rd_virty - 1; 3166 3167 /* now adjust cursor so it is relative to viewport */ 3168 x -= rcp->rc_xoffset; 3169 y -= rcp->rc_yoffset; 3170 3171 /* 3172 * no need to check for fall off, because we should 3173 * never move off the screen entirely! 3174 */ 3175 coff = 0; 3176 if (x < 0) { 3177 xoff = -x; 3178 x = 0; 3179 } 3180 if (y < 0) { 3181 yoff = -y; 3182 y = 0; 3183 coff = (yoff * 2) * 8; 3184 } 3185 3186 /* pan the display */ 3187 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3188 rcp->rc_xoffset); 3189 3190 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3191 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3192 /* NB: this unlocks the cursor */ 3193 PUT32(sc, hvpos, (x << 16) | y); 3194 } 3195 } 3196 3197 static void 3198 radeonfb_cursor_visible(struct radeonfb_display *dp) 3199 { 3200 int i; 3201 uint32_t gencntl, bit; 3202 3203 for (i = 0; i < dp->rd_ncrtcs; i++) { 3204 if (dp->rd_crtcs[i].rc_number) { 3205 gencntl = RADEON_CRTC2_GEN_CNTL; 3206 bit = RADEON_CRTC2_CUR_EN; 3207 } else { 3208 gencntl = RADEON_CRTC_GEN_CNTL; 3209 bit = RADEON_CRTC_CUR_EN; 3210 } 3211 3212 if (dp->rd_cursor.rc_visible) 3213 SET32(dp->rd_softc, gencntl, bit); 3214 else 3215 CLR32(dp->rd_softc, gencntl, bit); 3216 } 3217 } 3218 3219 static void 3220 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3221 { 3222 int i; 3223 uint32_t c0reg, c1reg; 3224 struct radeonfb_softc *sc = dp->rd_softc; 3225 3226 for (i = 0; i < dp->rd_ncrtcs; i++) { 3227 if (dp->rd_crtcs[i].rc_number) { 3228 c0reg = RADEON_CUR2_CLR0; 3229 c1reg = RADEON_CUR2_CLR1; 3230 } else { 3231 c0reg = RADEON_CUR_CLR0; 3232 c1reg = RADEON_CUR_CLR1; 3233 } 3234 3235 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3236 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3237 } 3238 } 3239 3240 static void 3241 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3242 { 3243 struct radeonfb_softc *sc; 3244 int i; 3245 3246 sc = dp->rd_softc; 3247 for (i = 0; i < dp->rd_ncrtcs; i++) { 3248 if (dp->rd_crtcs[i].rc_number) { 3249 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3250 } else { 3251 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3252 } 3253 } 3254 3255 if (which & WSDISPLAY_CURSOR_DOCMAP) 3256 radeonfb_cursor_cmap(dp); 3257 3258 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3259 radeonfb_cursor_shape(dp); 3260 3261 if (which & WSDISPLAY_CURSOR_DOCUR) 3262 radeonfb_cursor_visible(dp); 3263 3264 /* this one is unconditional, because it updates other stuff */ 3265 radeonfb_cursor_position(dp); 3266 } 3267 3268 static struct videomode * 3269 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3270 { 3271 int r1, r2; 3272 3273 /* otherwise pick the higher refresh rate */ 3274 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3275 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3276 3277 return (r1 < r2 ? m2 : m1); 3278 } 3279 3280 static const struct videomode * 3281 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3282 int x, int y) 3283 { 3284 struct edid_info *ep = &rp->rp_edid; 3285 struct videomode *vmp = NULL; 3286 int i; 3287 3288 if (!rp->rp_edid_valid) { 3289 /* fallback to safe mode */ 3290 return radeonfb_modelookup(sc->sc_defaultmode); 3291 } 3292 3293 /* always choose the preferred mode first! */ 3294 if (ep->edid_preferred_mode) { 3295 3296 /* XXX: add auto-stretching support for native mode */ 3297 3298 /* this may want panning to occur, btw */ 3299 if ((ep->edid_preferred_mode->hdisplay <= x) && 3300 (ep->edid_preferred_mode->vdisplay <= y)) 3301 return ep->edid_preferred_mode; 3302 } 3303 3304 for (i = 0; i < ep->edid_nmodes; i++) { 3305 /* 3306 * We elect to pick a resolution that is too large for 3307 * the monitor than one that is too small. This means 3308 * that we will prefer to pan rather than to try to 3309 * center a smaller display on a larger screen. In 3310 * practice, this shouldn't matter because if a 3311 * monitor can support a larger resolution, it can 3312 * probably also support the smaller. A specific 3313 * exception is fixed format panels, but hopefully 3314 * they are properly dealt with by the "autostretch" 3315 * logic above. 3316 */ 3317 if ((ep->edid_modes[i].hdisplay > x) || 3318 (ep->edid_modes[i].vdisplay > y)) { 3319 continue; 3320 } 3321 3322 /* 3323 * at this point, the display mode is no larger than 3324 * what we've requested. 3325 */ 3326 if (vmp == NULL) 3327 vmp = &ep->edid_modes[i]; 3328 3329 /* eliminate smaller modes */ 3330 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3331 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3332 continue; 3333 3334 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3335 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3336 vmp = &ep->edid_modes[i]; 3337 continue; 3338 } 3339 3340 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3341 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3342 3343 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3344 } 3345 3346 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3347 } 3348 3349 static int 3350 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3351 { 3352 int i; 3353 3354 for (i = 0; i < nlist; i++) { 3355 if ((x == list[i].hdisplay) && 3356 (y == list[i].vdisplay)) { 3357 return 1; 3358 } 3359 } 3360 return 0; 3361 } 3362 3363 static void 3364 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3365 int pan) 3366 { 3367 struct radeonfb_port *rp; 3368 struct edid_info *ep; 3369 int i, j; 3370 3371 *x = 0; 3372 *y = 0; 3373 3374 if (pan) { 3375 for (i = 0; i < dp->rd_ncrtcs; i++) { 3376 rp = dp->rd_crtcs[i].rc_port; 3377 ep = &rp->rp_edid; 3378 if (!rp->rp_edid_valid) { 3379 /* monitor not present */ 3380 continue; 3381 } 3382 3383 /* 3384 * For now we are ignoring "conflict" that 3385 * could occur when mixing some modes like 3386 * 1280x1024 and 1400x800. It isn't clear 3387 * which is better, so the first one wins. 3388 */ 3389 for (j = 0; j < ep->edid_nmodes; j++) { 3390 /* 3391 * ignore resolutions that are too big for 3392 * the radeon 3393 */ 3394 if (ep->edid_modes[j].hdisplay > 3395 dp->rd_softc->sc_maxx) 3396 continue; 3397 if (ep->edid_modes[j].vdisplay > 3398 dp->rd_softc->sc_maxy) 3399 continue; 3400 3401 /* 3402 * pick largest resolution, the 3403 * smaller monitor will pan 3404 */ 3405 if ((ep->edid_modes[j].hdisplay >= *x) && 3406 (ep->edid_modes[j].vdisplay >= *y)) { 3407 *x = ep->edid_modes[j].hdisplay; 3408 *y = ep->edid_modes[j].vdisplay; 3409 } 3410 } 3411 } 3412 3413 } else { 3414 struct videomode modes[64]; 3415 int nmodes = 0; 3416 int valid = 0; 3417 3418 for (i = 0; i < dp->rd_ncrtcs; i++) { 3419 /* 3420 * pick the largest resolution in common. 3421 */ 3422 rp = dp->rd_crtcs[i].rc_port; 3423 ep = &rp->rp_edid; 3424 3425 if (!rp->rp_edid_valid) 3426 continue; 3427 3428 if (!valid) { 3429 /* 3430 * Pick the preferred mode for this port 3431 * if available. 3432 */ 3433 if (ep->edid_preferred_mode) { 3434 struct videomode *vmp = 3435 ep->edid_preferred_mode; 3436 3437 if ((vmp->hdisplay <= 3438 dp->rd_softc->sc_maxx) && 3439 (vmp->vdisplay <= 3440 dp->rd_softc->sc_maxy)) 3441 modes[nmodes++] = *vmp; 3442 } else { 3443 3444 /* initialize starting list */ 3445 for (j = 0; j < ep->edid_nmodes; j++) { 3446 /* 3447 * ignore resolutions that are 3448 * too big for the radeon 3449 */ 3450 if (ep->edid_modes[j].hdisplay > 3451 dp->rd_softc->sc_maxx) 3452 continue; 3453 if (ep->edid_modes[j].vdisplay > 3454 dp->rd_softc->sc_maxy) 3455 continue; 3456 3457 modes[nmodes] = 3458 ep->edid_modes[j]; 3459 nmodes++; 3460 } 3461 } 3462 valid = 1; 3463 } else { 3464 /* merge into preexisting list */ 3465 for (j = 0; j < nmodes; j++) { 3466 if (!radeonfb_hasres(ep->edid_modes, 3467 ep->edid_nmodes, 3468 modes[j].hdisplay, 3469 modes[j].vdisplay)) { 3470 modes[j] = modes[nmodes]; 3471 j--; 3472 nmodes--; 3473 } 3474 } 3475 } 3476 } 3477 3478 /* now we have to pick from the merged list */ 3479 for (i = 0; i < nmodes; i++) { 3480 if ((modes[i].hdisplay >= *x) && 3481 (modes[i].vdisplay >= *y)) { 3482 *x = modes[i].hdisplay; 3483 *y = modes[i].vdisplay; 3484 } 3485 } 3486 } 3487 3488 if ((*x == 0) || (*y == 0)) { 3489 /* fallback to safe mode */ 3490 *x = 640; 3491 *y = 480; 3492 } 3493 } 3494 3495 /* 3496 * backlight levels are linear on: 3497 * - RV200, RV250, RV280, RV350 3498 * - but NOT on PowerBook4,3 6,3 6,5 3499 * according to Linux' radeonfb 3500 */ 3501 3502 /* Get the current backlight level for the display. */ 3503 3504 static int 3505 radeonfb_get_backlight(struct radeonfb_display *dp) 3506 { 3507 int s; 3508 uint32_t level; 3509 3510 s = spltty(); 3511 3512 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3513 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3514 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3515 3516 /* 3517 * On some chips, we should negate the backlight level. 3518 * XXX Find out on which chips. 3519 */ 3520 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3521 level = RADEONFB_BACKLIGHT_MAX - level; 3522 3523 splx(s); 3524 3525 return level; 3526 } 3527 3528 /* Set the backlight to the given level for the display. */ 3529 3530 static int 3531 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3532 { 3533 struct radeonfb_softc *sc; 3534 int rlevel, s; 3535 uint32_t lvds; 3536 3537 s = spltty(); 3538 3539 if (level < 0) 3540 level = 0; 3541 else if (level >= RADEONFB_BACKLIGHT_MAX) 3542 level = RADEONFB_BACKLIGHT_MAX; 3543 3544 sc = dp->rd_softc; 3545 3546 /* On some chips, we should negate the backlight level. */ 3547 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3548 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3549 } else 3550 rlevel = level; 3551 3552 callout_stop(&dp->rd_bl_lvds_co); 3553 radeonfb_engine_idle(sc); 3554 3555 /* 3556 * Turn off the display if the backlight is set to 0, since the 3557 * display is useless without backlight anyway. 3558 */ 3559 if (level == 0) 3560 radeonfb_blank(dp, 1); 3561 else if (radeonfb_get_backlight(dp) == 0) 3562 radeonfb_blank(dp, 0); 3563 3564 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3565 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3566 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3567 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3568 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3569 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3570 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3571 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3572 lvds |= RADEON_LVDS_ON; 3573 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3574 } else { 3575 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3576 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3577 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3578 } 3579 3580 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3581 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3582 /* XXX What is the correct delay? */ 3583 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3584 3585 splx(s); 3586 3587 return 0; 3588 } 3589 3590 /* 3591 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3592 * Set the delayed bits in the register, and clear the stored delayed 3593 * value. 3594 */ 3595 3596 static void radeonfb_lvds_callout(void *arg) 3597 { 3598 struct radeonfb_display *dp = arg; 3599 int s; 3600 3601 s = splhigh(); 3602 3603 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3604 dp->rd_bl_lvds_val); 3605 dp->rd_bl_lvds_val = 0; 3606 3607 splx(s); 3608 } 3609 3610 static void 3611 radeonfb_brightness_up(device_t dev) 3612 { 3613 struct radeonfb_softc *sc = device_private(dev); 3614 int level; 3615 3616 /* we assume the main display is the first one - need a better way */ 3617 if (sc->sc_ndisplays < 1) return; 3618 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3619 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3620 radeonfb_set_backlight(&sc->sc_displays[0], level); 3621 } 3622 3623 static void 3624 radeonfb_brightness_down(device_t dev) 3625 { 3626 struct radeonfb_softc *sc = device_private(dev); 3627 int level; 3628 3629 /* we assume the main display is the first one - need a better way */ 3630 if (sc->sc_ndisplays < 1) return; 3631 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3632 level = max(0, level - 5); 3633 radeonfb_set_backlight(&sc->sc_displays[0], level); 3634 } 3635