1 /* $NetBSD: radeonfb.c,v 1.46 2011/08/18 02:09:44 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.46 2011/08/18 02:09:44 christos Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 8 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 #include <dev/pci/wsdisplay_pci.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 103 static int radeonfb_match(device_t, cfdata_t, void *); 104 static void radeonfb_attach(device_t, device_t, void *); 105 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 106 struct lwp *); 107 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 108 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 109 static void radeonfb_loadbios(struct radeonfb_softc *, 110 const struct pci_attach_args *); 111 112 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 113 uintmax_t); 114 static int radeonfb_getclocks(struct radeonfb_softc *); 115 static int radeonfb_gettmds(struct radeonfb_softc *); 116 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 117 uint32_t *, uint32_t *); 118 static int radeonfb_getconnectors(struct radeonfb_softc *); 119 static const struct videomode *radeonfb_modelookup(const char *); 120 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 121 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 122 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 123 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 124 static void radeonfb_modeswitch(struct radeonfb_display *); 125 static void radeonfb_setcrtc(struct radeonfb_display *, int); 126 static void radeonfb_init_misc(struct radeonfb_softc *); 127 static void radeonfb_set_fbloc(struct radeonfb_softc *); 128 static void radeonfb_init_palette(struct radeonfb_softc *, int); 129 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 130 131 static int radeonfb_isblank(struct radeonfb_display *); 132 static void radeonfb_blank(struct radeonfb_display *, int); 133 static int radeonfb_set_cursor(struct radeonfb_display *, 134 struct wsdisplay_cursor *); 135 static int radeonfb_set_curpos(struct radeonfb_display *, 136 struct wsdisplay_curpos *); 137 138 /* acceleration support */ 139 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 140 int width, int height, uint32_t color); 141 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 142 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 143 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 144 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 145 int, uint32_t, uint32_t); 146 147 /* hw cursor support */ 148 static void radeonfb_cursor_cmap(struct radeonfb_display *); 149 static void radeonfb_cursor_shape(struct radeonfb_display *); 150 static void radeonfb_cursor_position(struct radeonfb_display *); 151 static void radeonfb_cursor_visible(struct radeonfb_display *); 152 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 153 154 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 155 static void radeonfb_engine_idle(struct radeonfb_softc *); 156 static void radeonfb_engine_flush(struct radeonfb_softc *); 157 static void radeonfb_engine_reset(struct radeonfb_softc *); 158 static void radeonfb_engine_init(struct radeonfb_display *); 159 static inline void radeonfb_unclip(struct radeonfb_softc *); 160 161 static void radeonfb_eraserows(void *, int, int, long); 162 static void radeonfb_erasecols(void *, int, int, int, long); 163 static void radeonfb_copyrows(void *, int, int, int); 164 static void radeonfb_copycols(void *, int, int, int, int); 165 static void radeonfb_cursor(void *, int, int, int); 166 static void radeonfb_putchar(void *, int, int, unsigned, long); 167 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 168 static int radeonfb_allocattr(void *, int, int, int, long *); 169 170 static int radeonfb_get_backlight(struct radeonfb_display *); 171 static int radeonfb_set_backlight(struct radeonfb_display *, int); 172 static void radeonfb_lvds_callout(void *); 173 174 static void radeonfb_brightness_up(device_t); 175 static void radeonfb_brightness_down(device_t); 176 177 static struct videomode *radeonfb_best_refresh(struct videomode *, 178 struct videomode *); 179 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 180 uint16_t *, int); 181 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 182 struct radeonfb_port *, int, int); 183 184 static int radeonfb_drm_print(void *, const char *); 185 186 #ifdef RADEONFB_DEBUG 187 int radeon_debug = 1; 188 #define DPRINTF(x) \ 189 if (radeon_debug) printf x 190 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 191 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 192 #else 193 #define DPRINTF(x) 194 #define PRINTREG(r) 195 #define PRINTPLL(r) 196 #endif 197 198 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 199 200 #ifndef RADEON_DEFAULT_MODE 201 /* any reasonably modern display should handle this */ 202 #define RADEON_DEFAULT_MODE "1024x768x60" 203 #endif 204 205 extern const u_char rasops_cmap[768]; 206 207 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 208 209 static struct { 210 int size; /* minimum memory size (MB) */ 211 int maxx; /* maximum x dimension */ 212 int maxy; /* maximum y dimension */ 213 int maxbpp; /* maximum bpp */ 214 int maxdisp; /* maximum logical display count */ 215 } radeonfb_limits[] = { 216 { 32, 2048, 1536, 32, 2 }, 217 { 16, 1600, 1200, 32, 2 }, 218 { 8, 1600, 1200, 32, 1 }, 219 { 0, 0, 0, 0, 0 }, 220 }; 221 222 static struct wsscreen_descr radeonfb_stdscreen = { 223 "fb", /* name */ 224 0, 0, /* ncols, nrows */ 225 NULL, /* textops */ 226 8, 16, /* fontwidth, fontheight */ 227 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 228 0, /* modecookie */ 229 }; 230 231 struct wsdisplay_accessops radeonfb_accessops = { 232 radeonfb_ioctl, 233 radeonfb_mmap, 234 NULL, /* vcons_alloc_screen */ 235 NULL, /* vcons_free_screen */ 236 NULL, /* vcons_show_screen */ 237 NULL, /* load_font */ 238 NULL, /* pollc */ 239 NULL, /* scroll */ 240 }; 241 242 static struct { 243 uint16_t devid; 244 uint16_t family; 245 uint16_t flags; 246 } radeonfb_devices[] = 247 { 248 /* R100 family */ 249 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 252 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 253 254 /* RV100 family */ 255 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 256 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 257 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 259 260 /* RS100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 263 264 /* RS200/RS250 family */ 265 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 266 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 269 270 /* R200 family */ 271 /* add more R200 products? , 5148 */ 272 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 277 278 /* RV200 family */ 279 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 283 284 /* RV250 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 290 291 /* RS300 family */ 292 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 296 297 /* RV280 family */ 298 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 305 306 /* R300 family */ 307 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 315 316 /* RV350/RV360 family */ 317 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 329 330 /* R350/R360 family */ 331 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 339 340 /* RV380/RV370 family */ 341 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 350 351 /* R420/R423 family */ 352 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 369 370 { 0, 0, 0 } 371 }; 372 373 static struct { 374 int divider; 375 int mask; 376 } radeonfb_dividers[] = { 377 { 1, 0 }, 378 { 2, 1 }, 379 { 3, 4 }, 380 { 4, 2 }, 381 { 6, 6 }, 382 { 8, 3 }, 383 { 12, 7 }, 384 { 0, 0 } 385 }; 386 387 /* 388 * This table taken from X11. 389 */ 390 static const struct { 391 int family; 392 struct radeon_tmds_pll plls[4]; 393 } radeonfb_tmds_pll[] = { 394 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 395 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 396 { RADEON_RS100, {{0, 0}}}, 397 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 400 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 401 { RADEON_RS300, {{0, 0}}}, 402 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 403 { RADEON_R300, {{-1, 0xb01cb}}}, 404 { RADEON_R350, {{-1, 0xb01cb}}}, 405 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 406 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 407 { RADEON_R420, {{-1, 0xb01cb}}}, 408 }; 409 410 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 411 412 413 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 414 radeonfb_match, radeonfb_attach, NULL, NULL); 415 416 static int 417 radeonfb_match(device_t parent, cfdata_t match, void *aux) 418 { 419 const struct pci_attach_args *pa = aux; 420 int i; 421 422 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 423 return 0; 424 425 for (i = 0; radeonfb_devices[i].devid; i++) { 426 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 427 return 100; /* high to defeat VGA/VESA */ 428 } 429 430 return 0; 431 } 432 433 static void 434 radeonfb_attach(device_t parent, device_t dev, void *aux) 435 { 436 struct radeonfb_softc *sc = device_private(dev); 437 const struct pci_attach_args *pa = aux; 438 const char *mptr; 439 bus_size_t bsz; 440 pcireg_t screg; 441 int i, j, fg, bg, ul, flags; 442 uint32_t v; 443 444 sc->sc_id = pa->pa_id; 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 447 break; 448 } 449 450 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 451 sizeof(sc->sc_devinfo)); 452 453 aprint_naive("\n"); 454 aprint_normal(": %s\n", sc->sc_devinfo); 455 456 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 457 458 KASSERT(radeonfb_devices[i].devid != 0); 459 sc->sc_pt = pa->pa_tag; 460 sc->sc_iot = pa->pa_iot; 461 sc->sc_pc = pa->pa_pc; 462 sc->sc_family = radeonfb_devices[i].family; 463 sc->sc_flags = radeonfb_devices[i].flags; 464 465 /* enable memory and IO access */ 466 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 467 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 468 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 469 470 /* 471 * Some flags are general to entire chip families, and rather 472 * than clutter up the table with them, we go ahead and set 473 * them here. 474 */ 475 switch (sc->sc_family) { 476 case RADEON_RS100: 477 case RADEON_RS200: 478 sc->sc_flags |= RFB_IGP | RFB_RV100; 479 break; 480 481 case RADEON_RV100: 482 case RADEON_RV200: 483 case RADEON_RV250: 484 case RADEON_RV280: 485 sc->sc_flags |= RFB_RV100; 486 break; 487 488 case RADEON_RS300: 489 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_R300: 493 case RADEON_RV350: 494 case RADEON_R350: 495 case RADEON_RV380: 496 case RADEON_R420: 497 /* newer chips */ 498 sc->sc_flags |= RFB_R300; 499 break; 500 501 case RADEON_R100: 502 sc->sc_flags |= RFB_NCRTC2; 503 break; 504 } 505 506 if ((sc->sc_family == RADEON_RV200) || 507 (sc->sc_family == RADEON_RV250) || 508 (sc->sc_family == RADEON_RV280) || 509 (sc->sc_family == RADEON_RV350)) { 510 bool inverted = 0; 511 /* backlight level is linear */ 512 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 513 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 514 "backlight_level_reverted", &inverted); 515 if (inverted) { 516 DPRINTF(("nope, it's inverted\n")); 517 sc->sc_flags |= RFB_INV_BLIGHT; 518 } 519 } else 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 522 /* 523 * XXX: to support true multihead, this must change. 524 */ 525 sc->sc_ndisplays = 1; 526 527 /* XXX: */ 528 if (!HAS_CRTC2(sc)) { 529 sc->sc_ndisplays = 1; 530 } 531 532 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 533 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 534 &sc->sc_regsz) != 0) { 535 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 536 goto error; 537 } 538 539 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 540 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 541 { 542 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 543 goto error; 544 } 545 sc->sc_romt = sc->sc_memt; 546 547 /* scratch register test... */ 548 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 549 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 550 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 551 goto error; 552 } 553 554 PRINTREG(RADEON_BIOS_4_SCRATCH); 555 PRINTREG(RADEON_FP_GEN_CNTL); 556 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 557 PRINTREG(RADEON_FP2_GEN_CNTL); 558 PRINTREG(RADEON_TMDS_CNTL); 559 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 560 PRINTREG(RADEON_TMDS_PLL_CNTL); 561 PRINTREG(RADEON_LVDS_GEN_CNTL); 562 PRINTREG(RADEON_FP_HORZ_STRETCH); 563 PRINTREG(RADEON_FP_VERT_STRETCH); 564 565 /* XXX: RV100 specific */ 566 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 567 568 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 569 RADEON_TMDS_TRANSMITTER_PLLEN, 570 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 571 572 radeonfb_i2c_init(sc); 573 574 radeonfb_loadbios(sc, pa); 575 576 #ifdef RADEONFB_BIOS_INIT 577 if (radeonfb_bios_init(sc)) { 578 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 579 } 580 #endif 581 582 if (radeonfb_getclocks(sc)) { 583 aprint_error("%s: Unable to get reference clocks from BIOS\n", 584 XNAME(sc)); 585 goto error; 586 } 587 588 if (radeonfb_gettmds(sc)) { 589 aprint_error("%s: Unable to identify TMDS PLL settings\n", 590 XNAME(sc)); 591 goto error; 592 } 593 594 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 595 "minpll = %d, maxpll = %d\n", XNAME(sc), 596 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 597 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 598 599 radeonfb_getconnectors(sc); 600 601 radeonfb_set_fbloc(sc); 602 603 for (i = 0; radeonfb_limits[i].size; i++) { 604 if (sc->sc_memsz >= radeonfb_limits[i].size) { 605 sc->sc_maxx = radeonfb_limits[i].maxx; 606 sc->sc_maxy = radeonfb_limits[i].maxy; 607 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 608 /* framebuffer offset, start at a 4K page */ 609 sc->sc_fboffset = sc->sc_memsz / 610 radeonfb_limits[i].maxdisp; 611 /* 612 * we use the fbsize to figure out where we can store 613 * things like cursor data. 614 */ 615 sc->sc_fbsize = 616 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 617 RADEON_STRIDEALIGN) * sc->sc_maxy, 618 4096); 619 break; 620 } 621 } 622 623 624 radeonfb_init_misc(sc); 625 radeonfb_init_palette(sc, 0); 626 if (HAS_CRTC2(sc)) 627 radeonfb_init_palette(sc, 1); 628 629 /* program the DAC wirings */ 630 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 631 switch (sc->sc_ports[i].rp_dac_type) { 632 case RADEON_DAC_PRIMARY: 633 PATCH32(sc, RADEON_DAC_CNTL2, 634 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 635 ~RADEON_DAC2_DAC_CLK_SEL); 636 break; 637 case RADEON_DAC_TVDAC: 638 /* we always use the TVDAC to drive a secondary analog 639 * CRT for now. if we ever support TV-out this will 640 * have to change. 641 */ 642 SET32(sc, RADEON_DAC_CNTL2, 643 RADEON_DAC2_DAC2_CLK_SEL); 644 PATCH32(sc, RADEON_DISP_HW_DEBUG, 645 i ? 0 : RADEON_CRT2_DISP1_SEL, 646 ~RADEON_CRT2_DISP1_SEL); 647 break; 648 } 649 } 650 PRINTREG(RADEON_DAC_CNTL2); 651 PRINTREG(RADEON_DISP_HW_DEBUG); 652 653 /* other DAC programming */ 654 v = GET32(sc, RADEON_DAC_CNTL); 655 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 656 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 657 PUT32(sc, RADEON_DAC_CNTL, v); 658 PRINTREG(RADEON_DAC_CNTL); 659 660 /* XXX: this may need more investigation */ 661 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 662 PRINTREG(RADEON_TV_DAC_CNTL); 663 664 /* enable TMDS */ 665 SET32(sc, RADEON_FP_GEN_CNTL, 666 RADEON_FP_TMDS_EN | 667 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 668 RADEON_FP_CRTC_DONT_SHADOW_HEND); 669 /* 670 * XXX 671 * no idea why this is necessary - if I do not clear this bit on my 672 * iBook G4 the screen remains black, even though it's already clear. 673 * It needs to be set on my Sun XVR-100 for the DVI port to work 674 */ 675 676 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 677 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 678 } else 679 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 681 if (HAS_CRTC2(sc)) 682 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 683 684 /* 685 * we use bus_space_map instead of pci_mapreg, because we don't 686 * need the full aperature space. no point in wasting virtual 687 * address space we don't intend to use, right? 688 */ 689 if ((sc->sc_memsz < (4096 * 1024)) || 690 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 691 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 692 (bsz < sc->sc_memsz)) { 693 sc->sc_memsz = 0; 694 aprint_error("%s: Bad frame buffer configuration\n", 695 XNAME(sc)); 696 goto error; 697 } 698 699 /* 64 MB should be enough -- more just wastes map entries */ 700 if (sc->sc_memsz > (64 << 20)) 701 sc->sc_memsz = (64 << 20); 702 703 sc->sc_memt = pa->pa_memt; 704 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 705 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 706 sc->sc_memsz = 0; 707 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 708 goto error; 709 } 710 711 aprint_normal("%s: %d MB aperture at 0x%08x, " 712 "%d KB registers at 0x%08x\n", XNAME(sc), 713 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 714 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 715 716 /* setup default video mode from devprop (allows PROM override) */ 717 sc->sc_defaultmode = radeonfb_default_mode; 718 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 719 "videomode", &mptr)) { 720 721 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 722 sc->sc_defaultmode = sc->sc_modebuf; 723 } 724 725 /* initialize some basic display parameters */ 726 for (i = 0; i < sc->sc_ndisplays; i++) { 727 struct radeonfb_display *dp = &sc->sc_displays[i]; 728 struct rasops_info *ri; 729 long defattr; 730 struct wsemuldisplaydev_attach_args aa; 731 732 /* 733 * Figure out how many "displays" (desktops) we are going to 734 * support. If more than one, then each CRTC gets its own 735 * programming. 736 * 737 * XXX: this code needs to change to support mergedfb. 738 * XXX: would be nice to allow this to be overridden 739 */ 740 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 741 DPRINTF(("dual crtcs!\n")); 742 dp->rd_ncrtcs = 2; 743 dp->rd_crtcs[0].rc_number = 0; 744 dp->rd_crtcs[1].rc_number = 1; 745 } else { 746 dp->rd_ncrtcs = 1; 747 dp->rd_crtcs[0].rc_number = i; 748 } 749 750 /* set up port pointer */ 751 for (j = 0; j < dp->rd_ncrtcs; j++) { 752 dp->rd_crtcs[j].rc_port = 753 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 754 } 755 756 dp->rd_softc = sc; 757 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 758 dp->rd_bg = WS_DEFAULT_BG; 759 #if 0 760 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 761 #else 762 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 763 #endif 764 /* for text mode, we pick a resolution that won't 765 * require panning */ 766 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 767 768 aprint_normal("%s: display %d: " 769 "initial virtual resolution %dx%d at %d bpp\n", 770 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 771 772 /* now select the *video mode* that we will use */ 773 for (j = 0; j < dp->rd_ncrtcs; j++) { 774 const struct videomode *vmp; 775 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 776 dp->rd_virtx, dp->rd_virty); 777 778 /* 779 * virtual resolution should be at least as high as 780 * physical 781 */ 782 if (dp->rd_virtx < vmp->hdisplay || 783 dp->rd_virty < vmp->vdisplay) { 784 dp->rd_virtx = vmp->hdisplay; 785 dp->rd_virty = vmp->vdisplay; 786 } 787 788 dp->rd_crtcs[j].rc_videomode = *vmp; 789 printf("%s: port %d: physical %dx%d %dHz\n", 790 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 791 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 792 vmp->htotal), vmp->vtotal)); 793 } 794 795 /* N.B.: radeon wants 64-byte aligned stride */ 796 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 797 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 798 799 dp->rd_offset = sc->sc_fboffset * i; 800 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 801 sc->sc_memh) + dp->rd_offset; 802 dp->rd_curoff = sc->sc_fbsize; 803 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 804 805 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 806 807 switch (dp->rd_bpp) { 808 case 8: 809 dp->rd_format = 2; 810 break; 811 case 32: 812 dp->rd_format = 6; 813 break; 814 default: 815 aprint_error("%s: bad depth %d\n", XNAME(sc), 816 dp->rd_bpp); 817 goto error; 818 } 819 820 DPRINTF(("init engine\n")); 821 /* XXX: this seems suspicious - per display engine 822 initialization? */ 823 radeonfb_engine_init(dp); 824 825 /* copy the template into place */ 826 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 827 dp->rd_wsscreens = dp->rd_wsscreens_storage; 828 829 /* and make up the list */ 830 dp->rd_wsscreenlist.nscreens = 1; 831 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 832 833 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 834 &radeonfb_accessops); 835 836 dp->rd_vd.init_screen = radeonfb_init_screen; 837 838 dp->rd_console = 0; 839 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 840 "is_console", &dp->rd_console); 841 842 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 843 844 845 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 846 dp->rd_console, &defattr); 847 848 ri = &dp->rd_vscreen.scr_ri; 849 850 /* clear the screen */ 851 rasops_unpack_attr(defattr, &fg, &bg, &ul); 852 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 853 ri->ri_devcmap[bg & 0xf]); 854 855 dp->rd_wsscreens->textops = &ri->ri_ops; 856 dp->rd_wsscreens->capabilities = ri->ri_caps; 857 dp->rd_wsscreens->nrows = ri->ri_rows; 858 dp->rd_wsscreens->ncols = ri->ri_cols; 859 860 #ifdef SPLASHSCREEN 861 dp->rd_splash.si_depth = ri->ri_depth; 862 dp->rd_splash.si_bits = ri->ri_bits; 863 dp->rd_splash.si_hwbits = ri->ri_hwbits; 864 dp->rd_splash.si_width = ri->ri_width; 865 dp->rd_splash.si_height = ri->ri_height; 866 dp->rd_splash.si_stride = ri->ri_stride; 867 dp->rd_splash.si_fillrect = NULL; 868 #endif 869 if (dp->rd_console) { 870 871 radeonfb_modeswitch(dp); 872 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 873 defattr); 874 #ifdef SPLASHSCREEN 875 if (splash_render(&dp->rd_splash, 876 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 877 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 878 else 879 #endif 880 vcons_replay_msgbuf(&dp->rd_vscreen); 881 } else { 882 883 /* 884 * since we're not the console we can postpone 885 * the rest until someone actually allocates a 886 * screen for us. but we do clear the screen 887 * at least. 888 */ 889 memset(ri->ri_bits, 0, 1024); 890 891 radeonfb_modeswitch(dp); 892 #ifdef SPLASHSCREEN 893 if (splash_render(&dp->rd_splash, 894 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 895 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 896 #endif 897 } 898 899 aa.console = dp->rd_console; 900 aa.scrdata = &dp->rd_wsscreenlist; 901 aa.accessops = &radeonfb_accessops; 902 aa.accesscookie = &dp->rd_vd; 903 904 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 905 906 radeonfb_blank(dp, 0); 907 908 /* Initialise delayed lvds operations for backlight. */ 909 callout_init(&dp->rd_bl_lvds_co, 0); 910 callout_setfunc(&dp->rd_bl_lvds_co, 911 radeonfb_lvds_callout, dp); 912 } 913 914 /* 915 * if we have console output via firmware like on sparc64 it may 916 * interfere with DAC programming so program the palette again 917 * here after we took over 918 */ 919 radeonfb_init_palette(sc, 0); 920 if (HAS_CRTC2(sc)) 921 radeonfb_init_palette(sc, 1); 922 923 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 924 radeonfb_brightness_up, TRUE); 925 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 926 radeonfb_brightness_down, TRUE); 927 928 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 929 930 return; 931 932 error: 933 if (sc->sc_biossz) 934 free(sc->sc_bios, M_DEVBUF); 935 936 if (sc->sc_regsz) 937 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 938 939 if (sc->sc_memsz) 940 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 941 } 942 943 static int 944 radeonfb_drm_print(void *aux, const char *pnp) 945 { 946 if (pnp) 947 aprint_normal("drm at %s", pnp); 948 return (UNCONF); 949 } 950 951 int 952 radeonfb_ioctl(void *v, void *vs, 953 unsigned long cmd, void *d, int flag, struct lwp *l) 954 { 955 struct vcons_data *vd; 956 struct radeonfb_display *dp; 957 struct radeonfb_softc *sc; 958 struct wsdisplay_param *param; 959 960 vd = (struct vcons_data *)v; 961 dp = (struct radeonfb_display *)vd->cookie; 962 sc = dp->rd_softc; 963 964 switch (cmd) { 965 case WSDISPLAYIO_GTYPE: 966 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 967 return 0; 968 969 case WSDISPLAYIO_GINFO: 970 if (vd->active != NULL) { 971 struct wsdisplay_fbinfo *fb; 972 fb = (struct wsdisplay_fbinfo *)d; 973 fb->width = dp->rd_virtx; 974 fb->height = dp->rd_virty; 975 fb->depth = dp->rd_bpp; 976 fb->cmsize = 256; 977 return 0; 978 } else 979 return ENODEV; 980 case WSDISPLAYIO_GVIDEO: 981 if (radeonfb_isblank(dp)) 982 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 983 else 984 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 985 return 0; 986 987 case WSDISPLAYIO_SVIDEO: 988 radeonfb_blank(dp, 989 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 990 return 0; 991 992 case WSDISPLAYIO_GETCMAP: 993 #if 0 994 if (dp->rd_bpp == 8) 995 return radeonfb_getcmap(sc, 996 (struct wsdisplay_cmap *)d); 997 #endif 998 return EINVAL; 999 1000 case WSDISPLAYIO_PUTCMAP: 1001 #if 0 1002 if (dp->rd_bpp == 8) 1003 return radeonfb_putcmap(sc, 1004 (struct wsdisplay_cmap *)d); 1005 #endif 1006 return EINVAL; 1007 1008 case WSDISPLAYIO_LINEBYTES: 1009 *(unsigned *)d = dp->rd_stride; 1010 return 0; 1011 1012 case WSDISPLAYIO_SMODE: 1013 if (*(int *)d != dp->rd_wsmode) { 1014 dp->rd_wsmode = *(int *)d; 1015 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1016 (dp->rd_vd.active)) { 1017 radeonfb_engine_init(dp); 1018 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1019 radeonfb_modeswitch(dp); 1020 vcons_redraw_screen(dp->rd_vd.active); 1021 } 1022 } 1023 return 0; 1024 1025 case WSDISPLAYIO_GCURMAX: 1026 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1027 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1028 return 0; 1029 1030 case WSDISPLAYIO_SCURSOR: 1031 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1032 1033 case WSDISPLAYIO_GCURSOR: 1034 return EPASSTHROUGH; 1035 1036 case WSDISPLAYIO_GCURPOS: 1037 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1038 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1039 return 0; 1040 1041 case WSDISPLAYIO_SCURPOS: 1042 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1043 1044 case WSDISPLAYIO_SSPLASH: 1045 #if defined(SPLASHSCREEN) 1046 if (*(int *)d == 1) { 1047 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1048 splash_render(&dp->rd_splash, 1049 SPLASH_F_CENTER|SPLASH_F_FILL); 1050 } else 1051 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1052 return 0; 1053 #else 1054 return ENODEV; 1055 #endif 1056 case WSDISPLAYIO_GETPARAM: 1057 param = (struct wsdisplay_param *)d; 1058 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1059 param->min = 0; 1060 param->max = RADEONFB_BACKLIGHT_MAX; 1061 param->curval = radeonfb_get_backlight(dp); 1062 return 0; 1063 } 1064 return EPASSTHROUGH; 1065 1066 case WSDISPLAYIO_SETPARAM: 1067 param = (struct wsdisplay_param *)d; 1068 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1069 return radeonfb_set_backlight(dp, param->curval); 1070 } 1071 return EPASSTHROUGH; 1072 1073 /* PCI config read/write passthrough. */ 1074 case PCI_IOC_CFGREAD: 1075 case PCI_IOC_CFGWRITE: 1076 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1077 1078 case WSDISPLAYIO_GET_BUSID: 1079 return wsdisplayio_busid_pci(&sc->sc_dev, sc->sc_pc, 1080 sc->sc_pt, d); 1081 1082 default: 1083 return EPASSTHROUGH; 1084 } 1085 } 1086 1087 paddr_t 1088 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1089 { 1090 struct vcons_data *vd; 1091 struct radeonfb_display *dp; 1092 struct radeonfb_softc *sc; 1093 paddr_t pa; 1094 1095 vd = (struct vcons_data *)v; 1096 dp = (struct radeonfb_display *)vd->cookie; 1097 sc = dp->rd_softc; 1098 1099 /* XXX: note that we don't allow mapping of registers right now */ 1100 /* XXX: this means that the XFree86 radeon driver won't work */ 1101 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1102 pa = bus_space_mmap(sc->sc_memt, 1103 sc->sc_memaddr + dp->rd_offset + offset, 0, 1104 prot, BUS_SPACE_MAP_LINEAR); 1105 return pa; 1106 } 1107 1108 #ifdef RADEONFB_MMAP_BARS 1109 /* 1110 * restrict all other mappings to processes with superuser privileges 1111 * or the kernel itself 1112 */ 1113 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1114 NULL) != 0) { 1115 aprint_error_dev(&sc->sc_dev, "mmap() rejected.\n"); 1116 return -1; 1117 } 1118 1119 if ((offset >= sc->sc_regaddr) && 1120 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1121 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1122 BUS_SPACE_MAP_LINEAR); 1123 } 1124 1125 if ((offset >= sc->sc_memaddr) && 1126 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1127 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1128 BUS_SPACE_MAP_LINEAR); 1129 } 1130 1131 if ((offset >= sc->sc_romaddr) && 1132 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1133 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1134 BUS_SPACE_MAP_LINEAR); 1135 } 1136 1137 #ifdef PCI_MAGIC_IO_RANGE 1138 /* allow mapping of IO space */ 1139 if ((offset >= PCI_MAGIC_IO_RANGE) && 1140 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1141 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1142 0, prot, 0); 1143 return pa; 1144 } 1145 #endif /* macppc */ 1146 1147 #endif /* RADEONFB_MMAP_BARS */ 1148 1149 return -1; 1150 } 1151 1152 static void 1153 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1154 { 1155 bus_space_tag_t romt; 1156 bus_space_handle_t romh, biosh; 1157 bus_size_t romsz; 1158 bus_addr_t ptr; 1159 1160 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1161 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1162 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1163 return; 1164 } 1165 1166 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1167 &sc->sc_biossz); 1168 if (sc->sc_biossz == 0) { 1169 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1170 return; 1171 } 1172 1173 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1174 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1175 1176 /* unmap the PCI expansion rom */ 1177 bus_space_unmap(romt, romh, romsz); 1178 1179 /* turn off rom decoder now */ 1180 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1181 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1182 ~PCI_MAPREG_ROM_ENABLE); 1183 1184 ptr = GETBIOS16(sc, 0x48); 1185 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1186 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1187 sc->sc_flags |= RFB_ATOM; 1188 } 1189 1190 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1191 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1192 } 1193 1194 1195 uint32_t 1196 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1197 { 1198 1199 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1200 } 1201 1202 void 1203 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1204 { 1205 1206 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1207 } 1208 1209 void 1210 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1211 uint32_t andmask, uint32_t ormask) 1212 { 1213 int s; 1214 uint32_t val; 1215 1216 s = splhigh(); 1217 val = radeonfb_get32(sc, reg); 1218 val = (val & andmask) | ormask; 1219 radeonfb_put32(sc, reg, val); 1220 splx(s); 1221 } 1222 1223 uint32_t 1224 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1225 { 1226 int s; 1227 uint32_t val; 1228 1229 s = splhigh(); 1230 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1231 val = radeonfb_get32(sc, RADEON_MM_DATA); 1232 splx(s); 1233 1234 return (val); 1235 } 1236 1237 void 1238 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1239 { 1240 int s; 1241 1242 s = splhigh(); 1243 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1244 radeonfb_put32(sc, RADEON_MM_DATA, val); 1245 splx(s); 1246 } 1247 1248 void 1249 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1250 uint32_t andmask, uint32_t ormask) 1251 { 1252 int s; 1253 uint32_t val; 1254 1255 s = splhigh(); 1256 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1257 val = radeonfb_get32(sc, RADEON_MM_DATA); 1258 val = (val & andmask) | ormask; 1259 radeonfb_put32(sc, RADEON_MM_DATA, val); 1260 splx(s); 1261 } 1262 1263 uint32_t 1264 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1265 { 1266 int s; 1267 uint32_t val; 1268 1269 s = splhigh(); 1270 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1271 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1272 if (HAS_R300CG(sc)) 1273 radeonfb_r300cg_workaround(sc); 1274 splx(s); 1275 1276 return (val); 1277 } 1278 1279 void 1280 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1281 { 1282 int s; 1283 1284 s = splhigh(); 1285 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1286 RADEON_PLL_WR_EN); 1287 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1288 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1289 splx(s); 1290 } 1291 1292 void 1293 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1294 uint32_t andmask, uint32_t ormask) 1295 { 1296 int s; 1297 uint32_t val; 1298 1299 s = splhigh(); 1300 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1301 RADEON_PLL_WR_EN); 1302 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1303 val = (val & andmask) | ormask; 1304 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1305 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1306 splx(s); 1307 } 1308 1309 int 1310 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1311 { 1312 uint32_t saved; 1313 1314 saved = GET32(sc, reg); 1315 PUT32(sc, reg, v); 1316 if (GET32(sc, reg) != v) { 1317 return -1; 1318 } 1319 PUT32(sc, reg, saved); 1320 return 0; 1321 } 1322 1323 uintmax_t 1324 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1325 uintmax_t defval) 1326 { 1327 prop_number_t pn; 1328 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1329 if (pn == NULL) { 1330 return defval; 1331 } 1332 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1333 return (prop_number_integer_value(pn)); 1334 } 1335 1336 int 1337 radeonfb_getclocks(struct radeonfb_softc *sc) 1338 { 1339 bus_addr_t ptr; 1340 int refclk = 0; 1341 int refdiv = 0; 1342 int minpll = 0; 1343 int maxpll = 0; 1344 1345 /* load initial property values if port/board provides them */ 1346 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1347 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1348 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1349 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1350 1351 if (refclk && refdiv && minpll && maxpll) 1352 goto dontprobe; 1353 1354 if (!sc->sc_biossz) { 1355 /* no BIOS */ 1356 aprint_verbose("%s: No video BIOS, using default clocks\n", 1357 XNAME(sc)); 1358 if (IS_IGP(sc)) 1359 refclk = refclk ? refclk : 1432; 1360 else 1361 refclk = refclk ? refclk : 2700; 1362 refdiv = refdiv ? refdiv : 12; 1363 minpll = minpll ? minpll : 12500; 1364 maxpll = maxpll ? maxpll : 35000; 1365 } else if (IS_ATOM(sc)) { 1366 /* ATOM BIOS */ 1367 ptr = GETBIOS16(sc, 0x48); 1368 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1369 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1370 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1371 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1372 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1373 /* 1374 * ATOM BIOS doesn't supply a reference divider, so we 1375 * have to probe for it. 1376 */ 1377 if (refdiv < 2) 1378 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1379 RADEON_PPLL_REF_DIV_MASK; 1380 /* 1381 * if probe is zero, just assume one that should work 1382 * for most parts 1383 */ 1384 if (refdiv < 2) 1385 refdiv = 12; 1386 1387 } else { 1388 /* Legacy BIOS */ 1389 ptr = GETBIOS16(sc, 0x48); 1390 ptr = GETBIOS16(sc, ptr + 0x30); 1391 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1392 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1393 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1394 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1395 } 1396 1397 1398 dontprobe: 1399 sc->sc_refclk = refclk * 10; 1400 sc->sc_refdiv = refdiv; 1401 sc->sc_minpll = minpll * 10; 1402 sc->sc_maxpll = maxpll * 10; 1403 return 0; 1404 } 1405 1406 int 1407 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1408 uint32_t *postdivbit, uint32_t *feedbackdiv) 1409 { 1410 int i; 1411 uint32_t outfreq; 1412 int div; 1413 1414 DPRINTF(("dot clock: %u\n", dotclock)); 1415 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1416 outfreq = div * dotclock; 1417 if ((outfreq >= sc->sc_minpll) && 1418 (outfreq <= sc->sc_maxpll)) { 1419 DPRINTF(("outfreq: %u\n", outfreq)); 1420 *postdivbit = 1421 ((uint32_t)radeonfb_dividers[i].mask << 16); 1422 DPRINTF(("post divider: %d (mask %x)\n", div, 1423 *postdivbit)); 1424 break; 1425 } 1426 } 1427 1428 if (div == 0) 1429 return 1; 1430 1431 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1432 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1433 return 0; 1434 } 1435 1436 #if 0 1437 #ifdef RADEONFB_DEBUG 1438 static void 1439 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1440 { 1441 char asc[17]; 1442 unsigned ptr = (unsigned)buffer; 1443 char *start = (char *)(ptr & ~0xf); 1444 char *end = (char *)(ptr + size); 1445 1446 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1447 1448 if (pfx == NULL) { 1449 pfx = ""; 1450 } 1451 1452 while (start < end) { 1453 unsigned offset = (unsigned)start & 0xf; 1454 if (offset == 0) { 1455 printf("%s%x: ", pfx, (unsigned)start); 1456 } 1457 if (((unsigned)start < ptr) || 1458 ((unsigned)start >= (ptr + size))) { 1459 printf(" "); 1460 asc[offset] = ' '; 1461 } else { 1462 printf("%02x", *(unsigned char *)start); 1463 if ((*start >= ' ') && (*start <= '~')) { 1464 asc[offset] = *start; 1465 } else { 1466 asc[offset] = '.'; 1467 } 1468 } 1469 asc[offset + 1] = 0; 1470 if (offset % 2) { 1471 printf(" "); 1472 } 1473 if (offset == 15) { 1474 printf(" %s\n", asc); 1475 } 1476 start++; 1477 } 1478 } 1479 #endif 1480 #endif 1481 1482 int 1483 radeonfb_getconnectors(struct radeonfb_softc *sc) 1484 { 1485 int i; 1486 int found = 0; 1487 1488 for (i = 0; i < 2; i++) { 1489 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1490 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1491 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1492 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1493 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1494 } 1495 1496 /* 1497 * This logic is borrowed from Xorg's radeon driver. 1498 */ 1499 if (!sc->sc_biossz) 1500 goto nobios; 1501 1502 if (IS_ATOM(sc)) { 1503 /* not done yet */ 1504 } else { 1505 uint16_t ptr; 1506 int port = 0; 1507 1508 ptr = GETBIOS16(sc, 0x48); 1509 ptr = GETBIOS16(sc, ptr + 0x50); 1510 for (i = 1; i < 4; i++) { 1511 uint16_t entry; 1512 uint8_t conn, ddc, dac, tmds; 1513 1514 /* 1515 * Parse the connector table. From reading the code, 1516 * it appears to made up of 16-bit entries for each 1517 * connector. The 16-bits are defined as: 1518 * 1519 * bits 12-15 - connector type (0 == end of table) 1520 * bits 8-11 - DDC type 1521 * bits 5-7 - ??? 1522 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1523 * bits 1-3 - ??? 1524 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1525 */ 1526 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1527 break; 1528 entry = GETBIOS16(sc, ptr + i * 2); 1529 1530 conn = (entry >> 12) & 0xf; 1531 ddc = (entry >> 8) & 0xf; 1532 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1533 RADEON_DAC_PRIMARY; 1534 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1535 RADEON_TMDS_INT; 1536 1537 if (conn == RADEON_CONN_NONE) 1538 continue; /* no connector */ 1539 1540 if ((found > 0) && 1541 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1542 /* duplicate entry for same connector */ 1543 continue; 1544 } 1545 1546 /* internal DDC_DVI port gets priority */ 1547 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1548 port = 0; 1549 else 1550 port = 1; 1551 1552 sc->sc_ports[port].rp_ddc_type = 1553 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1554 sc->sc_ports[port].rp_dac_type = dac; 1555 sc->sc_ports[port].rp_conn_type = 1556 min(conn, RADEON_CONN_UNSUPPORTED) ; 1557 1558 sc->sc_ports[port].rp_tmds_type = tmds; 1559 1560 if ((conn != RADEON_CONN_DVI_I) && 1561 (conn != RADEON_CONN_DVI_D) && 1562 (tmds == RADEON_TMDS_INT)) 1563 sc->sc_ports[port].rp_tmds_type = 1564 RADEON_TMDS_UNKNOWN; 1565 1566 found += (port + 1); 1567 } 1568 } 1569 1570 nobios: 1571 if (!found) { 1572 DPRINTF(("No connector info in BIOS!\n")); 1573 /* default, port 0 = internal TMDS, port 1 = CRT */ 1574 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1575 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1576 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1577 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1578 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1579 1580 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1581 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1582 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1583 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1584 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1585 } 1586 1587 /* 1588 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1589 * these chips should use TVDAC for the VGA port. 1590 */ 1591 if (HAS_SDAC(sc)) { 1592 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1593 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1594 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1595 } else { 1596 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1597 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1598 } 1599 } else if (!HAS_CRTC2(sc)) { 1600 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1601 } 1602 1603 for (i = 0; i < 2; i++) { 1604 char edid[128]; 1605 uint8_t ddc; 1606 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1607 prop_data_t edid_data; 1608 1609 DPRINTF(("Port #%d:\n", i)); 1610 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1611 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1612 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1613 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1614 1615 sc->sc_ports[i].rp_edid_valid = 0; 1616 /* first look for static EDID data */ 1617 if ((edid_data = prop_dictionary_get(device_properties( 1618 &sc->sc_dev), "EDID")) != NULL) { 1619 1620 aprint_normal_dev(&sc->sc_dev, "using static EDID\n"); 1621 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1622 if (edid_parse(edid, eip) == 0) { 1623 1624 sc->sc_ports[i].rp_edid_valid = 1; 1625 } 1626 } 1627 /* if we didn't find any we'll try to talk to the monitor */ 1628 if (sc->sc_ports[i].rp_edid_valid != 1) { 1629 1630 ddc = sc->sc_ports[i].rp_ddc_type; 1631 if (ddc != RADEON_DDC_NONE) { 1632 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1633 == 0) && (edid_parse(edid, eip) == 0)) { 1634 1635 sc->sc_ports[i].rp_edid_valid = 1; 1636 edid_print(eip); 1637 } 1638 } 1639 } 1640 } 1641 1642 return found; 1643 } 1644 1645 int 1646 radeonfb_gettmds(struct radeonfb_softc *sc) 1647 { 1648 int i; 1649 1650 if (!sc->sc_biossz) { 1651 goto nobios; 1652 } 1653 1654 if (IS_ATOM(sc)) { 1655 /* XXX: not done yet */ 1656 } else { 1657 uint16_t ptr; 1658 int n; 1659 1660 ptr = GETBIOS16(sc, 0x48); 1661 ptr = GETBIOS16(sc, ptr + 0x34); 1662 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1663 if (GETBIOS8(sc, ptr) == 3) { 1664 /* revision three table */ 1665 n = GETBIOS8(sc, ptr + 5) + 1; 1666 n = min(n, 4); 1667 1668 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1669 for (i = 0; i < n; i++) { 1670 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1671 ptr + i * 10 + 8); 1672 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1673 ptr + i * 10 + 0x10); 1674 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1675 sc->sc_tmds_pll[i].rtp_freq, 1676 sc->sc_tmds_pll[i].rtp_pll)); 1677 } 1678 return 0; 1679 } 1680 } 1681 1682 nobios: 1683 DPRINTF(("no suitable DFP table present\n")); 1684 for (i = 0; 1685 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1686 i++) { 1687 int j; 1688 1689 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1690 continue; 1691 1692 for (j = 0; j < 4; j++) { 1693 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1694 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1695 sc->sc_tmds_pll[j].rtp_freq, 1696 sc->sc_tmds_pll[j].rtp_pll)); 1697 } 1698 return 0; 1699 } 1700 1701 return -1; 1702 } 1703 1704 const struct videomode * 1705 radeonfb_modelookup(const char *name) 1706 { 1707 int i; 1708 1709 for (i = 0; i < videomode_count; i++) 1710 if (!strcmp(name, videomode_list[i].name)) 1711 return &videomode_list[i]; 1712 1713 return NULL; 1714 } 1715 1716 void 1717 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1718 { 1719 if (crtc) { 1720 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1721 RADEON_P2PLL_ATOMIC_UPDATE_R); 1722 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1723 } else { 1724 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1725 RADEON_PPLL_ATOMIC_UPDATE_R); 1726 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1727 } 1728 } 1729 1730 void 1731 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1732 { 1733 int i; 1734 1735 for (i = 10000; i; i--) { 1736 if (crtc) { 1737 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1738 RADEON_P2PLL_ATOMIC_UPDATE_R) 1739 break; 1740 } else { 1741 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1742 RADEON_PPLL_ATOMIC_UPDATE_R) 1743 break; 1744 } 1745 } 1746 } 1747 1748 void 1749 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1750 { 1751 uint32_t pbit = 0; 1752 uint32_t feed = 0; 1753 uint32_t data; 1754 #if 1 1755 int i; 1756 #endif 1757 1758 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1759 1760 if (crtc == 0) { 1761 1762 /* XXXX: mobility workaround missing */ 1763 /* XXXX: R300 stuff missing */ 1764 1765 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1766 RADEON_VCLK_SRC_SEL_CPUCLK, 1767 ~RADEON_VCLK_SRC_SEL_MASK); 1768 1769 /* put vclk into reset, use atomic updates */ 1770 SETPLL(sc, RADEON_PPLL_CNTL, 1771 RADEON_PPLL_REFCLK_SEL | 1772 RADEON_PPLL_FBCLK_SEL | 1773 RADEON_PPLL_RESET | 1774 RADEON_PPLL_ATOMIC_UPDATE_EN | 1775 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1776 1777 /* select clock 3 */ 1778 #if 0 1779 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1780 ~RADEON_PLL_DIV_SEL); 1781 #else 1782 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1783 ~RADEON_PLL_DIV_SEL); 1784 #endif 1785 1786 /* XXX: R300 family -- program divider differently? */ 1787 1788 /* program reference divider */ 1789 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1790 ~RADEON_PPLL_REF_DIV_MASK); 1791 PRINTPLL(RADEON_PPLL_REF_DIV); 1792 1793 #if 0 1794 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1795 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1796 RADEON_PPLL_POST3_DIV_MASK); 1797 data |= pbit; 1798 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1799 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1800 #else 1801 for (i = 0; i < 4; i++) { 1802 } 1803 #endif 1804 1805 /* use the atomic update */ 1806 radeonfb_pllwriteupdate(sc, crtc); 1807 1808 /* and wait for it to complete */ 1809 radeonfb_pllwaitatomicread(sc, crtc); 1810 1811 /* program HTOTAL (why?) */ 1812 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1813 1814 /* drop reset */ 1815 CLRPLL(sc, RADEON_PPLL_CNTL, 1816 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1817 RADEON_PPLL_ATOMIC_UPDATE_EN | 1818 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1819 1820 PRINTPLL(RADEON_PPLL_CNTL); 1821 1822 /* give clock time to lock */ 1823 delay(50000); 1824 1825 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1826 RADEON_VCLK_SRC_SEL_PPLLCLK, 1827 ~RADEON_VCLK_SRC_SEL_MASK); 1828 1829 } else { 1830 1831 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1832 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1833 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1834 1835 /* put vclk into reset, use atomic updates */ 1836 SETPLL(sc, RADEON_P2PLL_CNTL, 1837 RADEON_P2PLL_RESET | 1838 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1839 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1840 1841 /* XXX: R300 family -- program divider differently? */ 1842 1843 /* program reference divider */ 1844 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1845 ~RADEON_P2PLL_REF_DIV_MASK); 1846 1847 /* program feedback and post dividers */ 1848 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1849 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1850 RADEON_P2PLL_POST0_DIV_MASK); 1851 data |= pbit; 1852 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1853 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1854 1855 /* use the atomic update */ 1856 radeonfb_pllwriteupdate(sc, crtc); 1857 1858 /* and wait for it to complete */ 1859 radeonfb_pllwaitatomicread(sc, crtc); 1860 1861 /* program HTOTAL (why?) */ 1862 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1863 1864 /* drop reset */ 1865 CLRPLL(sc, RADEON_P2PLL_CNTL, 1866 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1867 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1868 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1869 1870 /* allow time for clock to lock */ 1871 delay(50000); 1872 1873 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1874 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1875 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1876 } 1877 PRINTREG(RADEON_CRTC_MORE_CNTL); 1878 } 1879 1880 void 1881 radeonfb_modeswitch(struct radeonfb_display *dp) 1882 { 1883 struct radeonfb_softc *sc = dp->rd_softc; 1884 int i; 1885 1886 /* blank the display while we switch modes */ 1887 radeonfb_blank(dp, 1); 1888 1889 #if 0 1890 SET32(sc, RADEON_CRTC_EXT_CNTL, 1891 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1892 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1893 #endif 1894 1895 /* these registers might get in the way... */ 1896 PUT32(sc, RADEON_OVR_CLR, 0); 1897 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1898 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1899 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1900 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1901 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1902 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1903 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1904 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1905 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1906 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1907 1908 for (i = 0; i < dp->rd_ncrtcs; i++) 1909 radeonfb_setcrtc(dp, i); 1910 1911 /* activate the display */ 1912 radeonfb_blank(dp, 0); 1913 } 1914 1915 void 1916 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1917 { 1918 int crtc; 1919 struct videomode *mode; 1920 struct radeonfb_softc *sc; 1921 struct radeonfb_crtc *cp; 1922 uint32_t v; 1923 uint32_t gencntl; 1924 uint32_t htotaldisp; 1925 uint32_t hsyncstrt; 1926 uint32_t vtotaldisp; 1927 uint32_t vsyncstrt; 1928 uint32_t fphsyncstrt; 1929 uint32_t fpvsyncstrt; 1930 uint32_t fphtotaldisp; 1931 uint32_t fpvtotaldisp; 1932 uint32_t pitch; 1933 1934 sc = dp->rd_softc; 1935 cp = &dp->rd_crtcs[index]; 1936 crtc = cp->rc_number; 1937 mode = &cp->rc_videomode; 1938 1939 #if 1 1940 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1941 (dp->rd_bpp * 8)); 1942 #else 1943 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1944 (sc->sc_maxbpp * 8)); 1945 #endif 1946 //pitch = pitch | (pitch << 16); 1947 1948 switch (crtc) { 1949 case 0: 1950 gencntl = RADEON_CRTC_GEN_CNTL; 1951 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1952 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1953 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1954 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1955 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1956 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1957 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1958 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1959 break; 1960 case 1: 1961 gencntl = RADEON_CRTC2_GEN_CNTL; 1962 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1963 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1964 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1965 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1966 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1967 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1968 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1969 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1970 break; 1971 default: 1972 panic("Bad CRTC!"); 1973 break; 1974 } 1975 1976 /* 1977 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1978 */ 1979 /* only bother with 32bpp and 8bpp */ 1980 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1981 1982 if (crtc == 1) { 1983 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1984 } else { 1985 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1986 } 1987 1988 if (mode->flags & VID_DBLSCAN) 1989 v |= RADEON_CRTC2_DBL_SCAN_EN; 1990 1991 if (mode->flags & VID_INTERLACE) 1992 v |= RADEON_CRTC2_INTERLACE_EN; 1993 1994 if (mode->flags & VID_CSYNC) { 1995 v |= RADEON_CRTC2_CSYNC_EN; 1996 if (crtc == 1) 1997 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1998 } 1999 2000 PUT32(sc, gencntl, v); 2001 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2002 2003 /* 2004 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2005 */ 2006 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2007 if (crtc == 0) { 2008 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2009 RADEON_CRTC_DISPLAY_DIS); 2010 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2011 if (mode->flags & VID_CSYNC) 2012 v |= RADEON_CRTC_VSYNC_TRISTAT; 2013 } 2014 /* unconditional turn on CRT, in case first CRTC is DFP */ 2015 v |= RADEON_CRTC_CRT_ON; 2016 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2017 PRINTREG(RADEON_CRTC_EXT_CNTL); 2018 2019 /* 2020 * H_TOTAL_DISP 2021 */ 2022 v = ((mode->hdisplay / 8) - 1) << 16; 2023 v |= (mode->htotal / 8) - 1; 2024 PUT32(sc, htotaldisp, v); 2025 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2026 PUT32(sc, fphtotaldisp, v); 2027 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2028 2029 /* 2030 * H_SYNC_STRT_WID 2031 */ 2032 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2033 v |= mode->hsync_start; 2034 if (mode->flags & VID_NHSYNC) 2035 v |= RADEON_CRTC_H_SYNC_POL; 2036 PUT32(sc, hsyncstrt, v); 2037 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2038 PUT32(sc, fphsyncstrt, v); 2039 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2040 2041 /* 2042 * V_TOTAL_DISP 2043 */ 2044 v = ((mode->vdisplay - 1) << 16); 2045 v |= (mode->vtotal - 1); 2046 PUT32(sc, vtotaldisp, v); 2047 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2048 PUT32(sc, fpvtotaldisp, v); 2049 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2050 2051 /* 2052 * V_SYNC_STRT_WID 2053 */ 2054 v = ((mode->vsync_end - mode->vsync_start) << 16); 2055 v |= (mode->vsync_start - 1); 2056 if (mode->flags & VID_NVSYNC) 2057 v |= RADEON_CRTC_V_SYNC_POL; 2058 PUT32(sc, vsyncstrt, v); 2059 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2060 PUT32(sc, fpvsyncstrt, v); 2061 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2062 2063 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2064 2065 switch (crtc) { 2066 case 0: 2067 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2068 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2069 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2070 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2071 2072 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2073 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2074 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2075 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2076 PRINTREG(RADEON_CRTC_EXT_CNTL); 2077 PRINTREG(RADEON_CRTC_GEN_CNTL); 2078 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2079 break; 2080 2081 case 1: 2082 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2083 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2084 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2085 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2086 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2087 RADEON_CRTC2_VSYNC_DIS | 2088 RADEON_CRTC2_HSYNC_DIS | 2089 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2090 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2091 break; 2092 } 2093 } 2094 2095 int 2096 radeonfb_isblank(struct radeonfb_display *dp) 2097 { 2098 uint32_t reg, mask; 2099 2100 if (dp->rd_crtcs[0].rc_number) { 2101 reg = RADEON_CRTC2_GEN_CNTL; 2102 mask = RADEON_CRTC2_DISP_DIS; 2103 } else { 2104 reg = RADEON_CRTC_EXT_CNTL; 2105 mask = RADEON_CRTC_DISPLAY_DIS; 2106 } 2107 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2108 } 2109 2110 void 2111 radeonfb_blank(struct radeonfb_display *dp, int blank) 2112 { 2113 struct radeonfb_softc *sc = dp->rd_softc; 2114 uint32_t reg, mask; 2115 uint32_t fpreg, fpval; 2116 int i; 2117 2118 for (i = 0; i < dp->rd_ncrtcs; i++) { 2119 2120 if (dp->rd_crtcs[i].rc_number) { 2121 reg = RADEON_CRTC2_GEN_CNTL; 2122 mask = RADEON_CRTC2_DISP_DIS; 2123 fpreg = RADEON_FP2_GEN_CNTL; 2124 fpval = RADEON_FP2_ON; 2125 } else { 2126 reg = RADEON_CRTC_EXT_CNTL; 2127 mask = RADEON_CRTC_DISPLAY_DIS; 2128 fpreg = RADEON_FP_GEN_CNTL; 2129 fpval = RADEON_FP_FPON; 2130 } 2131 2132 if (blank) { 2133 SET32(sc, reg, mask); 2134 CLR32(sc, fpreg, fpval); 2135 } else { 2136 CLR32(sc, reg, mask); 2137 SET32(sc, fpreg, fpval); 2138 } 2139 } 2140 PRINTREG(RADEON_FP_GEN_CNTL); 2141 PRINTREG(RADEON_FP2_GEN_CNTL); 2142 } 2143 2144 void 2145 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2146 long *defattr) 2147 { 2148 struct radeonfb_display *dp = cookie; 2149 struct rasops_info *ri = &scr->scr_ri; 2150 2151 /* initialize font subsystem */ 2152 wsfont_init(); 2153 2154 DPRINTF(("init screen called, existing %d\n", existing)); 2155 2156 ri->ri_depth = dp->rd_bpp; 2157 ri->ri_width = dp->rd_virtx; 2158 ri->ri_height = dp->rd_virty; 2159 ri->ri_stride = dp->rd_stride; 2160 ri->ri_flg = RI_CENTER; 2161 ri->ri_bits = (void *)dp->rd_fbptr; 2162 2163 /* XXX: 32 bpp only */ 2164 /* this is rgb in "big-endian order..." */ 2165 ri->ri_rnum = 8; 2166 ri->ri_gnum = 8; 2167 ri->ri_bnum = 8; 2168 ri->ri_rpos = 16; 2169 ri->ri_gpos = 8; 2170 ri->ri_bpos = 0; 2171 2172 if (existing) { 2173 ri->ri_flg |= RI_CLEAR; 2174 2175 /* start a modeswitch now */ 2176 radeonfb_modeswitch(dp); 2177 } 2178 2179 /* 2180 * XXX: font selection should be based on properties, with some 2181 * normal/reasonable default. 2182 */ 2183 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2184 2185 /* initialize and look for an initial font */ 2186 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2187 2188 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2189 dp->rd_virtx / ri->ri_font->fontwidth); 2190 2191 /* enable acceleration */ 2192 dp->rd_putchar = ri->ri_ops.putchar; 2193 ri->ri_ops.copyrows = radeonfb_copyrows; 2194 ri->ri_ops.copycols = radeonfb_copycols; 2195 ri->ri_ops.eraserows = radeonfb_eraserows; 2196 ri->ri_ops.erasecols = radeonfb_erasecols; 2197 ri->ri_ops.allocattr = radeonfb_allocattr; 2198 if (!IS_R300(dp->rd_softc)) { 2199 ri->ri_ops.putchar = radeonfb_putchar; 2200 } else { 2201 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2202 } 2203 ri->ri_ops.cursor = radeonfb_cursor; 2204 } 2205 2206 void 2207 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2208 { 2209 uint32_t gen, ext, gen2 = 0; 2210 uint32_t agploc, aperbase, apersize, mcfbloc; 2211 2212 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2213 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2214 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2215 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2216 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2217 2218 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2219 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2220 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2221 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2222 2223 if (HAS_CRTC2(sc)) { 2224 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2225 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2226 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2227 } 2228 2229 delay(100000); 2230 2231 mcfbloc = (aperbase >> 16) | 2232 ((aperbase + (apersize - 1)) & 0xffff0000); 2233 2234 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2235 sc->sc_memsz = apersize; 2236 2237 if (((agploc & 0xffff) << 16) != 2238 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2239 agploc = mcfbloc & 0xffff0000U; 2240 agploc |= ((agploc + 0x10000) >> 16); 2241 } 2242 2243 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2244 2245 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2246 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2247 2248 DPRINTF(("aperbase = %u\n", aperbase)); 2249 PRINTREG(RADEON_MC_FB_LOCATION); 2250 PRINTREG(RADEON_MC_AGP_LOCATION); 2251 2252 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2253 2254 if (HAS_CRTC2(sc)) 2255 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2256 2257 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2258 2259 #if 0 2260 /* XXX: what is this AGP garbage? :-) */ 2261 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2262 #endif 2263 2264 delay(100000); 2265 2266 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2267 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2268 2269 if (HAS_CRTC2(sc)) 2270 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2271 } 2272 2273 void 2274 radeonfb_init_misc(struct radeonfb_softc *sc) 2275 { 2276 PUT32(sc, RADEON_BUS_CNTL, 2277 RADEON_BUS_MASTER_DIS | 2278 RADEON_BUS_PREFETCH_MODE_ACT | 2279 RADEON_BUS_PCI_READ_RETRY_EN | 2280 RADEON_BUS_PCI_WRT_RETRY_EN | 2281 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2282 RADEON_BUS_MSTR_RD_MULT | 2283 RADEON_BUS_MSTR_RD_LINE | 2284 RADEON_BUS_RD_DISCARD_EN | 2285 RADEON_BUS_MSTR_DISCONNECT_EN | 2286 RADEON_BUS_READ_BURST); 2287 2288 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2289 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2290 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2291 PUT32(sc, RADEON_RBBM_CNTL, 2292 (3 << RADEON_RB_SETTLE_SHIFT) | 2293 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2294 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2295 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2296 2297 /* XXX: figure out what these mean! */ 2298 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2299 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2300 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2301 2302 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2303 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2304 } 2305 2306 /* 2307 * This loads a linear color map for true color. 2308 */ 2309 void 2310 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2311 { 2312 int i; 2313 uint32_t vclk; 2314 2315 #define DAC_WIDTH ((1 << 10) - 1) 2316 #define CLUT_WIDTH ((1 << 8) - 1) 2317 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2318 2319 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2320 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2321 2322 if (crtc) 2323 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2324 else 2325 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2326 2327 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2328 if (sc->sc_displays[crtc].rd_bpp == 0) 2329 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2330 2331 if (sc->sc_displays[crtc].rd_bpp == 8) { 2332 /* ANSI palette */ 2333 int j = 0; 2334 2335 for (i = 0; i <= CLUT_WIDTH; ++i) { 2336 PUT32(sc, RADEON_PALETTE_30_DATA, 2337 (rasops_cmap[j] << 22) | 2338 (rasops_cmap[j + 1] << 12) | 2339 (rasops_cmap[j + 2] << 2)); 2340 j += 3; 2341 } 2342 } else { 2343 /* linear ramp */ 2344 for (i = 0; i <= CLUT_WIDTH; ++i) { 2345 PUT32(sc, RADEON_PALETTE_30_DATA, 2346 (CLUT_COLOR(i) << 10) | 2347 (CLUT_COLOR(i) << 20) | 2348 (CLUT_COLOR(i))); 2349 } 2350 } 2351 2352 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2353 PRINTREG(RADEON_DAC_CNTL2); 2354 2355 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2356 } 2357 2358 /* 2359 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2360 */ 2361 void 2362 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2363 { 2364 uint32_t tmp, save; 2365 2366 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2367 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2368 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2369 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2370 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2371 } 2372 2373 /* 2374 * Acceleration entry points. 2375 */ 2376 static void 2377 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2378 { 2379 struct rasops_info *ri = cookie; 2380 struct vcons_screen *scr = ri->ri_hw; 2381 struct radeonfb_display *dp = scr->scr_cookie; 2382 struct wsdisplay_font *font = PICK_FONT(ri, c); 2383 uint32_t x, y, w, h; 2384 uint32_t bg, fg, flg; 2385 uint8_t *data; 2386 2387 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2388 return; 2389 2390 if (!CHAR_IN_FONT(c, font)) 2391 return; 2392 2393 w = font->fontwidth; 2394 h = font->fontheight; 2395 2396 flg = attr & 0xff; 2397 if (flg & WSATTR_REVERSE) { 2398 fg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2399 bg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2400 } else { 2401 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2402 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2403 } 2404 2405 x = ri->ri_xorigin + col * w; 2406 y = ri->ri_yorigin + row * h; 2407 2408 if (c == 0x20) { 2409 radeonfb_rectfill(dp, x, y, w, h, bg); 2410 } else { 2411 data = (uint8_t *)font->data + 2412 (c - font->firstchar) * ri->ri_fontscale; 2413 2414 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2415 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2416 } 2417 } 2418 2419 /* 2420 * wrapper for software character drawing 2421 * just sync the engine and call rasops*_putchar() 2422 */ 2423 2424 static void 2425 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2426 { 2427 struct rasops_info *ri = cookie; 2428 struct vcons_screen *scr = ri->ri_hw; 2429 struct radeonfb_display *dp = scr->scr_cookie; 2430 2431 radeonfb_engine_idle(dp->rd_softc); 2432 dp->rd_putchar(ri, row, col, c, attr); 2433 } 2434 2435 static void 2436 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2437 { 2438 struct rasops_info *ri = cookie; 2439 struct vcons_screen *scr = ri->ri_hw; 2440 struct radeonfb_display *dp = scr->scr_cookie; 2441 uint32_t x, y, w, h, fg, bg, ul; 2442 2443 /* XXX: check for full emulation mode? */ 2444 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2445 x = ri->ri_xorigin; 2446 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2447 w = ri->ri_emuwidth; 2448 h = ri->ri_font->fontheight * nrows; 2449 2450 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2451 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2452 } 2453 } 2454 2455 static void 2456 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2457 { 2458 struct rasops_info *ri = cookie; 2459 struct vcons_screen *scr = ri->ri_hw; 2460 struct radeonfb_display *dp = scr->scr_cookie; 2461 uint32_t x, ys, yd, w, h; 2462 2463 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2464 x = ri->ri_xorigin; 2465 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2466 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2467 w = ri->ri_emuwidth; 2468 h = ri->ri_font->fontheight * nrows; 2469 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2470 RADEON_ROP3_S, 0xffffffff); 2471 } 2472 } 2473 2474 static void 2475 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2476 { 2477 struct rasops_info *ri = cookie; 2478 struct vcons_screen *scr = ri->ri_hw; 2479 struct radeonfb_display *dp = scr->scr_cookie; 2480 uint32_t xs, xd, y, w, h; 2481 2482 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2483 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2484 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2485 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2486 w = ri->ri_font->fontwidth * ncols; 2487 h = ri->ri_font->fontheight; 2488 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2489 RADEON_ROP3_S, 0xffffffff); 2490 } 2491 } 2492 2493 static void 2494 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2495 long fillattr) 2496 { 2497 struct rasops_info *ri = cookie; 2498 struct vcons_screen *scr = ri->ri_hw; 2499 struct radeonfb_display *dp = scr->scr_cookie; 2500 uint32_t x, y, w, h, fg, bg, ul; 2501 2502 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2503 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2504 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2505 w = ri->ri_font->fontwidth * ncols; 2506 h = ri->ri_font->fontheight; 2507 2508 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2509 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2510 } 2511 } 2512 2513 static void 2514 radeonfb_cursor(void *cookie, int on, int row, int col) 2515 { 2516 struct rasops_info *ri = cookie; 2517 struct vcons_screen *scr = ri->ri_hw; 2518 struct radeonfb_display *dp = scr->scr_cookie; 2519 int x, y, wi, he; 2520 2521 wi = ri->ri_font->fontwidth; 2522 he = ri->ri_font->fontheight; 2523 2524 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2525 x = ri->ri_ccol * wi + ri->ri_xorigin; 2526 y = ri->ri_crow * he + ri->ri_yorigin; 2527 /* first turn off the old cursor */ 2528 if (ri->ri_flg & RI_CURSOR) { 2529 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2530 RADEON_ROP3_Dn, 0xffffffff); 2531 ri->ri_flg &= ~RI_CURSOR; 2532 } 2533 ri->ri_crow = row; 2534 ri->ri_ccol = col; 2535 /* then (possibly) turn on the new one */ 2536 if (on) { 2537 x = ri->ri_ccol * wi + ri->ri_xorigin; 2538 y = ri->ri_crow * he + ri->ri_yorigin; 2539 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2540 RADEON_ROP3_Dn, 0xffffffff); 2541 ri->ri_flg |= RI_CURSOR; 2542 } 2543 } else { 2544 scr->scr_ri.ri_crow = row; 2545 scr->scr_ri.ri_ccol = col; 2546 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2547 } 2548 } 2549 2550 static int 2551 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2552 { 2553 if ((fg == 0) && (bg == 0)) { 2554 fg = WS_DEFAULT_FG; 2555 bg = WS_DEFAULT_BG; 2556 } 2557 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2558 return 0; 2559 } 2560 2561 /* 2562 * Underlying acceleration support. 2563 */ 2564 static void 2565 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2566 int height, uint32_t fg, uint32_t bg) 2567 { 2568 struct radeonfb_softc *sc = dp->rd_softc; 2569 uint32_t gmc; 2570 uint32_t padded_width = (width+7) & 0xfff8; 2571 uint32_t topleft, bottomright; 2572 2573 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2574 2575 if (width != padded_width) { 2576 2577 radeonfb_wait_fifo(sc, 2); 2578 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2579 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2580 ((xd + width) & 0x1fff); 2581 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2582 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2583 } 2584 2585 radeonfb_wait_fifo(sc, 5); 2586 2587 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2588 RADEON_GMC_BRUSH_NONE | 2589 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2590 //RADEON_GMC_BYTE_LSB_TO_MSB | 2591 RADEON_GMC_DST_CLIPPING | 2592 RADEON_ROP3_S | 2593 RADEON_DP_SRC_SOURCE_HOST_DATA | 2594 RADEON_GMC_CLR_CMP_CNTL_DIS | 2595 RADEON_GMC_WR_MSK_DIS | 2596 gmc); 2597 2598 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2599 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2600 2601 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2602 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2603 2604 } 2605 2606 static void 2607 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2608 { 2609 struct radeonfb_softc *sc = dp->rd_softc; 2610 int i; 2611 uint32_t latch = 0; 2612 int shift = 0; 2613 2614 for (i = 0; i < count; i++) { 2615 latch |= (data[i] << shift); 2616 if (shift == 24) { 2617 radeonfb_wait_fifo(sc, 1); 2618 PUT32(sc, RADEON_HOST_DATA0, latch); 2619 latch = 0; 2620 shift = 0; 2621 } else 2622 shift += 8; 2623 } 2624 if (shift != 0) { 2625 radeonfb_wait_fifo(sc, 1); 2626 PUT32(sc, RADEON_HOST_DATA0, latch); 2627 } 2628 radeonfb_unclip(sc); 2629 } 2630 2631 static void 2632 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2633 int width, int height, uint32_t color) 2634 { 2635 struct radeonfb_softc *sc = dp->rd_softc; 2636 uint32_t gmc; 2637 2638 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2639 2640 radeonfb_wait_fifo(sc, 6); 2641 2642 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2643 RADEON_GMC_BRUSH_SOLID_COLOR | 2644 RADEON_GMC_SRC_DATATYPE_COLOR | 2645 RADEON_GMC_CLR_CMP_CNTL_DIS | 2646 RADEON_ROP3_P | gmc); 2647 2648 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2649 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2650 PUT32(sc, RADEON_DP_CNTL, 2651 RADEON_DST_X_LEFT_TO_RIGHT | 2652 RADEON_DST_Y_TOP_TO_BOTTOM); 2653 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2654 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2655 2656 /* 2657 * XXX: we don't wait for the fifo to empty -- that would slow 2658 * things down! The linux radeonfb driver waits, but xfree doesn't 2659 */ 2660 /* XXX: for now we do, to make it safe for direct drawing */ 2661 radeonfb_engine_idle(sc); 2662 } 2663 2664 static void 2665 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2666 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2667 { 2668 struct radeonfb_softc *sc = dp->rd_softc; 2669 uint32_t gmc; 2670 uint32_t dir; 2671 2672 if (dsty < srcy) { 2673 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2674 } else { 2675 srcy += height - 1; 2676 dsty += height - 1; 2677 dir = 0; 2678 } 2679 if (dstx < srcx) { 2680 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2681 } else { 2682 srcx += width - 1; 2683 dstx += width - 1; 2684 } 2685 2686 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2687 2688 radeonfb_wait_fifo(sc, 6); 2689 2690 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2691 //RADEON_GMC_SRC_CLIPPING | 2692 RADEON_GMC_BRUSH_SOLID_COLOR | 2693 RADEON_GMC_SRC_DATATYPE_COLOR | 2694 RADEON_GMC_CLR_CMP_CNTL_DIS | 2695 RADEON_DP_SRC_SOURCE_MEMORY | 2696 rop | gmc); 2697 2698 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2699 PUT32(sc, RADEON_DP_CNTL, dir); 2700 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2701 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2702 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2703 2704 /* 2705 * XXX: we don't wait for the fifo to empty -- that would slow 2706 * things down! The linux radeonfb driver waits, but xfree doesn't 2707 */ 2708 /* XXX: for now we do, to make it safe for direct drawing */ 2709 radeonfb_engine_idle(sc); 2710 } 2711 2712 static void 2713 radeonfb_engine_idle(struct radeonfb_softc *sc) 2714 { 2715 int i; 2716 2717 radeonfb_wait_fifo(sc, 64); 2718 for (i = RADEON_TIMEOUT; i; i--) { 2719 if ((GET32(sc, RADEON_RBBM_STATUS) & 2720 RADEON_RBBM_ACTIVE) == 0) { 2721 radeonfb_engine_flush(sc); 2722 break; 2723 } 2724 } 2725 } 2726 2727 static void 2728 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2729 { 2730 int i; 2731 2732 for (i = RADEON_TIMEOUT; i; i--) { 2733 if ((GET32(sc, RADEON_RBBM_STATUS) & 2734 RADEON_RBBM_FIFOCNT_MASK) >= n) 2735 return; 2736 } 2737 #ifdef DIAGNOSTIC 2738 if (!i) 2739 printf("%s: timed out waiting for fifo (%x)\n", 2740 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2741 #endif 2742 } 2743 2744 static void 2745 radeonfb_engine_flush(struct radeonfb_softc *sc) 2746 { 2747 int i; 2748 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2749 for (i = RADEON_TIMEOUT; i; i--) { 2750 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2751 RADEON_RB2D_DC_BUSY) == 0) 2752 break; 2753 } 2754 #ifdef DIAGNOSTIC 2755 if (!i) 2756 printf("%s: engine flush timed out!\n", XNAME(sc)); 2757 #endif 2758 } 2759 2760 static inline void 2761 radeonfb_unclip(struct radeonfb_softc *sc) 2762 { 2763 2764 radeonfb_wait_fifo(sc, 2); 2765 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2766 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2767 } 2768 2769 static void 2770 radeonfb_engine_init(struct radeonfb_display *dp) 2771 { 2772 struct radeonfb_softc *sc = dp->rd_softc; 2773 uint32_t pitch; 2774 volatile uint32_t junk; 2775 2776 /* no 3D */ 2777 PUT32(sc, RADEON_RB3D_CNTL, 0); 2778 2779 radeonfb_engine_reset(sc); 2780 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2781 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2782 2783 radeonfb_wait_fifo(sc, 1); 2784 if (!IS_R300(sc)) 2785 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2786 2787 radeonfb_wait_fifo(sc, 3); 2788 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2789 (pitch << 22) | (sc->sc_aperbase >> 10)); 2790 2791 2792 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2793 (pitch << 22) | (sc->sc_aperbase >> 10)); 2794 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2795 (pitch << 22) | (sc->sc_aperbase >> 10)); 2796 2797 radeonfb_wait_fifo(sc, 1); 2798 #if _BYTE_ORDER == _BIG_ENDIAN 2799 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2800 #else 2801 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2802 #endif 2803 junk = GET32(sc, RADEON_DP_DATATYPE); 2804 2805 /* default scissors -- no clipping */ 2806 radeonfb_wait_fifo(sc, 1); 2807 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2808 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2809 2810 radeonfb_wait_fifo(sc, 1); 2811 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2812 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2813 RADEON_GMC_CLR_CMP_CNTL_DIS | 2814 RADEON_GMC_BRUSH_SOLID_COLOR | 2815 RADEON_GMC_SRC_DATATYPE_COLOR); 2816 2817 radeonfb_wait_fifo(sc, 7); 2818 PUT32(sc, RADEON_DST_LINE_START, 0); 2819 PUT32(sc, RADEON_DST_LINE_END, 0); 2820 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2821 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2822 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2823 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2824 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2825 2826 radeonfb_engine_idle(sc); 2827 } 2828 2829 static void 2830 radeonfb_engine_reset(struct radeonfb_softc *sc) 2831 { 2832 uint32_t hpc, rbbm, mclkcntl, clkindex; 2833 2834 radeonfb_engine_flush(sc); 2835 2836 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2837 if (HAS_R300CG(sc)) 2838 radeonfb_r300cg_workaround(sc); 2839 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2840 2841 /* 2842 * According to comments in XFree code, resetting the HDP via 2843 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2844 * So we use HOST_PATH_CNTL instead. 2845 */ 2846 2847 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2848 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2849 if (IS_R300(sc)) { 2850 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2851 RADEON_SOFT_RESET_CP | 2852 RADEON_SOFT_RESET_HI | 2853 RADEON_SOFT_RESET_E2); 2854 GET32(sc, RADEON_RBBM_SOFT_RESET); 2855 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2856 /* 2857 * XXX: this bit is not defined in any ATI docs I have, 2858 * nor in the XFree code, but XFree does it. Why? 2859 */ 2860 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2861 } else { 2862 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2863 RADEON_SOFT_RESET_CP | 2864 RADEON_SOFT_RESET_SE | 2865 RADEON_SOFT_RESET_RE | 2866 RADEON_SOFT_RESET_PP | 2867 RADEON_SOFT_RESET_E2 | 2868 RADEON_SOFT_RESET_RB); 2869 GET32(sc, RADEON_RBBM_SOFT_RESET); 2870 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2871 ~(RADEON_SOFT_RESET_CP | 2872 RADEON_SOFT_RESET_SE | 2873 RADEON_SOFT_RESET_RE | 2874 RADEON_SOFT_RESET_PP | 2875 RADEON_SOFT_RESET_E2 | 2876 RADEON_SOFT_RESET_RB)); 2877 GET32(sc, RADEON_RBBM_SOFT_RESET); 2878 } 2879 2880 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2881 GET32(sc, RADEON_HOST_PATH_CNTL); 2882 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2883 2884 if (IS_R300(sc)) 2885 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2886 2887 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2888 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2889 2890 if (HAS_R300CG(sc)) 2891 radeonfb_r300cg_workaround(sc); 2892 } 2893 2894 static int 2895 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2896 { 2897 int x, y; 2898 2899 x = pos->x; 2900 y = pos->y; 2901 2902 /* 2903 * This doesn't let a cursor move off the screen. I'm not 2904 * sure if this will have negative effects for e.g. Xinerama. 2905 * I'd guess Xinerama handles it by changing the cursor shape, 2906 * but that needs verification. 2907 */ 2908 if (x >= dp->rd_virtx) 2909 x = dp->rd_virtx - 1; 2910 if (x < 0) 2911 x = 0; 2912 if (y >= dp->rd_virty) 2913 y = dp->rd_virty - 1; 2914 if (y < 0) 2915 y = 0; 2916 2917 dp->rd_cursor.rc_pos.x = x; 2918 dp->rd_cursor.rc_pos.y = y; 2919 2920 radeonfb_cursor_position(dp); 2921 return 0; 2922 } 2923 2924 static int 2925 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2926 { 2927 unsigned flags; 2928 2929 uint8_t r[2], g[2], b[2]; 2930 unsigned index, count; 2931 int i, err; 2932 int pitch, size; 2933 struct radeonfb_cursor nc; 2934 2935 flags = wc->which; 2936 2937 /* copy old values */ 2938 nc = dp->rd_cursor; 2939 2940 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2941 index = wc->cmap.index; 2942 count = wc->cmap.count; 2943 2944 if (index >= 2 || (index + count) > 2) 2945 return EINVAL; 2946 2947 err = copyin(wc->cmap.red, &r[index], count); 2948 if (err) 2949 return err; 2950 err = copyin(wc->cmap.green, &g[index], count); 2951 if (err) 2952 return err; 2953 err = copyin(wc->cmap.blue, &b[index], count); 2954 if (err) 2955 return err; 2956 2957 for (i = index; i < index + count; i++) { 2958 nc.rc_cmap[i] = 2959 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2960 } 2961 } 2962 2963 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2964 if ((wc->size.x > RADEON_CURSORMAXX) || 2965 (wc->size.y > RADEON_CURSORMAXY)) 2966 return EINVAL; 2967 2968 /* figure bytes per line */ 2969 pitch = (wc->size.x + 7) / 8; 2970 size = pitch * wc->size.y; 2971 2972 /* clear the old cursor and mask */ 2973 memset(nc.rc_image, 0, 512); 2974 memset(nc.rc_mask, 0, 512); 2975 2976 nc.rc_size = wc->size; 2977 2978 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2979 return err; 2980 2981 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2982 return err; 2983 } 2984 2985 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2986 nc.rc_hot = wc->hot; 2987 if (nc.rc_hot.x >= nc.rc_size.x) 2988 nc.rc_hot.x = nc.rc_size.x - 1; 2989 if (nc.rc_hot.y >= nc.rc_size.y) 2990 nc.rc_hot.y = nc.rc_size.y - 1; 2991 } 2992 2993 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2994 nc.rc_pos = wc->pos; 2995 if (nc.rc_pos.x >= dp->rd_virtx) 2996 nc.rc_pos.x = dp->rd_virtx - 1; 2997 #if 0 2998 if (nc.rc_pos.x < 0) 2999 nc.rc_pos.x = 0; 3000 #endif 3001 if (nc.rc_pos.y >= dp->rd_virty) 3002 nc.rc_pos.y = dp->rd_virty - 1; 3003 #if 0 3004 if (nc.rc_pos.y < 0) 3005 nc.rc_pos.y = 0; 3006 #endif 3007 } 3008 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3009 nc.rc_visible = wc->enable; 3010 } 3011 3012 dp->rd_cursor = nc; 3013 radeonfb_cursor_update(dp, wc->which); 3014 3015 return 0; 3016 } 3017 3018 /* 3019 * Change the cursor shape. Call this with the cursor locked to avoid 3020 * flickering/tearing. 3021 */ 3022 static void 3023 radeonfb_cursor_shape(struct radeonfb_display *dp) 3024 { 3025 uint8_t and[512], xor[512]; 3026 int i, j, src, dst, pitch; 3027 const uint8_t *msk = dp->rd_cursor.rc_mask; 3028 const uint8_t *img = dp->rd_cursor.rc_image; 3029 3030 /* 3031 * Radeon cursor data interleaves one line of AND data followed 3032 * by a line of XOR data. (Each line corresponds to a whole hardware 3033 * pitch - i.e. 64 pixels or 8 bytes.) 3034 * 3035 * The cursor is displayed using the following table: 3036 * 3037 * AND XOR Result 3038 * ---------------------- 3039 * 0 0 Cursor color 0 3040 * 0 1 Cursor color 1 3041 * 1 0 Transparent 3042 * 1 1 Complement of background 3043 * 3044 * Our masks are therefore different from what we were passed. 3045 * Passed in, I'm assuming the data represents either color 0 or 1, 3046 * and a mask, so the passed in table looks like: 3047 * 3048 * IMG Mask Result 3049 * ----------------------- 3050 * 0 0 Transparent 3051 * 0 1 Cursor color 0 3052 * 1 0 Transparent 3053 * 1 1 Cursor color 1 3054 * 3055 * IF mask bit == 1, AND = 0, XOR = color. 3056 * IF mask bit == 0, AND = 1, XOR = 0. 3057 * 3058 * hence: AND = ~(mask); XOR = color & ~(mask); 3059 */ 3060 3061 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3062 3063 /* start by assuming all bits are transparent */ 3064 memset(and, 0xff, 512); 3065 memset(xor, 0x00, 512); 3066 3067 src = 0; 3068 dst = 0; 3069 for (i = 0; i < 64; i++) { 3070 for (j = 0; j < 64; j += 8) { 3071 if ((i < dp->rd_cursor.rc_size.y) && 3072 (j < dp->rd_cursor.rc_size.x)) { 3073 3074 /* take care to leave odd bits alone */ 3075 and[dst] &= ~(msk[src]); 3076 xor[dst] = img[src] & msk[src]; 3077 src++; 3078 } 3079 dst++; 3080 } 3081 } 3082 3083 /* copy the image into place */ 3084 for (i = 0; i < 64; i++) { 3085 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3086 &and[i * 8], 8); 3087 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3088 &xor[i * 8], 8); 3089 } 3090 } 3091 3092 static void 3093 radeonfb_cursor_position(struct radeonfb_display *dp) 3094 { 3095 struct radeonfb_softc *sc = dp->rd_softc; 3096 uint32_t offset, hvoff, hvpos; /* registers */ 3097 uint32_t coff; /* cursor offset */ 3098 int i, x, y, xoff, yoff, crtcoff; 3099 3100 /* 3101 * XXX: this also needs to handle pan/scan 3102 */ 3103 for (i = 0; i < dp->rd_ncrtcs; i++) { 3104 3105 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3106 3107 if (rcp->rc_number) { 3108 offset = RADEON_CUR2_OFFSET; 3109 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3110 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3111 crtcoff = RADEON_CRTC2_OFFSET; 3112 } else { 3113 offset = RADEON_CUR_OFFSET; 3114 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3115 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3116 crtcoff = RADEON_CRTC_OFFSET; 3117 } 3118 3119 x = dp->rd_cursor.rc_pos.x; 3120 y = dp->rd_cursor.rc_pos.y; 3121 3122 while (y < rcp->rc_yoffset) { 3123 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3124 } 3125 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3126 rcp->rc_yoffset += RADEON_PANINCREMENT; 3127 } 3128 while (x < rcp->rc_xoffset) { 3129 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3130 } 3131 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3132 rcp->rc_xoffset += RADEON_PANINCREMENT; 3133 } 3134 3135 /* adjust for the cursor's hotspot */ 3136 x -= dp->rd_cursor.rc_hot.x; 3137 y -= dp->rd_cursor.rc_hot.y; 3138 xoff = yoff = 0; 3139 3140 if (x >= dp->rd_virtx) 3141 x = dp->rd_virtx - 1; 3142 if (y >= dp->rd_virty) 3143 y = dp->rd_virty - 1; 3144 3145 /* now adjust cursor so it is relative to viewport */ 3146 x -= rcp->rc_xoffset; 3147 y -= rcp->rc_yoffset; 3148 3149 /* 3150 * no need to check for fall off, because we should 3151 * never move off the screen entirely! 3152 */ 3153 coff = 0; 3154 if (x < 0) { 3155 xoff = -x; 3156 x = 0; 3157 } 3158 if (y < 0) { 3159 yoff = -y; 3160 y = 0; 3161 coff = (yoff * 2) * 8; 3162 } 3163 3164 /* pan the display */ 3165 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3166 rcp->rc_xoffset); 3167 3168 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3169 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3170 /* NB: this unlocks the cursor */ 3171 PUT32(sc, hvpos, (x << 16) | y); 3172 } 3173 } 3174 3175 static void 3176 radeonfb_cursor_visible(struct radeonfb_display *dp) 3177 { 3178 int i; 3179 uint32_t gencntl, bit; 3180 3181 for (i = 0; i < dp->rd_ncrtcs; i++) { 3182 if (dp->rd_crtcs[i].rc_number) { 3183 gencntl = RADEON_CRTC2_GEN_CNTL; 3184 bit = RADEON_CRTC2_CUR_EN; 3185 } else { 3186 gencntl = RADEON_CRTC_GEN_CNTL; 3187 bit = RADEON_CRTC_CUR_EN; 3188 } 3189 3190 if (dp->rd_cursor.rc_visible) 3191 SET32(dp->rd_softc, gencntl, bit); 3192 else 3193 CLR32(dp->rd_softc, gencntl, bit); 3194 } 3195 } 3196 3197 static void 3198 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3199 { 3200 int i; 3201 uint32_t c0reg, c1reg; 3202 struct radeonfb_softc *sc = dp->rd_softc; 3203 3204 for (i = 0; i < dp->rd_ncrtcs; i++) { 3205 if (dp->rd_crtcs[i].rc_number) { 3206 c0reg = RADEON_CUR2_CLR0; 3207 c1reg = RADEON_CUR2_CLR1; 3208 } else { 3209 c0reg = RADEON_CUR_CLR0; 3210 c1reg = RADEON_CUR_CLR1; 3211 } 3212 3213 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3214 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3215 } 3216 } 3217 3218 static void 3219 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3220 { 3221 struct radeonfb_softc *sc; 3222 int i; 3223 3224 sc = dp->rd_softc; 3225 for (i = 0; i < dp->rd_ncrtcs; i++) { 3226 if (dp->rd_crtcs[i].rc_number) { 3227 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3228 } else { 3229 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3230 } 3231 } 3232 3233 if (which & WSDISPLAY_CURSOR_DOCMAP) 3234 radeonfb_cursor_cmap(dp); 3235 3236 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3237 radeonfb_cursor_shape(dp); 3238 3239 if (which & WSDISPLAY_CURSOR_DOCUR) 3240 radeonfb_cursor_visible(dp); 3241 3242 /* this one is unconditional, because it updates other stuff */ 3243 radeonfb_cursor_position(dp); 3244 } 3245 3246 static struct videomode * 3247 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3248 { 3249 int r1, r2; 3250 3251 /* otherwise pick the higher refresh rate */ 3252 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3253 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3254 3255 return (r1 < r2 ? m2 : m1); 3256 } 3257 3258 static const struct videomode * 3259 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3260 int x, int y) 3261 { 3262 struct edid_info *ep = &rp->rp_edid; 3263 struct videomode *vmp = NULL; 3264 int i; 3265 3266 if (!rp->rp_edid_valid) { 3267 /* fallback to safe mode */ 3268 return radeonfb_modelookup(sc->sc_defaultmode); 3269 } 3270 3271 /* always choose the preferred mode first! */ 3272 if (ep->edid_preferred_mode) { 3273 3274 /* XXX: add auto-stretching support for native mode */ 3275 3276 /* this may want panning to occur, btw */ 3277 if ((ep->edid_preferred_mode->hdisplay <= x) && 3278 (ep->edid_preferred_mode->vdisplay <= y)) 3279 return ep->edid_preferred_mode; 3280 } 3281 3282 for (i = 0; i < ep->edid_nmodes; i++) { 3283 /* 3284 * We elect to pick a resolution that is too large for 3285 * the monitor than one that is too small. This means 3286 * that we will prefer to pan rather than to try to 3287 * center a smaller display on a larger screen. In 3288 * practice, this shouldn't matter because if a 3289 * monitor can support a larger resolution, it can 3290 * probably also support the smaller. A specific 3291 * exception is fixed format panels, but hopefully 3292 * they are properly dealt with by the "autostretch" 3293 * logic above. 3294 */ 3295 if ((ep->edid_modes[i].hdisplay > x) || 3296 (ep->edid_modes[i].vdisplay > y)) { 3297 continue; 3298 } 3299 3300 /* 3301 * at this point, the display mode is no larger than 3302 * what we've requested. 3303 */ 3304 if (vmp == NULL) 3305 vmp = &ep->edid_modes[i]; 3306 3307 /* eliminate smaller modes */ 3308 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3309 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3310 continue; 3311 3312 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3313 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3314 vmp = &ep->edid_modes[i]; 3315 continue; 3316 } 3317 3318 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3319 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3320 3321 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3322 } 3323 3324 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3325 } 3326 3327 static int 3328 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3329 { 3330 int i; 3331 3332 for (i = 0; i < nlist; i++) { 3333 if ((x == list[i].hdisplay) && 3334 (y == list[i].vdisplay)) { 3335 return 1; 3336 } 3337 } 3338 return 0; 3339 } 3340 3341 static void 3342 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3343 int pan) 3344 { 3345 struct radeonfb_port *rp; 3346 struct edid_info *ep; 3347 int i, j; 3348 3349 *x = 0; 3350 *y = 0; 3351 3352 if (pan) { 3353 for (i = 0; i < dp->rd_ncrtcs; i++) { 3354 rp = dp->rd_crtcs[i].rc_port; 3355 ep = &rp->rp_edid; 3356 if (!rp->rp_edid_valid) { 3357 /* monitor not present */ 3358 continue; 3359 } 3360 3361 /* 3362 * For now we are ignoring "conflict" that 3363 * could occur when mixing some modes like 3364 * 1280x1024 and 1400x800. It isn't clear 3365 * which is better, so the first one wins. 3366 */ 3367 for (j = 0; j < ep->edid_nmodes; j++) { 3368 /* 3369 * ignore resolutions that are too big for 3370 * the radeon 3371 */ 3372 if (ep->edid_modes[j].hdisplay > 3373 dp->rd_softc->sc_maxx) 3374 continue; 3375 if (ep->edid_modes[j].vdisplay > 3376 dp->rd_softc->sc_maxy) 3377 continue; 3378 3379 /* 3380 * pick largest resolution, the 3381 * smaller monitor will pan 3382 */ 3383 if ((ep->edid_modes[j].hdisplay >= *x) && 3384 (ep->edid_modes[j].vdisplay >= *y)) { 3385 *x = ep->edid_modes[j].hdisplay; 3386 *y = ep->edid_modes[j].vdisplay; 3387 } 3388 } 3389 } 3390 3391 } else { 3392 struct videomode modes[64]; 3393 int nmodes = 0; 3394 int valid = 0; 3395 3396 for (i = 0; i < dp->rd_ncrtcs; i++) { 3397 /* 3398 * pick the largest resolution in common. 3399 */ 3400 rp = dp->rd_crtcs[i].rc_port; 3401 ep = &rp->rp_edid; 3402 3403 if (!rp->rp_edid_valid) 3404 continue; 3405 3406 if (!valid) { 3407 /* 3408 * Pick the preferred mode for this port 3409 * if available. 3410 */ 3411 if (ep->edid_preferred_mode) { 3412 struct videomode *vmp = 3413 ep->edid_preferred_mode; 3414 3415 if ((vmp->hdisplay <= 3416 dp->rd_softc->sc_maxx) && 3417 (vmp->vdisplay <= 3418 dp->rd_softc->sc_maxy)) 3419 modes[nmodes++] = *vmp; 3420 } else { 3421 3422 /* initialize starting list */ 3423 for (j = 0; j < ep->edid_nmodes; j++) { 3424 /* 3425 * ignore resolutions that are 3426 * too big for the radeon 3427 */ 3428 if (ep->edid_modes[j].hdisplay > 3429 dp->rd_softc->sc_maxx) 3430 continue; 3431 if (ep->edid_modes[j].vdisplay > 3432 dp->rd_softc->sc_maxy) 3433 continue; 3434 3435 modes[nmodes] = 3436 ep->edid_modes[j]; 3437 nmodes++; 3438 } 3439 } 3440 valid = 1; 3441 } else { 3442 /* merge into preexisting list */ 3443 for (j = 0; j < nmodes; j++) { 3444 if (!radeonfb_hasres(ep->edid_modes, 3445 ep->edid_nmodes, 3446 modes[j].hdisplay, 3447 modes[j].vdisplay)) { 3448 modes[j] = modes[nmodes]; 3449 j--; 3450 nmodes--; 3451 } 3452 } 3453 } 3454 } 3455 3456 /* now we have to pick from the merged list */ 3457 for (i = 0; i < nmodes; i++) { 3458 if ((modes[i].hdisplay >= *x) && 3459 (modes[i].vdisplay >= *y)) { 3460 *x = modes[i].hdisplay; 3461 *y = modes[i].vdisplay; 3462 } 3463 } 3464 } 3465 3466 if ((*x == 0) || (*y == 0)) { 3467 /* fallback to safe mode */ 3468 *x = 640; 3469 *y = 480; 3470 } 3471 } 3472 3473 /* 3474 * backlight levels are linear on: 3475 * - RV200, RV250, RV280, RV350 3476 * - but NOT on PowerBook4,3 6,3 6,5 3477 * according to Linux' radeonfb 3478 */ 3479 3480 /* Get the current backlight level for the display. */ 3481 3482 static int 3483 radeonfb_get_backlight(struct radeonfb_display *dp) 3484 { 3485 int s; 3486 uint32_t level; 3487 3488 s = spltty(); 3489 3490 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3491 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3492 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3493 3494 /* 3495 * On some chips, we should negate the backlight level. 3496 * XXX Find out on which chips. 3497 */ 3498 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3499 level = RADEONFB_BACKLIGHT_MAX - level; 3500 3501 splx(s); 3502 3503 return level; 3504 } 3505 3506 /* Set the backlight to the given level for the display. */ 3507 3508 static int 3509 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3510 { 3511 struct radeonfb_softc *sc; 3512 int rlevel, s; 3513 uint32_t lvds; 3514 3515 s = spltty(); 3516 3517 if (level < 0) 3518 level = 0; 3519 else if (level >= RADEONFB_BACKLIGHT_MAX) 3520 level = RADEONFB_BACKLIGHT_MAX; 3521 3522 sc = dp->rd_softc; 3523 3524 /* On some chips, we should negate the backlight level. */ 3525 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3526 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3527 } else 3528 rlevel = level; 3529 3530 callout_stop(&dp->rd_bl_lvds_co); 3531 radeonfb_engine_idle(sc); 3532 3533 /* 3534 * Turn off the display if the backlight is set to 0, since the 3535 * display is useless without backlight anyway. 3536 */ 3537 if (level == 0) 3538 radeonfb_blank(dp, 1); 3539 else if (radeonfb_get_backlight(dp) == 0) 3540 radeonfb_blank(dp, 0); 3541 3542 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3543 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3544 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3545 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3546 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3547 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3548 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3549 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3550 lvds |= RADEON_LVDS_ON; 3551 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3552 } else { 3553 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3554 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3555 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3556 } 3557 3558 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3559 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3560 /* XXX What is the correct delay? */ 3561 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3562 3563 splx(s); 3564 3565 return 0; 3566 } 3567 3568 /* 3569 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3570 * Set the delayed bits in the register, and clear the stored delayed 3571 * value. 3572 */ 3573 3574 static void radeonfb_lvds_callout(void *arg) 3575 { 3576 struct radeonfb_display *dp = arg; 3577 int s; 3578 3579 s = splhigh(); 3580 3581 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3582 dp->rd_bl_lvds_val); 3583 dp->rd_bl_lvds_val = 0; 3584 3585 splx(s); 3586 } 3587 3588 static void 3589 radeonfb_brightness_up(device_t dev) 3590 { 3591 struct radeonfb_softc *sc = device_private(dev); 3592 int level; 3593 3594 /* we assume the main display is the first one - need a better way */ 3595 if (sc->sc_ndisplays < 1) return; 3596 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3597 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3598 radeonfb_set_backlight(&sc->sc_displays[0], level); 3599 } 3600 3601 static void 3602 radeonfb_brightness_down(device_t dev) 3603 { 3604 struct radeonfb_softc *sc = device_private(dev); 3605 int level; 3606 3607 /* we assume the main display is the first one - need a better way */ 3608 if (sc->sc_ndisplays < 1) return; 3609 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3610 level = max(0, level - 5); 3611 radeonfb_set_backlight(&sc->sc_displays[0], level); 3612 } 3613