1 /* $NetBSD: radeonfb.c,v 1.79 2013/10/09 17:18:23 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.79 2013/10/09 17:18:23 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 174 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 175 #endif 176 177 static int radeonfb_set_backlight(struct radeonfb_display *, int); 178 static int radeonfb_get_backlight(struct radeonfb_display *); 179 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 180 static void radeonfb_lvds_callout(void *); 181 182 static void radeonfb_brightness_up(device_t); 183 static void radeonfb_brightness_down(device_t); 184 185 static struct videomode *radeonfb_best_refresh(struct videomode *, 186 struct videomode *); 187 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 188 uint16_t *, int); 189 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 190 struct radeonfb_port *, int, int); 191 192 static int radeonfb_drm_print(void *, const char *); 193 194 #ifdef RADEONFB_DEBUG 195 int radeon_debug = 1; 196 #define DPRINTF(x) \ 197 if (radeon_debug) printf x 198 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 199 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 200 #else 201 #define DPRINTF(x) 202 #define PRINTREG(r) 203 #define PRINTPLL(r) 204 #endif 205 206 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 207 208 #ifndef RADEON_DEFAULT_MODE 209 /* any reasonably modern display should handle this */ 210 #define RADEON_DEFAULT_MODE "1024x768x60" 211 #endif 212 213 extern const u_char rasops_cmap[768]; 214 215 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 216 217 static struct { 218 int size; /* minimum memory size (MB) */ 219 int maxx; /* maximum x dimension */ 220 int maxy; /* maximum y dimension */ 221 int maxbpp; /* maximum bpp */ 222 int maxdisp; /* maximum logical display count */ 223 } radeonfb_limits[] = { 224 { 32, 2048, 1536, 32, 2 }, 225 { 16, 1600, 1200, 32, 2 }, 226 { 8, 1600, 1200, 32, 1 }, 227 { 0, 0, 0, 0, 0 }, 228 }; 229 230 static struct wsscreen_descr radeonfb_stdscreen = { 231 "fb", /* name */ 232 0, 0, /* ncols, nrows */ 233 NULL, /* textops */ 234 8, 16, /* fontwidth, fontheight */ 235 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 236 0, /* modecookie */ 237 }; 238 239 struct wsdisplay_accessops radeonfb_accessops = { 240 radeonfb_ioctl, 241 radeonfb_mmap, 242 NULL, /* vcons_alloc_screen */ 243 NULL, /* vcons_free_screen */ 244 NULL, /* vcons_show_screen */ 245 NULL, /* load_font */ 246 NULL, /* pollc */ 247 NULL, /* scroll */ 248 }; 249 250 static struct { 251 uint16_t devid; 252 uint16_t family; 253 uint16_t flags; 254 } radeonfb_devices[] = 255 { 256 /* R100 family */ 257 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 261 262 /* RV100 family */ 263 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 267 268 /* RS100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 271 272 /* RS200/RS250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 277 278 /* R200 family */ 279 /* add more R200 products? , 5148 */ 280 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 285 286 /* RV200 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 291 292 /* RV250 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 298 299 /* RS300 family */ 300 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 304 305 /* RV280 family */ 306 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 313 314 /* R300 family */ 315 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 323 324 /* RV350/RV360 family */ 325 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 337 338 /* R350/R360 family */ 339 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 347 348 /* RV380/RV370 family */ 349 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 359 360 #if notyet 361 /* R420/R423 family */ 362 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 379 #endif 380 { 0, 0, 0 } 381 }; 382 383 static struct { 384 int divider; 385 int mask; 386 } radeonfb_dividers[] = { 387 { 16, 5 }, 388 { 12, 7 }, 389 { 8, 3 }, 390 { 6, 6 }, 391 { 4, 2 }, 392 { 3, 4 }, 393 { 2, 1 }, 394 { 1, 0 }, 395 { 0, 0 } 396 }; 397 398 /* 399 * This table taken from X11. 400 */ 401 static const struct { 402 int family; 403 struct radeon_tmds_pll plls[4]; 404 } radeonfb_tmds_pll[] = { 405 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_RS100, {{0, 0}}}, 408 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 411 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 412 { RADEON_RS300, {{0, 0}}}, 413 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 414 { RADEON_R300, {{-1, 0xb01cb}}}, 415 { RADEON_R350, {{-1, 0xb01cb}}}, 416 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 417 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 418 { RADEON_R420, {{-1, 0xb01cb}}}, 419 }; 420 421 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 422 423 424 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 425 radeonfb_match, radeonfb_attach, NULL, NULL); 426 427 static int 428 radeonfb_match(device_t parent, cfdata_t match, void *aux) 429 { 430 const struct pci_attach_args *pa = aux; 431 int i; 432 433 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 434 return 0; 435 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 438 return 100; /* high to defeat VGA/VESA */ 439 } 440 441 return 0; 442 } 443 444 static void 445 radeonfb_attach(device_t parent, device_t dev, void *aux) 446 { 447 struct radeonfb_softc *sc = device_private(dev); 448 const struct pci_attach_args *pa = aux; 449 const char *mptr; 450 bus_size_t bsz; 451 pcireg_t screg; 452 int i, j, fg, bg, ul, flags; 453 uint32_t v; 454 455 sc->sc_dev = dev; 456 sc->sc_id = pa->pa_id; 457 for (i = 0; radeonfb_devices[i].devid; i++) { 458 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 459 break; 460 } 461 462 pci_aprint_devinfo(pa, NULL); 463 464 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 465 466 KASSERT(radeonfb_devices[i].devid != 0); 467 sc->sc_pt = pa->pa_tag; 468 sc->sc_iot = pa->pa_iot; 469 sc->sc_pc = pa->pa_pc; 470 sc->sc_family = radeonfb_devices[i].family; 471 sc->sc_flags = radeonfb_devices[i].flags; 472 473 /* enable memory and IO access */ 474 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 475 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 476 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 477 478 /* 479 * Some flags are general to entire chip families, and rather 480 * than clutter up the table with them, we go ahead and set 481 * them here. 482 */ 483 switch (sc->sc_family) { 484 case RADEON_RS100: 485 case RADEON_RS200: 486 sc->sc_flags |= RFB_IGP | RFB_RV100; 487 break; 488 489 case RADEON_RV100: 490 case RADEON_RV200: 491 case RADEON_RV250: 492 case RADEON_RV280: 493 sc->sc_flags |= RFB_RV100; 494 break; 495 496 case RADEON_RS300: 497 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 498 break; 499 500 case RADEON_R300: 501 case RADEON_RV350: 502 case RADEON_R350: 503 case RADEON_RV380: 504 case RADEON_R420: 505 /* newer chips */ 506 sc->sc_flags |= RFB_R300; 507 break; 508 509 case RADEON_R100: 510 sc->sc_flags |= RFB_NCRTC2; 511 break; 512 } 513 514 if ((sc->sc_family == RADEON_RV200) || 515 (sc->sc_family == RADEON_RV250) || 516 (sc->sc_family == RADEON_RV280) || 517 (sc->sc_family == RADEON_RV350)) { 518 bool inverted = 0; 519 /* backlight level is linear */ 520 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 521 prop_dictionary_get_bool(device_properties(sc->sc_dev), 522 "backlight_level_reverted", &inverted); 523 if (inverted) { 524 DPRINTF(("nope, it's inverted\n")); 525 sc->sc_flags |= RFB_INV_BLIGHT; 526 } 527 } else 528 sc->sc_flags |= RFB_INV_BLIGHT; 529 530 /* 531 * XXX: to support true multihead, this must change. 532 */ 533 sc->sc_ndisplays = 1; 534 535 /* XXX: */ 536 if (!HAS_CRTC2(sc)) { 537 sc->sc_ndisplays = 1; 538 } 539 540 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 541 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 542 &sc->sc_regsz) != 0) { 543 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 544 goto error; 545 } 546 547 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 548 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 549 { 550 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 551 goto error; 552 } 553 sc->sc_romt = sc->sc_memt; 554 555 sc->sc_mapped = TRUE; 556 557 /* scratch register test... */ 558 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 559 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 560 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 561 goto error; 562 } 563 564 PRINTREG(RADEON_CRTC_EXT_CNTL); 565 PRINTREG(RADEON_CRTC_GEN_CNTL); 566 PRINTREG(RADEON_CRTC2_GEN_CNTL); 567 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 568 PRINTREG(RADEON_DAC_CNTL2); 569 PRINTREG(RADEON_FP_GEN_CNTL); 570 PRINTREG(RADEON_FP2_GEN_CNTL); 571 572 PRINTREG(RADEON_BIOS_4_SCRATCH); 573 PRINTREG(RADEON_FP_GEN_CNTL); 574 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 575 PRINTREG(RADEON_FP2_GEN_CNTL); 576 PRINTREG(RADEON_TMDS_CNTL); 577 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 578 PRINTREG(RADEON_TMDS_PLL_CNTL); 579 PRINTREG(RADEON_LVDS_GEN_CNTL); 580 PRINTREG(RADEON_FP_HORZ_STRETCH); 581 PRINTREG(RADEON_FP_VERT_STRETCH); 582 583 if (IS_RV100(sc)) 584 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 585 586 /* XXX 587 * according to xf86-video-radeon R3xx has this bit backwards 588 */ 589 if (IS_R300(sc)) { 590 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 591 0, 592 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 593 } else { 594 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 595 RADEON_TMDS_TRANSMITTER_PLLEN, 596 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 597 } 598 599 radeonfb_i2c_init(sc); 600 601 radeonfb_loadbios(sc, pa); 602 603 #ifdef RADEONFB_BIOS_INIT 604 if (radeonfb_bios_init(sc)) { 605 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 606 } 607 #endif 608 609 if (radeonfb_getclocks(sc)) { 610 aprint_error("%s: Unable to get reference clocks from BIOS\n", 611 XNAME(sc)); 612 goto error; 613 } 614 615 if (radeonfb_gettmds(sc)) { 616 aprint_error("%s: Unable to identify TMDS PLL settings\n", 617 XNAME(sc)); 618 goto error; 619 } 620 621 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 622 "minpll = %d, maxpll = %d\n", XNAME(sc), 623 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 624 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 625 626 radeonfb_getconnectors(sc); 627 628 radeonfb_set_fbloc(sc); 629 630 for (i = 0; radeonfb_limits[i].size; i++) { 631 if (sc->sc_memsz >= radeonfb_limits[i].size) { 632 sc->sc_maxx = radeonfb_limits[i].maxx; 633 sc->sc_maxy = radeonfb_limits[i].maxy; 634 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 635 /* framebuffer offset, start at a 4K page */ 636 sc->sc_fboffset = sc->sc_memsz / 637 radeonfb_limits[i].maxdisp; 638 /* 639 * we use the fbsize to figure out where we can store 640 * things like cursor data. 641 */ 642 sc->sc_fbsize = 643 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 644 RADEON_STRIDEALIGN) * sc->sc_maxy, 645 4096); 646 break; 647 } 648 } 649 650 651 radeonfb_init_misc(sc); 652 653 /* program the DAC wirings */ 654 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 655 switch (sc->sc_ports[i].rp_dac_type) { 656 case RADEON_DAC_PRIMARY: 657 PATCH32(sc, RADEON_DAC_CNTL2, 658 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 659 ~RADEON_DAC2_DAC_CLK_SEL); 660 break; 661 case RADEON_DAC_TVDAC: 662 /* we always use the TVDAC to drive a secondary analog 663 * CRT for now. if we ever support TV-out this will 664 * have to change. 665 */ 666 SET32(sc, RADEON_DAC_CNTL2, 667 RADEON_DAC2_DAC2_CLK_SEL); 668 PATCH32(sc, RADEON_DISP_HW_DEBUG, 669 i ? 0 : RADEON_CRT2_DISP1_SEL, 670 ~RADEON_CRT2_DISP1_SEL); 671 /* we're using CRTC2 for the 2nd port */ 672 if (sc->sc_ports[i].rp_number == 1) { 673 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 674 RADEON_DISP_DAC2_SOURCE_CRTC2, 675 ~RADEON_DISP_DAC2_SOURCE_MASK); 676 } 677 678 break; 679 } 680 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 681 sc->sc_ports[i].rp_tmds_type)); 682 switch (sc->sc_ports[i].rp_tmds_type) { 683 case RADEON_TMDS_INT: 684 /* point FP0 at the CRTC this port uses */ 685 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 686 __func__, sc->sc_ports[i].rp_number)); 687 if (IS_R300(sc)) { 688 PATCH32(sc, RADEON_FP_GEN_CNTL, 689 sc->sc_ports[i].rp_number ? 690 R200_FP_SOURCE_SEL_CRTC2 : 691 R200_FP_SOURCE_SEL_CRTC1, 692 ~R200_FP_SOURCE_SEL_MASK); 693 } else { 694 PATCH32(sc, RADEON_FP_GEN_CNTL, 695 sc->sc_ports[i].rp_number ? 696 RADEON_FP_SEL_CRTC2 : 697 RADEON_FP_SEL_CRTC1, 698 ~RADEON_FP_SEL_MASK); 699 } 700 } 701 } 702 PRINTREG(RADEON_DAC_CNTL2); 703 PRINTREG(RADEON_DISP_HW_DEBUG); 704 705 /* other DAC programming */ 706 v = GET32(sc, RADEON_DAC_CNTL); 707 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 708 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 709 PUT32(sc, RADEON_DAC_CNTL, v); 710 PRINTREG(RADEON_DAC_CNTL); 711 712 /* XXX: this may need more investigation */ 713 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 714 PRINTREG(RADEON_TV_DAC_CNTL); 715 716 /* enable TMDS */ 717 SET32(sc, RADEON_FP_GEN_CNTL, 718 RADEON_FP_TMDS_EN | 719 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 720 RADEON_FP_CRTC_DONT_SHADOW_HEND); 721 /* 722 * XXX 723 * no idea why this is necessary - if I do not clear this bit on my 724 * iBook G4 the screen remains black, even though it's already clear. 725 * It needs to be set on my Sun XVR-100 for the DVI port to work 726 * TODO: 727 * see if this is still necessary now that CRTCs, DACs and outputs are 728 * getting wired up in a halfway sane way 729 */ 730 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 731 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 732 } else { 733 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 734 } 735 736 /* 737 * we use bus_space_map instead of pci_mapreg, because we don't 738 * need the full aperature space. no point in wasting virtual 739 * address space we don't intend to use, right? 740 */ 741 if ((sc->sc_memsz < (4096 * 1024)) || 742 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 743 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 744 (bsz < sc->sc_memsz)) { 745 sc->sc_memsz = 0; 746 aprint_error("%s: Bad frame buffer configuration\n", 747 XNAME(sc)); 748 goto error; 749 } 750 751 /* 64 MB should be enough -- more just wastes map entries */ 752 if (sc->sc_memsz > (64 << 20)) 753 sc->sc_memsz = (64 << 20); 754 755 sc->sc_memt = pa->pa_memt; 756 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 757 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 758 sc->sc_memsz = 0; 759 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 760 goto error; 761 } 762 763 aprint_normal("%s: %d MB aperture at 0x%08x, " 764 "%d KB registers at 0x%08x\n", XNAME(sc), 765 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 766 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 767 768 /* setup default video mode from devprop (allows PROM override) */ 769 sc->sc_defaultmode = radeonfb_default_mode; 770 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 771 "videomode", &mptr)) { 772 773 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 774 sc->sc_defaultmode = sc->sc_modebuf; 775 } 776 777 /* initialize some basic display parameters */ 778 for (i = 0; i < sc->sc_ndisplays; i++) { 779 struct radeonfb_display *dp = &sc->sc_displays[i]; 780 struct rasops_info *ri; 781 long defattr; 782 struct wsemuldisplaydev_attach_args aa; 783 784 /* 785 * Figure out how many "displays" (desktops) we are going to 786 * support. If more than one, then each CRTC gets its own 787 * programming. 788 * 789 * XXX: this code needs to change to support mergedfb. 790 * XXX: would be nice to allow this to be overridden 791 */ 792 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 793 DPRINTF(("dual crtcs!\n")); 794 dp->rd_ncrtcs = 2; 795 dp->rd_crtcs[0].rc_port = 796 &sc->sc_ports[0]; 797 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 798 dp->rd_crtcs[1].rc_port = 799 &sc->sc_ports[1]; 800 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 801 } else { 802 dp->rd_ncrtcs = 1; 803 dp->rd_crtcs[0].rc_port = 804 &sc->sc_ports[i]; 805 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 806 } 807 808 dp->rd_softc = sc; 809 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 810 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 811 812 /* for text mode, we pick a resolution that won't 813 * require panning */ 814 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 815 816 aprint_normal("%s: display %d: " 817 "initial virtual resolution %dx%d at %d bpp\n", 818 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 819 820 /* now select the *video mode* that we will use */ 821 for (j = 0; j < dp->rd_ncrtcs; j++) { 822 const struct videomode *vmp; 823 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 824 dp->rd_virtx, dp->rd_virty); 825 826 /* 827 * virtual resolution should be at least as high as 828 * physical 829 */ 830 if (dp->rd_virtx < vmp->hdisplay || 831 dp->rd_virty < vmp->vdisplay) { 832 dp->rd_virtx = vmp->hdisplay; 833 dp->rd_virty = vmp->vdisplay; 834 } 835 836 dp->rd_crtcs[j].rc_videomode = *vmp; 837 printf("%s: port %d: physical %dx%d %dHz\n", 838 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 839 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 840 vmp->htotal), vmp->vtotal)); 841 } 842 843 /* N.B.: radeon wants 64-byte aligned stride */ 844 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 845 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 846 DPRINTF(("stride: %d\n", dp->rd_stride)); 847 848 dp->rd_offset = sc->sc_fboffset * i; 849 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 850 sc->sc_memh) + dp->rd_offset; 851 dp->rd_curoff = sc->sc_fbsize; 852 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 853 854 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 855 856 switch (dp->rd_bpp) { 857 case 8: 858 dp->rd_format = 2; 859 break; 860 case 32: 861 dp->rd_format = 6; 862 break; 863 default: 864 aprint_error("%s: bad depth %d\n", XNAME(sc), 865 dp->rd_bpp); 866 goto error; 867 } 868 869 DPRINTF(("init engine\n")); 870 /* XXX: this seems suspicious - per display engine 871 initialization? */ 872 radeonfb_engine_init(dp); 873 874 /* copy the template into place */ 875 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 876 dp->rd_wsscreens = dp->rd_wsscreens_storage; 877 878 /* and make up the list */ 879 dp->rd_wsscreenlist.nscreens = 1; 880 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 881 882 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 883 &radeonfb_accessops); 884 885 dp->rd_vd.init_screen = radeonfb_init_screen; 886 887 #ifdef RADEONFB_DEBUG 888 dp->rd_virty -= 200; 889 #endif 890 891 dp->rd_console = 0; 892 prop_dictionary_get_bool(device_properties(sc->sc_dev), 893 "is_console", &dp->rd_console); 894 895 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 896 897 898 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 899 dp->rd_console, &defattr); 900 901 ri = &dp->rd_vscreen.scr_ri; 902 903 /* clear the screen */ 904 rasops_unpack_attr(defattr, &fg, &bg, &ul); 905 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 906 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 907 dp->rd_bg); 908 909 dp->rd_wsscreens->textops = &ri->ri_ops; 910 dp->rd_wsscreens->capabilities = ri->ri_caps; 911 dp->rd_wsscreens->nrows = ri->ri_rows; 912 dp->rd_wsscreens->ncols = ri->ri_cols; 913 914 #ifdef SPLASHSCREEN 915 dp->rd_splash.si_depth = ri->ri_depth; 916 dp->rd_splash.si_bits = ri->ri_bits; 917 dp->rd_splash.si_hwbits = ri->ri_hwbits; 918 dp->rd_splash.si_width = ri->ri_width; 919 dp->rd_splash.si_height = ri->ri_height; 920 dp->rd_splash.si_stride = ri->ri_stride; 921 dp->rd_splash.si_fillrect = NULL; 922 #endif 923 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 924 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 925 dp->rd_gc.gc_rop = RADEON_ROP3_S; 926 dp->rd_gc.gc_blitcookie = dp; 927 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 928 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 929 dp->rd_virtx, 930 ri->ri_font->fontwidth, 931 ri->ri_font->fontheight, 932 defattr); 933 if (dp->rd_console) { 934 935 radeonfb_modeswitch(dp); 936 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 937 defattr); 938 #ifdef SPLASHSCREEN 939 if (splash_render(&dp->rd_splash, 940 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 941 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 942 else 943 #endif 944 vcons_replay_msgbuf(&dp->rd_vscreen); 945 } else { 946 947 /* 948 * since we're not the console we can postpone 949 * the rest until someone actually allocates a 950 * screen for us. but we do clear the screen 951 * at least. 952 */ 953 memset(ri->ri_bits, 0, 1024); 954 955 radeonfb_modeswitch(dp); 956 #ifdef SPLASHSCREEN 957 if (splash_render(&dp->rd_splash, 958 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 959 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 960 #endif 961 } 962 963 aa.console = dp->rd_console; 964 aa.scrdata = &dp->rd_wsscreenlist; 965 aa.accessops = &radeonfb_accessops; 966 aa.accesscookie = &dp->rd_vd; 967 968 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 969 970 radeonfb_blank(dp, 0); 971 972 /* Initialise delayed lvds operations for backlight. */ 973 callout_init(&dp->rd_bl_lvds_co, 0); 974 callout_setfunc(&dp->rd_bl_lvds_co, 975 radeonfb_lvds_callout, dp); 976 dp->rd_bl_on = 1; 977 dp->rd_bl_level = radeonfb_get_backlight(dp); 978 radeonfb_set_backlight(dp, dp->rd_bl_level); 979 } 980 981 for (i = 0; i < RADEON_NDISPLAYS; i++) 982 radeonfb_init_palette(&sc->sc_displays[i]); 983 984 if (HAS_CRTC2(sc)) { 985 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 986 } 987 988 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 989 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 990 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 991 radeonfb_brightness_up, TRUE); 992 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 993 radeonfb_brightness_down, TRUE); 994 995 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 996 997 PRINTREG(RADEON_CRTC_EXT_CNTL); 998 PRINTREG(RADEON_CRTC_GEN_CNTL); 999 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1000 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1001 PRINTREG(RADEON_DAC_CNTL2); 1002 PRINTREG(RADEON_FP_GEN_CNTL); 1003 PRINTREG(RADEON_FP2_GEN_CNTL); 1004 1005 return; 1006 1007 error: 1008 if (sc->sc_biossz) 1009 free(sc->sc_bios, M_DEVBUF); 1010 1011 if (sc->sc_regsz) 1012 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1013 1014 if (sc->sc_memsz) 1015 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1016 } 1017 1018 static void 1019 radeonfb_map(struct radeonfb_softc *sc) 1020 { 1021 if (!sc->sc_mapped) { 1022 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1023 &sc->sc_regh) != 0) { 1024 aprint_error_dev(sc->sc_dev, 1025 "unable to map registers!\n"); 1026 return; 1027 } 1028 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1029 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1030 sc->sc_memsz = 0; 1031 aprint_error_dev(sc->sc_dev, 1032 "Unable to map frame buffer\n"); 1033 return; 1034 } 1035 sc->sc_mapped = TRUE; 1036 } 1037 } 1038 1039 static void 1040 radeonfb_unmap(struct radeonfb_softc *sc) 1041 { 1042 if (sc->sc_mapped) { 1043 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1044 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1045 sc->sc_mapped = FALSE; 1046 } 1047 } 1048 1049 static int 1050 radeonfb_drm_print(void *aux, const char *pnp) 1051 { 1052 if (pnp) 1053 aprint_normal("drm at %s", pnp); 1054 return (UNCONF); 1055 } 1056 1057 int 1058 radeonfb_ioctl(void *v, void *vs, 1059 unsigned long cmd, void *d, int flag, struct lwp *l) 1060 { 1061 struct vcons_data *vd; 1062 struct radeonfb_display *dp; 1063 struct radeonfb_softc *sc; 1064 struct wsdisplay_param *param; 1065 struct vcons_screen *ms; 1066 1067 vd = (struct vcons_data *)v; 1068 ms = vd->active; 1069 dp = (struct radeonfb_display *)vd->cookie; 1070 sc = dp->rd_softc; 1071 1072 switch (cmd) { 1073 case WSDISPLAYIO_GTYPE: 1074 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1075 return 0; 1076 1077 case WSDISPLAYIO_GINFO: 1078 if (vd->active != NULL) { 1079 struct wsdisplay_fbinfo *fb; 1080 fb = (struct wsdisplay_fbinfo *)d; 1081 fb->width = dp->rd_virtx; 1082 fb->height = dp->rd_virty; 1083 fb->depth = dp->rd_bpp; 1084 fb->cmsize = 256; 1085 return 0; 1086 } else 1087 return ENODEV; 1088 case WSDISPLAYIO_GVIDEO: 1089 if (radeonfb_isblank(dp)) 1090 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1091 else 1092 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1093 return 0; 1094 1095 case WSDISPLAYIO_SVIDEO: 1096 radeonfb_blank(dp, 1097 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1098 return 0; 1099 1100 case WSDISPLAYIO_GETCMAP: 1101 #if 0 1102 if (dp->rd_bpp == 8) 1103 return radeonfb_getcmap(sc, 1104 (struct wsdisplay_cmap *)d); 1105 #endif 1106 return EINVAL; 1107 1108 case WSDISPLAYIO_PUTCMAP: 1109 #if 0 1110 if (dp->rd_bpp == 8) 1111 return radeonfb_putcmap(sc, 1112 (struct wsdisplay_cmap *)d); 1113 #endif 1114 return EINVAL; 1115 1116 case WSDISPLAYIO_LINEBYTES: 1117 *(unsigned *)d = dp->rd_stride; 1118 return 0; 1119 1120 case WSDISPLAYIO_SMODE: 1121 if (*(int *)d != dp->rd_wsmode) { 1122 dp->rd_wsmode = *(int *)d; 1123 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1124 (dp->rd_vd.active)) { 1125 radeonfb_map(sc); 1126 radeonfb_engine_init(dp); 1127 glyphcache_wipe(&dp->rd_gc); 1128 radeonfb_init_palette(dp); 1129 radeonfb_modeswitch(dp); 1130 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1131 dp->rd_virty, dp->rd_bg); 1132 vcons_redraw_screen(dp->rd_vd.active); 1133 } else { 1134 radeonfb_unmap(sc); 1135 } 1136 } 1137 return 0; 1138 1139 case WSDISPLAYIO_GCURMAX: 1140 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1141 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1142 return 0; 1143 1144 case WSDISPLAYIO_SCURSOR: 1145 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1146 1147 case WSDISPLAYIO_GCURSOR: 1148 return EPASSTHROUGH; 1149 1150 case WSDISPLAYIO_GCURPOS: 1151 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1152 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1153 return 0; 1154 1155 case WSDISPLAYIO_SCURPOS: 1156 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1157 1158 case WSDISPLAYIO_SSPLASH: 1159 #if defined(SPLASHSCREEN) 1160 if (*(int *)d == 1) { 1161 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1162 splash_render(&dp->rd_splash, 1163 SPLASH_F_CENTER|SPLASH_F_FILL); 1164 } else 1165 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1166 return 0; 1167 #else 1168 return ENODEV; 1169 #endif 1170 case WSDISPLAYIO_GETPARAM: 1171 param = (struct wsdisplay_param *)d; 1172 switch (param->param) { 1173 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1174 param->min = 0; 1175 param->max = 255; 1176 param->curval = dp->rd_bl_level; 1177 return 0; 1178 case WSDISPLAYIO_PARAM_BACKLIGHT: 1179 param->min = 0; 1180 param->max = RADEONFB_BACKLIGHT_MAX; 1181 param->curval = dp->rd_bl_on; 1182 return 0; 1183 } 1184 return EPASSTHROUGH; 1185 1186 case WSDISPLAYIO_SETPARAM: 1187 param = (struct wsdisplay_param *)d; 1188 switch (param->param) { 1189 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1190 radeonfb_set_backlight(dp, param->curval); 1191 return 0; 1192 case WSDISPLAYIO_PARAM_BACKLIGHT: 1193 radeonfb_switch_backlight(dp, param->curval); 1194 return 0; 1195 } 1196 return EPASSTHROUGH; 1197 1198 /* PCI config read/write passthrough. */ 1199 case PCI_IOC_CFGREAD: 1200 case PCI_IOC_CFGWRITE: 1201 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1202 1203 case WSDISPLAYIO_GET_BUSID: 1204 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1205 sc->sc_pt, d); 1206 1207 case WSDISPLAYIO_GET_EDID: { 1208 struct wsdisplayio_edid_info *ei = d; 1209 return wsdisplayio_get_edid(sc->sc_dev, ei); 1210 } 1211 1212 case WSDISPLAYIO_GET_FBINFO: { 1213 struct wsdisplayio_fbinfo *fbi = d; 1214 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1215 } 1216 1217 default: 1218 return EPASSTHROUGH; 1219 } 1220 } 1221 1222 paddr_t 1223 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1224 { 1225 struct vcons_data *vd; 1226 struct radeonfb_display *dp; 1227 struct radeonfb_softc *sc; 1228 paddr_t pa; 1229 1230 vd = (struct vcons_data *)v; 1231 dp = (struct radeonfb_display *)vd->cookie; 1232 sc = dp->rd_softc; 1233 1234 /* XXX: note that we don't allow mapping of registers right now */ 1235 /* XXX: this means that the XFree86 radeon driver won't work */ 1236 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1237 pa = bus_space_mmap(sc->sc_memt, 1238 sc->sc_memaddr + dp->rd_offset + offset, 0, 1239 prot, BUS_SPACE_MAP_LINEAR); 1240 return pa; 1241 } 1242 1243 #ifdef RADEONFB_MMAP_BARS 1244 /* 1245 * restrict all other mappings to processes with superuser privileges 1246 * or the kernel itself 1247 */ 1248 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1249 NULL, NULL, NULL, NULL) != 0) { 1250 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1251 return -1; 1252 } 1253 1254 if ((offset >= sc->sc_regaddr) && 1255 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1256 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1257 BUS_SPACE_MAP_LINEAR); 1258 } 1259 1260 if ((offset >= sc->sc_memaddr) && 1261 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1262 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1263 BUS_SPACE_MAP_LINEAR); 1264 } 1265 1266 if ((offset >= sc->sc_romaddr) && 1267 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1268 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1269 BUS_SPACE_MAP_LINEAR); 1270 } 1271 1272 #ifdef PCI_MAGIC_IO_RANGE 1273 /* allow mapping of IO space */ 1274 if ((offset >= PCI_MAGIC_IO_RANGE) && 1275 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1276 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1277 0, prot, 0); 1278 return pa; 1279 } 1280 #endif /* PCI_MAGIC_IO_RANGE */ 1281 1282 #endif /* RADEONFB_MMAP_BARS */ 1283 1284 return -1; 1285 } 1286 1287 static void 1288 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1289 { 1290 bus_space_tag_t romt; 1291 bus_space_handle_t romh, biosh; 1292 bus_size_t romsz; 1293 bus_addr_t ptr; 1294 1295 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1296 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1297 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1298 return; 1299 } 1300 1301 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1302 &sc->sc_biossz); 1303 if (sc->sc_biossz == 0) { 1304 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1305 return; 1306 } 1307 1308 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1309 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1310 1311 /* unmap the PCI expansion rom */ 1312 bus_space_unmap(romt, romh, romsz); 1313 1314 /* turn off rom decoder now */ 1315 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1316 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1317 ~PCI_MAPREG_ROM_ENABLE); 1318 1319 ptr = GETBIOS16(sc, 0x48); 1320 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1321 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1322 sc->sc_flags |= RFB_ATOM; 1323 } 1324 1325 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1326 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1327 } 1328 1329 1330 uint32_t 1331 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1332 { 1333 1334 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1335 } 1336 1337 void 1338 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1339 { 1340 1341 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1342 } 1343 1344 void 1345 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1346 { 1347 1348 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1349 } 1350 1351 void 1352 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1353 uint32_t andmask, uint32_t ormask) 1354 { 1355 int s; 1356 uint32_t val; 1357 1358 s = splhigh(); 1359 val = radeonfb_get32(sc, reg); 1360 val = (val & andmask) | ormask; 1361 radeonfb_put32(sc, reg, val); 1362 splx(s); 1363 } 1364 1365 uint32_t 1366 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1367 { 1368 int s; 1369 uint32_t val; 1370 1371 s = splhigh(); 1372 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1373 val = radeonfb_get32(sc, RADEON_MM_DATA); 1374 splx(s); 1375 1376 return (val); 1377 } 1378 1379 void 1380 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1381 { 1382 int s; 1383 1384 s = splhigh(); 1385 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1386 radeonfb_put32(sc, RADEON_MM_DATA, val); 1387 splx(s); 1388 } 1389 1390 void 1391 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1392 uint32_t andmask, uint32_t ormask) 1393 { 1394 int s; 1395 uint32_t val; 1396 1397 s = splhigh(); 1398 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1399 val = radeonfb_get32(sc, RADEON_MM_DATA); 1400 val = (val & andmask) | ormask; 1401 radeonfb_put32(sc, RADEON_MM_DATA, val); 1402 splx(s); 1403 } 1404 1405 uint32_t 1406 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1407 { 1408 int s; 1409 uint32_t val; 1410 1411 s = splhigh(); 1412 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1413 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1414 if (HAS_R300CG(sc)) 1415 radeonfb_r300cg_workaround(sc); 1416 splx(s); 1417 1418 return (val); 1419 } 1420 1421 void 1422 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1423 { 1424 int s; 1425 1426 s = splhigh(); 1427 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1428 RADEON_PLL_WR_EN); 1429 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1430 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1431 splx(s); 1432 } 1433 1434 void 1435 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1436 uint32_t andmask, uint32_t ormask) 1437 { 1438 int s; 1439 uint32_t val; 1440 1441 s = splhigh(); 1442 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1443 RADEON_PLL_WR_EN); 1444 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1445 val = (val & andmask) | ormask; 1446 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1447 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1448 splx(s); 1449 } 1450 1451 int 1452 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1453 { 1454 uint32_t saved; 1455 1456 saved = GET32(sc, reg); 1457 PUT32(sc, reg, v); 1458 if (GET32(sc, reg) != v) { 1459 return -1; 1460 } 1461 PUT32(sc, reg, saved); 1462 return 0; 1463 } 1464 1465 uintmax_t 1466 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1467 uintmax_t defval) 1468 { 1469 prop_number_t pn; 1470 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1471 if (pn == NULL) { 1472 return defval; 1473 } 1474 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1475 return (prop_number_integer_value(pn)); 1476 } 1477 1478 int 1479 radeonfb_getclocks(struct radeonfb_softc *sc) 1480 { 1481 bus_addr_t ptr; 1482 int refclk = 0; 1483 int refdiv = 0; 1484 int minpll = 0; 1485 int maxpll = 0; 1486 1487 /* load initial property values if port/board provides them */ 1488 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1489 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1490 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1491 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1492 1493 PRINTPLL(RADEON_PPLL_REF_DIV); 1494 PRINTPLL(RADEON_PPLL_DIV_0); 1495 PRINTPLL(RADEON_PPLL_DIV_1); 1496 PRINTPLL(RADEON_PPLL_DIV_2); 1497 PRINTPLL(RADEON_PPLL_DIV_3); 1498 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1499 PRINTPLL(RADEON_P2PLL_REF_DIV); 1500 PRINTPLL(RADEON_P2PLL_DIV_0); 1501 1502 if (refclk && refdiv && minpll && maxpll) 1503 goto dontprobe; 1504 1505 if (!sc->sc_biossz) { 1506 /* no BIOS */ 1507 aprint_verbose("%s: No video BIOS, using default clocks\n", 1508 XNAME(sc)); 1509 if (IS_IGP(sc)) 1510 refclk = refclk ? refclk : 1432; 1511 else 1512 refclk = refclk ? refclk : 2700; 1513 refdiv = refdiv ? refdiv : 12; 1514 minpll = minpll ? minpll : 12500; 1515 /* XXX 1516 * Need to check if the firmware or something programmed a 1517 * higher value than this, and if so, bump it. 1518 * The RV280 in my iBook is unhappy if the PLL input is less 1519 * than 360MHz 1520 */ 1521 maxpll = maxpll ? maxpll : 40000/*35000*/; 1522 } else if (IS_ATOM(sc)) { 1523 /* ATOM BIOS */ 1524 ptr = GETBIOS16(sc, 0x48); 1525 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1526 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1527 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1528 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1529 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1530 /* 1531 * ATOM BIOS doesn't supply a reference divider, so we 1532 * have to probe for it. 1533 */ 1534 if (refdiv < 2) 1535 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1536 RADEON_PPLL_REF_DIV_MASK; 1537 /* 1538 * if probe is zero, just assume one that should work 1539 * for most parts 1540 */ 1541 if (refdiv < 2) 1542 refdiv = 12; 1543 1544 } else { 1545 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1546 /* Legacy BIOS */ 1547 ptr = GETBIOS16(sc, 0x48); 1548 ptr = GETBIOS16(sc, ptr + 0x30); 1549 if (IS_R300(sc)) { 1550 refdiv = refdiv ? refdiv : 1551 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1552 R300_PPLL_REF_DIV_ACC_SHIFT; 1553 } else { 1554 refdiv = refdiv ? refdiv : 1555 tmp & RADEON_PPLL_REF_DIV_MASK; 1556 } 1557 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1558 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1559 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1560 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1561 } 1562 1563 1564 dontprobe: 1565 sc->sc_refclk = refclk * 10; 1566 sc->sc_refdiv = refdiv; 1567 sc->sc_minpll = minpll * 10; 1568 sc->sc_maxpll = maxpll * 10; 1569 return 0; 1570 } 1571 1572 int 1573 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1574 uint32_t *postdivbit, uint32_t *feedbackdiv) 1575 { 1576 int i; 1577 uint32_t outfreq; 1578 int div; 1579 1580 DPRINTF(("dot clock: %u\n", dotclock)); 1581 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1582 outfreq = div * dotclock; 1583 if ((outfreq >= sc->sc_minpll) && 1584 (outfreq <= sc->sc_maxpll)) { 1585 DPRINTF(("outfreq: %u\n", outfreq)); 1586 *postdivbit = 1587 ((uint32_t)radeonfb_dividers[i].mask << 16); 1588 DPRINTF(("post divider: %d (mask %x)\n", div, 1589 *postdivbit)); 1590 break; 1591 } 1592 } 1593 1594 if (div == 0) 1595 return 1; 1596 1597 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1598 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1599 return 0; 1600 } 1601 1602 #if 0 1603 #ifdef RADEONFB_DEBUG 1604 static void 1605 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1606 { 1607 char asc[17]; 1608 unsigned ptr = (unsigned)buffer; 1609 char *start = (char *)(ptr & ~0xf); 1610 char *end = (char *)(ptr + size); 1611 1612 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1613 1614 if (pfx == NULL) { 1615 pfx = ""; 1616 } 1617 1618 while (start < end) { 1619 unsigned offset = (unsigned)start & 0xf; 1620 if (offset == 0) { 1621 printf("%s%x: ", pfx, (unsigned)start); 1622 } 1623 if (((unsigned)start < ptr) || 1624 ((unsigned)start >= (ptr + size))) { 1625 printf(" "); 1626 asc[offset] = ' '; 1627 } else { 1628 printf("%02x", *(unsigned char *)start); 1629 if ((*start >= ' ') && (*start <= '~')) { 1630 asc[offset] = *start; 1631 } else { 1632 asc[offset] = '.'; 1633 } 1634 } 1635 asc[offset + 1] = 0; 1636 if (offset % 2) { 1637 printf(" "); 1638 } 1639 if (offset == 15) { 1640 printf(" %s\n", asc); 1641 } 1642 start++; 1643 } 1644 } 1645 #endif 1646 #endif 1647 1648 int 1649 radeonfb_getconnectors(struct radeonfb_softc *sc) 1650 { 1651 int i; 1652 int found = 0; 1653 1654 for (i = 0; i < 2; i++) { 1655 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1656 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1657 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1658 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1659 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1660 } 1661 1662 /* 1663 * This logic is borrowed from Xorg's radeon driver. 1664 */ 1665 if (!sc->sc_biossz) 1666 goto nobios; 1667 1668 if (IS_ATOM(sc)) { 1669 /* not done yet */ 1670 } else { 1671 uint16_t ptr; 1672 int port = 0; 1673 1674 ptr = GETBIOS16(sc, 0x48); 1675 ptr = GETBIOS16(sc, ptr + 0x50); 1676 for (i = 1; i < 4; i++) { 1677 uint16_t entry; 1678 uint8_t conn, ddc, dac, tmds; 1679 1680 /* 1681 * Parse the connector table. From reading the code, 1682 * it appears to made up of 16-bit entries for each 1683 * connector. The 16-bits are defined as: 1684 * 1685 * bits 12-15 - connector type (0 == end of table) 1686 * bits 8-11 - DDC type 1687 * bits 5-7 - ??? 1688 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1689 * bits 1-3 - ??? 1690 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1691 */ 1692 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1693 break; 1694 entry = GETBIOS16(sc, ptr + i * 2); 1695 1696 conn = (entry >> 12) & 0xf; 1697 ddc = (entry >> 8) & 0xf; 1698 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1699 RADEON_DAC_PRIMARY; 1700 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1701 RADEON_TMDS_INT; 1702 1703 if (conn == RADEON_CONN_NONE) 1704 continue; /* no connector */ 1705 1706 if ((found > 0) && 1707 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1708 /* duplicate entry for same connector */ 1709 continue; 1710 } 1711 1712 /* internal DDC_DVI port gets priority */ 1713 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1714 port = 0; 1715 else 1716 port = 1; 1717 1718 sc->sc_ports[port].rp_ddc_type = 1719 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1720 sc->sc_ports[port].rp_dac_type = dac; 1721 sc->sc_ports[port].rp_conn_type = 1722 min(conn, RADEON_CONN_UNSUPPORTED) ; 1723 1724 sc->sc_ports[port].rp_tmds_type = tmds; 1725 1726 if ((conn != RADEON_CONN_DVI_I) && 1727 (conn != RADEON_CONN_DVI_D) && 1728 (tmds == RADEON_TMDS_INT)) 1729 sc->sc_ports[port].rp_tmds_type = 1730 RADEON_TMDS_UNKNOWN; 1731 sc->sc_ports[port].rp_number = i - 1; 1732 1733 found += (port + 1); 1734 } 1735 } 1736 1737 nobios: 1738 if (!found) { 1739 DPRINTF(("No connector info in BIOS!\n")); 1740 if IS_MOBILITY(sc) { 1741 /* default, port 0 = internal TMDS, port 1 = CRT */ 1742 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1743 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1744 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1745 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1746 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1747 sc->sc_ports[0].rp_number = 0; 1748 1749 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1750 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1751 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1752 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1753 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1754 sc->sc_ports[1].rp_number = 1; 1755 } else { 1756 /* default, port 0 = DVI, port 1 = CRT */ 1757 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1758 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1759 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1760 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1761 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1762 sc->sc_ports[0].rp_number = 1; 1763 1764 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1765 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1766 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1767 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1768 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1769 sc->sc_ports[1].rp_number = 0; 1770 } 1771 } 1772 1773 /* 1774 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1775 * these chips should use TVDAC for the VGA port. 1776 */ 1777 if (HAS_SDAC(sc)) { 1778 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1779 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1780 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1781 } else { 1782 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1783 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1784 } 1785 } else if (!HAS_CRTC2(sc)) { 1786 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1787 } 1788 1789 for (i = 0; i < 2; i++) { 1790 char edid[128]; 1791 uint8_t ddc; 1792 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1793 prop_data_t edid_data; 1794 1795 DPRINTF(("Port #%d:\n", i)); 1796 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1797 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1798 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1799 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1800 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1801 1802 sc->sc_ports[i].rp_edid_valid = 0; 1803 /* first look for static EDID data */ 1804 if ((edid_data = prop_dictionary_get(device_properties( 1805 sc->sc_dev), "EDID")) != NULL) { 1806 1807 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1808 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1809 if (edid_parse(edid, eip) == 0) { 1810 1811 sc->sc_ports[i].rp_edid_valid = 1; 1812 } 1813 } 1814 /* if we didn't find any we'll try to talk to the monitor */ 1815 if (sc->sc_ports[i].rp_edid_valid != 1) { 1816 1817 ddc = sc->sc_ports[i].rp_ddc_type; 1818 if (ddc != RADEON_DDC_NONE) { 1819 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1820 == 0) && (edid_parse(edid, eip) == 0)) { 1821 1822 sc->sc_ports[i].rp_edid_valid = 1; 1823 #ifdef RADEONFB_DEBUG 1824 edid_print(eip); 1825 #endif 1826 } 1827 } 1828 } 1829 } 1830 1831 return found; 1832 } 1833 1834 int 1835 radeonfb_gettmds(struct radeonfb_softc *sc) 1836 { 1837 int i; 1838 1839 if (!sc->sc_biossz) { 1840 goto nobios; 1841 } 1842 1843 if (IS_ATOM(sc)) { 1844 /* XXX: not done yet */ 1845 } else { 1846 uint16_t ptr; 1847 int n; 1848 1849 ptr = GETBIOS16(sc, 0x48); 1850 ptr = GETBIOS16(sc, ptr + 0x34); 1851 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1852 if (GETBIOS8(sc, ptr) == 3) { 1853 /* revision three table */ 1854 n = GETBIOS8(sc, ptr + 5) + 1; 1855 n = min(n, 4); 1856 1857 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1858 for (i = 0; i < n; i++) { 1859 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1860 ptr + i * 10 + 8); 1861 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1862 ptr + i * 10 + 0x10); 1863 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1864 sc->sc_tmds_pll[i].rtp_freq, 1865 sc->sc_tmds_pll[i].rtp_pll)); 1866 } 1867 return 0; 1868 } 1869 } 1870 1871 nobios: 1872 DPRINTF(("no suitable DFP table present\n")); 1873 for (i = 0; 1874 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1875 i++) { 1876 int j; 1877 1878 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1879 continue; 1880 1881 for (j = 0; j < 4; j++) { 1882 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1883 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1884 sc->sc_tmds_pll[j].rtp_freq, 1885 sc->sc_tmds_pll[j].rtp_pll)); 1886 } 1887 return 0; 1888 } 1889 1890 return -1; 1891 } 1892 1893 const struct videomode * 1894 radeonfb_modelookup(const char *name) 1895 { 1896 int i; 1897 1898 for (i = 0; i < videomode_count; i++) 1899 if (!strcmp(name, videomode_list[i].name)) 1900 return &videomode_list[i]; 1901 1902 return NULL; 1903 } 1904 1905 void 1906 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1907 { 1908 if (crtc) { 1909 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1910 RADEON_P2PLL_ATOMIC_UPDATE_R); 1911 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1912 } else { 1913 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1914 RADEON_PPLL_ATOMIC_UPDATE_R); 1915 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1916 } 1917 } 1918 1919 void 1920 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1921 { 1922 int i; 1923 1924 for (i = 10000; i; i--) { 1925 if (crtc) { 1926 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1927 RADEON_P2PLL_ATOMIC_UPDATE_R) 1928 break; 1929 } else { 1930 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1931 RADEON_PPLL_ATOMIC_UPDATE_R) 1932 break; 1933 } 1934 } 1935 } 1936 1937 void 1938 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1939 { 1940 uint32_t pbit = 0; 1941 uint32_t feed = 0; 1942 uint32_t data, refdiv, div0; 1943 1944 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1945 1946 if (crtc == 0) { 1947 1948 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1949 if (IS_R300(sc)) { 1950 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1951 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1952 } else { 1953 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1954 sc->sc_refdiv; 1955 } 1956 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1957 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1958 RADEON_PPLL_POST3_DIV_MASK); 1959 div0 |= pbit; 1960 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1961 1962 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1963 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1964 /* 1965 * nothing to do here, the PLL is already where we 1966 * want it 1967 */ 1968 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1969 ~RADEON_PLL_DIV_SEL); 1970 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1971 return; 1972 } 1973 1974 /* alright, we do need to reprogram stuff */ 1975 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1976 RADEON_VCLK_SRC_SEL_CPUCLK, 1977 ~RADEON_VCLK_SRC_SEL_MASK); 1978 1979 /* put vclk into reset, use atomic updates */ 1980 SETPLL(sc, RADEON_PPLL_CNTL, 1981 RADEON_PPLL_REFCLK_SEL | 1982 RADEON_PPLL_FBCLK_SEL | 1983 RADEON_PPLL_RESET | 1984 RADEON_PPLL_ATOMIC_UPDATE_EN | 1985 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1986 1987 /* select clock 0 */ 1988 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1989 ~RADEON_PLL_DIV_SEL); 1990 1991 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1992 1993 /* xf86-video-radeon does this, not sure why */ 1994 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1995 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1996 1997 /* use the atomic update */ 1998 radeonfb_pllwriteupdate(sc, crtc); 1999 2000 /* and wait for it to complete */ 2001 radeonfb_pllwaitatomicread(sc, crtc); 2002 2003 /* program HTOTAL (why?) */ 2004 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2005 2006 /* drop reset */ 2007 CLRPLL(sc, RADEON_PPLL_CNTL, 2008 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2009 RADEON_PPLL_ATOMIC_UPDATE_EN | 2010 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2011 2012 PRINTPLL(RADEON_PPLL_CNTL); 2013 PRINTPLL(RADEON_PPLL_REF_DIV); 2014 PRINTPLL(RADEON_PPLL_DIV_3); 2015 2016 /* give clock time to lock */ 2017 delay(50000); 2018 2019 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2020 RADEON_VCLK_SRC_SEL_PPLLCLK, 2021 ~RADEON_VCLK_SRC_SEL_MASK); 2022 2023 } else { 2024 2025 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2026 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2027 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2028 2029 /* put vclk into reset, use atomic updates */ 2030 SETPLL(sc, RADEON_P2PLL_CNTL, 2031 RADEON_P2PLL_RESET | 2032 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2033 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2034 2035 /* program reference divider */ 2036 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2037 ~RADEON_P2PLL_REF_DIV_MASK); 2038 2039 /* program feedback and post dividers */ 2040 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2041 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2042 RADEON_P2PLL_POST0_DIV_MASK); 2043 data |= pbit; 2044 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2045 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2046 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2047 2048 PRINTPLL(RADEON_P2PLL_REF_DIV); 2049 PRINTPLL(RADEON_P2PLL_DIV_0); 2050 2051 /* use the atomic update */ 2052 radeonfb_pllwriteupdate(sc, crtc); 2053 2054 /* and wait for it to complete */ 2055 radeonfb_pllwaitatomicread(sc, crtc); 2056 2057 /* program HTOTAL (why?) */ 2058 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2059 2060 /* drop reset */ 2061 CLRPLL(sc, RADEON_P2PLL_CNTL, 2062 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2063 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2064 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2065 2066 /* allow time for clock to lock */ 2067 delay(50000); 2068 2069 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2070 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2071 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2072 } 2073 PRINTREG(RADEON_CRTC_MORE_CNTL); 2074 } 2075 2076 void 2077 radeonfb_modeswitch(struct radeonfb_display *dp) 2078 { 2079 struct radeonfb_softc *sc = dp->rd_softc; 2080 int i; 2081 2082 /* blank the display while we switch modes */ 2083 radeonfb_blank(dp, 1); 2084 2085 #if 0 2086 SET32(sc, RADEON_CRTC_EXT_CNTL, 2087 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2088 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2089 #endif 2090 2091 /* these registers might get in the way... */ 2092 PUT32(sc, RADEON_OVR_CLR, 0); 2093 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2094 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2095 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2096 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2097 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2098 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2099 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2100 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2101 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2102 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2103 2104 for (i = 0; i < dp->rd_ncrtcs; i++) 2105 radeonfb_setcrtc(dp, i); 2106 2107 /* activate the display */ 2108 radeonfb_blank(dp, 0); 2109 } 2110 2111 void 2112 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2113 { 2114 int crtc; 2115 struct videomode *mode; 2116 struct radeonfb_softc *sc; 2117 struct radeonfb_crtc *cp; 2118 uint32_t v; 2119 uint32_t gencntl; 2120 uint32_t htotaldisp; 2121 uint32_t hsyncstrt; 2122 uint32_t vtotaldisp; 2123 uint32_t vsyncstrt; 2124 uint32_t fphsyncstrt; 2125 uint32_t fpvsyncstrt; 2126 uint32_t fphtotaldisp; 2127 uint32_t fpvtotaldisp; 2128 uint32_t pitch; 2129 2130 sc = dp->rd_softc; 2131 cp = &dp->rd_crtcs[index]; 2132 crtc = cp->rc_number; 2133 mode = &cp->rc_videomode; 2134 2135 #if 1 2136 pitch = dp->rd_stride / dp->rd_bpp; 2137 #else 2138 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2139 (sc->sc_maxbpp * 8)); 2140 #endif 2141 switch (crtc) { 2142 case 0: 2143 gencntl = RADEON_CRTC_GEN_CNTL; 2144 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2145 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2146 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2147 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2148 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2149 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2150 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2151 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2152 break; 2153 case 1: 2154 gencntl = RADEON_CRTC2_GEN_CNTL; 2155 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2156 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2157 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2158 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2159 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2160 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2161 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2162 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2163 break; 2164 default: 2165 panic("Bad CRTC!"); 2166 break; 2167 } 2168 2169 /* 2170 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2171 */ 2172 /* only bother with 32bpp and 8bpp */ 2173 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2174 2175 if (crtc == 1) { 2176 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2177 } else { 2178 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2179 } 2180 2181 if (mode->flags & VID_DBLSCAN) 2182 v |= RADEON_CRTC2_DBL_SCAN_EN; 2183 2184 if (mode->flags & VID_INTERLACE) 2185 v |= RADEON_CRTC2_INTERLACE_EN; 2186 2187 if (mode->flags & VID_CSYNC) { 2188 v |= RADEON_CRTC2_CSYNC_EN; 2189 if (crtc == 1) 2190 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2191 } 2192 2193 PUT32(sc, gencntl, v); 2194 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2195 2196 /* 2197 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2198 */ 2199 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2200 if (crtc == 0) { 2201 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2202 RADEON_CRTC_DISPLAY_DIS); 2203 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2204 if (mode->flags & VID_CSYNC) 2205 v |= RADEON_CRTC_VSYNC_TRISTAT; 2206 } 2207 /* unconditional turn on CRT, in case first CRTC is DFP */ 2208 v |= RADEON_CRTC_CRT_ON; 2209 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2210 PRINTREG(RADEON_CRTC_EXT_CNTL); 2211 2212 /* 2213 * H_TOTAL_DISP 2214 */ 2215 v = ((mode->hdisplay / 8) - 1) << 16; 2216 v |= (mode->htotal / 8) - 1; 2217 PUT32(sc, htotaldisp, v); 2218 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2219 PUT32(sc, fphtotaldisp, v); 2220 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2221 2222 /* 2223 * H_SYNC_STRT_WID 2224 */ 2225 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2226 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2227 if (mode->flags & VID_NHSYNC) 2228 v |= RADEON_CRTC_H_SYNC_POL; 2229 PUT32(sc, hsyncstrt, v); 2230 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2231 PUT32(sc, fphsyncstrt, v); 2232 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2233 2234 /* 2235 * V_TOTAL_DISP 2236 */ 2237 v = ((mode->vdisplay - 1) << 16); 2238 v |= (mode->vtotal - 1); 2239 PUT32(sc, vtotaldisp, v); 2240 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2241 PUT32(sc, fpvtotaldisp, v); 2242 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2243 2244 /* 2245 * V_SYNC_STRT_WID 2246 */ 2247 v = ((mode->vsync_end - mode->vsync_start) << 16); 2248 v |= (mode->vsync_start - 1); 2249 if (mode->flags & VID_NVSYNC) 2250 v |= RADEON_CRTC_V_SYNC_POL; 2251 PUT32(sc, vsyncstrt, v); 2252 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2253 PUT32(sc, fpvsyncstrt, v); 2254 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2255 2256 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2257 2258 switch (crtc) { 2259 case 0: 2260 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2261 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2262 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2263 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2264 2265 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2266 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2267 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2268 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2269 PRINTREG(RADEON_CRTC_EXT_CNTL); 2270 PRINTREG(RADEON_CRTC_GEN_CNTL); 2271 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2272 break; 2273 2274 case 1: 2275 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2276 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2277 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2278 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2279 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2280 RADEON_CRTC2_VSYNC_DIS | 2281 RADEON_CRTC2_HSYNC_DIS | 2282 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2283 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2284 break; 2285 } 2286 } 2287 2288 int 2289 radeonfb_isblank(struct radeonfb_display *dp) 2290 { 2291 uint32_t reg, mask; 2292 2293 if(!dp->rd_softc->sc_mapped) 2294 return 1; 2295 2296 if (dp->rd_crtcs[0].rc_number) { 2297 reg = RADEON_CRTC2_GEN_CNTL; 2298 mask = RADEON_CRTC2_DISP_DIS; 2299 } else { 2300 reg = RADEON_CRTC_EXT_CNTL; 2301 mask = RADEON_CRTC_DISPLAY_DIS; 2302 } 2303 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2304 } 2305 2306 void 2307 radeonfb_blank(struct radeonfb_display *dp, int blank) 2308 { 2309 struct radeonfb_softc *sc = dp->rd_softc; 2310 uint32_t reg, mask; 2311 uint32_t fpreg, fpval; 2312 int i; 2313 2314 if (!sc->sc_mapped) 2315 return; 2316 2317 for (i = 0; i < dp->rd_ncrtcs; i++) { 2318 2319 if (dp->rd_crtcs[i].rc_number) { 2320 reg = RADEON_CRTC2_GEN_CNTL; 2321 mask = RADEON_CRTC2_DISP_DIS; 2322 fpreg = RADEON_FP2_GEN_CNTL; 2323 fpval = RADEON_FP2_ON; 2324 } else { 2325 reg = RADEON_CRTC_EXT_CNTL; 2326 mask = RADEON_CRTC_DISPLAY_DIS; 2327 fpreg = RADEON_FP_GEN_CNTL; 2328 fpval = RADEON_FP_FPON; 2329 } 2330 2331 if (blank) { 2332 SET32(sc, reg, mask); 2333 CLR32(sc, fpreg, fpval); 2334 } else { 2335 CLR32(sc, reg, mask); 2336 SET32(sc, fpreg, fpval); 2337 } 2338 } 2339 PRINTREG(RADEON_FP_GEN_CNTL); 2340 PRINTREG(RADEON_FP2_GEN_CNTL); 2341 } 2342 2343 void 2344 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2345 long *defattr) 2346 { 2347 struct radeonfb_display *dp = cookie; 2348 struct rasops_info *ri = &scr->scr_ri; 2349 2350 /* initialize font subsystem */ 2351 wsfont_init(); 2352 2353 DPRINTF(("init screen called, existing %d\n", existing)); 2354 2355 ri->ri_depth = dp->rd_bpp; 2356 ri->ri_width = dp->rd_virtx; 2357 ri->ri_height = dp->rd_virty; 2358 ri->ri_stride = dp->rd_stride; 2359 ri->ri_flg = RI_CENTER; 2360 switch (ri->ri_depth) { 2361 case 8: 2362 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2363 break; 2364 case 32: 2365 ri->ri_flg |= RI_ENABLE_ALPHA; 2366 /* we run radeons in RGB even on SPARC hardware */ 2367 ri->ri_rnum = 8; 2368 ri->ri_gnum = 8; 2369 ri->ri_bnum = 8; 2370 ri->ri_rpos = 16; 2371 ri->ri_gpos = 8; 2372 ri->ri_bpos = 0; 2373 break; 2374 } 2375 2376 ri->ri_bits = (void *)dp->rd_fbptr; 2377 2378 #ifdef VCONS_DRAW_INTR 2379 scr->scr_flags |= VCONS_DONT_READ; 2380 #endif 2381 2382 if (existing) { 2383 ri->ri_flg |= RI_CLEAR; 2384 2385 /* start a modeswitch now */ 2386 radeonfb_modeswitch(dp); 2387 } 2388 2389 /* 2390 * XXX: font selection should be based on properties, with some 2391 * normal/reasonable default. 2392 */ 2393 2394 /* initialize and look for an initial font */ 2395 rasops_init(ri, 0, 0); 2396 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2397 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2398 2399 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2400 dp->rd_virtx / ri->ri_font->fontwidth); 2401 2402 /* enable acceleration */ 2403 dp->rd_putchar = ri->ri_ops.putchar; 2404 ri->ri_ops.copyrows = radeonfb_copyrows; 2405 ri->ri_ops.copycols = radeonfb_copycols; 2406 ri->ri_ops.eraserows = radeonfb_eraserows; 2407 ri->ri_ops.erasecols = radeonfb_erasecols; 2408 /* pick a putchar method based on font and Radeon model */ 2409 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2410 /* got a bitmap font */ 2411 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2412 if (IS_R300(dp->rd_softc)) { 2413 /* 2414 * radeonfb_putchar() doesn't work right on some R3xx 2415 * so we use software drawing here, the wrapper just 2416 * makes sure the engine is idle before scribbling 2417 * into vram 2418 */ 2419 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2420 } else 2421 #endif 2422 ri->ri_ops.putchar = radeonfb_putchar; 2423 } else { 2424 /* got an alpha font */ 2425 switch(ri->ri_depth) { 2426 case 32: 2427 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2428 break; 2429 case 8: 2430 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2431 break; 2432 default: 2433 /* XXX this should never happen */ 2434 panic("%s: depth is not 8 or 32 but we got an" \ 2435 " alpha font?!", __func__); 2436 } 2437 } 2438 ri->ri_ops.cursor = radeonfb_cursor; 2439 } 2440 2441 void 2442 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2443 { 2444 uint32_t gen, ext, gen2 = 0; 2445 uint32_t agploc, aperbase, apersize, mcfbloc; 2446 2447 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2448 /* XXX */ 2449 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2450 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2451 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2452 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2453 2454 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2455 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2456 #if 0 2457 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2458 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2459 #endif 2460 2461 if (HAS_CRTC2(sc)) { 2462 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2463 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2464 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2465 } 2466 2467 delay(100000); 2468 2469 mcfbloc = (aperbase >> 16) | 2470 ((aperbase + (apersize - 1)) & 0xffff0000); 2471 2472 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2473 sc->sc_memsz = apersize; 2474 2475 if (((agploc & 0xffff) << 16) != 2476 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2477 agploc = mcfbloc & 0xffff0000U; 2478 agploc |= ((agploc + 0x10000) >> 16); 2479 } 2480 2481 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2482 2483 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2484 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2485 2486 DPRINTF(("aperbase = %u\n", aperbase)); 2487 PRINTREG(RADEON_MC_FB_LOCATION); 2488 PRINTREG(RADEON_MC_AGP_LOCATION); 2489 2490 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2491 2492 if (HAS_CRTC2(sc)) 2493 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2494 2495 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2496 2497 #if 0 2498 /* XXX: what is this AGP garbage? :-) */ 2499 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2500 #endif 2501 2502 delay(100000); 2503 2504 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2505 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2506 2507 if (HAS_CRTC2(sc)) 2508 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2509 } 2510 2511 void 2512 radeonfb_init_misc(struct radeonfb_softc *sc) 2513 { 2514 PUT32(sc, RADEON_BUS_CNTL, 2515 RADEON_BUS_MASTER_DIS | 2516 RADEON_BUS_PREFETCH_MODE_ACT | 2517 RADEON_BUS_PCI_READ_RETRY_EN | 2518 RADEON_BUS_PCI_WRT_RETRY_EN | 2519 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2520 RADEON_BUS_MSTR_RD_MULT | 2521 RADEON_BUS_MSTR_RD_LINE | 2522 RADEON_BUS_RD_DISCARD_EN | 2523 RADEON_BUS_MSTR_DISCONNECT_EN | 2524 RADEON_BUS_READ_BURST); 2525 2526 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2527 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2528 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2529 PUT32(sc, RADEON_RBBM_CNTL, 2530 (3 << RADEON_RB_SETTLE_SHIFT) | 2531 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2532 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2533 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2534 2535 /* XXX: figure out what these mean! */ 2536 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2537 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2538 #if 0 2539 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2540 #endif 2541 2542 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2543 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2544 } 2545 2546 /* 2547 * This loads a linear color map for true color. 2548 */ 2549 void 2550 radeonfb_init_palette(struct radeonfb_display *dp) 2551 { 2552 struct radeonfb_softc *sc = dp->rd_softc; 2553 int i, cc; 2554 uint32_t vclk; 2555 int crtc; 2556 2557 #define DAC_WIDTH ((1 << 10) - 1) 2558 #define CLUT_WIDTH ((1 << 8) - 1) 2559 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2560 2561 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2562 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2563 2564 /* initialize the palette for every CRTC used by this display */ 2565 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2566 crtc = dp->rd_crtcs[cc].rc_number; 2567 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2568 2569 if (crtc) 2570 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2571 else 2572 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2573 2574 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2575 2576 if (dp->rd_bpp == 8) { 2577 2578 /* R3G3B2 palette */ 2579 int j = 0; 2580 uint32_t tmp, r, g, b; 2581 2582 for (i = 0; i <= CLUT_WIDTH; ++i) { 2583 tmp = i & 0xe0; 2584 /* 2585 * replicate bits so 0xe0 maps to a red value of 0xff 2586 * in order to make white look actually white 2587 */ 2588 tmp |= (tmp >> 3) | (tmp >> 6); 2589 r = tmp; 2590 2591 tmp = (i & 0x1c) << 3; 2592 tmp |= (tmp >> 3) | (tmp >> 6); 2593 g = tmp; 2594 2595 tmp = (i & 0x03) << 6; 2596 tmp |= tmp >> 2; 2597 tmp |= tmp >> 4; 2598 b = tmp; 2599 2600 PUT32(sc, RADEON_PALETTE_30_DATA, 2601 (r << 22) | 2602 (g << 12) | 2603 (b << 2)); 2604 j += 3; 2605 } 2606 } else { 2607 /* linear ramp */ 2608 for (i = 0; i <= CLUT_WIDTH; ++i) { 2609 PUT32(sc, RADEON_PALETTE_30_DATA, 2610 (CLUT_COLOR(i) << 10) | 2611 (CLUT_COLOR(i) << 20) | 2612 (CLUT_COLOR(i))); 2613 } 2614 } 2615 } 2616 2617 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2618 PRINTREG(RADEON_DAC_CNTL2); 2619 2620 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2621 } 2622 2623 /* 2624 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2625 */ 2626 void 2627 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2628 { 2629 uint32_t tmp, save; 2630 2631 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2632 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2633 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2634 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2635 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2636 } 2637 2638 /* 2639 * Acceleration entry points. 2640 */ 2641 2642 /* this one draws characters using bitmap fonts */ 2643 static void 2644 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2645 { 2646 struct rasops_info *ri = cookie; 2647 struct vcons_screen *scr = ri->ri_hw; 2648 struct radeonfb_display *dp = scr->scr_cookie; 2649 struct radeonfb_softc *sc = dp->rd_softc; 2650 struct wsdisplay_font *font = PICK_FONT(ri, c); 2651 uint32_t w, h; 2652 int xd, yd, offset, i; 2653 uint32_t bg, fg, gmc; 2654 uint32_t reg; 2655 uint8_t *data8; 2656 uint16_t *data16; 2657 void *data; 2658 2659 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2660 return; 2661 2662 if (!CHAR_IN_FONT(c, font)) 2663 return; 2664 2665 w = font->fontwidth; 2666 h = font->fontheight; 2667 2668 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2669 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2670 2671 xd = ri->ri_xorigin + col * w; 2672 yd = ri->ri_yorigin + row * h; 2673 2674 if (c == 0x20) { 2675 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2676 return; 2677 } 2678 data = WSFONT_GLYPH(c, font); 2679 2680 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2681 2682 radeonfb_wait_fifo(sc, 9); 2683 2684 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2685 RADEON_GMC_BRUSH_NONE | 2686 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2687 RADEON_GMC_DST_CLIPPING | 2688 RADEON_ROP3_S | 2689 RADEON_DP_SRC_SOURCE_HOST_DATA | 2690 RADEON_GMC_CLR_CMP_CNTL_DIS | 2691 RADEON_GMC_WR_MSK_DIS | 2692 gmc); 2693 2694 PUT32(sc, RADEON_SC_LEFT, xd); 2695 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2696 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2697 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2698 PUT32(sc, RADEON_DP_CNTL, 2699 RADEON_DST_X_LEFT_TO_RIGHT | 2700 RADEON_DST_Y_TOP_TO_BOTTOM); 2701 2702 PUT32(sc, RADEON_SRC_X_Y, 0); 2703 offset = 32 - (font->stride << 3); 2704 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2705 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2706 2707 radeonfb_wait_fifo(sc, h); 2708 switch (font->stride) { 2709 case 1: { 2710 data8 = data; 2711 for (i = 0; i < h; i++) { 2712 reg = *data8; 2713 #if BYTE_ORDER == LITTLE_ENDIAN 2714 reg = reg << 24; 2715 #endif 2716 bus_space_write_stream_4(sc->sc_regt, 2717 sc->sc_regh, RADEON_HOST_DATA0, reg); 2718 data8++; 2719 } 2720 break; 2721 } 2722 case 2: { 2723 data16 = data; 2724 for (i = 0; i < h; i++) { 2725 reg = *data16; 2726 #if BYTE_ORDER == LITTLE_ENDIAN 2727 reg = reg << 16; 2728 #endif 2729 bus_space_write_stream_4(sc->sc_regt, 2730 sc->sc_regh, RADEON_HOST_DATA0, reg); 2731 data16++; 2732 } 2733 break; 2734 } 2735 } 2736 if (attr & 1) 2737 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2738 } 2739 2740 /* ... while this one is for anti-aliased ones */ 2741 static void 2742 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2743 { 2744 struct rasops_info *ri = cookie; 2745 struct vcons_screen *scr = ri->ri_hw; 2746 struct radeonfb_display *dp = scr->scr_cookie; 2747 struct radeonfb_softc *sc = dp->rd_softc; 2748 struct wsdisplay_font *font = PICK_FONT(ri, c); 2749 uint32_t bg, fg, gmc; 2750 uint8_t *data; 2751 int w, h, xd, yd; 2752 int i, r, g, b, aval; 2753 int rf, gf, bf, rb, gb, bb; 2754 uint32_t pixel; 2755 int rv; 2756 2757 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2758 return; 2759 2760 if (!CHAR_IN_FONT(c, font)) 2761 return; 2762 2763 w = font->fontwidth; 2764 h = font->fontheight; 2765 2766 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2767 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2768 2769 xd = ri->ri_xorigin + col * w; 2770 yd = ri->ri_yorigin + row * h; 2771 2772 if (c == 0x20) { 2773 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2774 if (attr & 1) 2775 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2776 return; 2777 } 2778 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2779 if (rv == GC_OK) 2780 return; 2781 2782 data = WSFONT_GLYPH(c, font); 2783 2784 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2785 2786 radeonfb_wait_fifo(sc, 5); 2787 2788 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2789 RADEON_GMC_BRUSH_NONE | 2790 RADEON_GMC_SRC_DATATYPE_COLOR | 2791 RADEON_ROP3_S | 2792 RADEON_DP_SRC_SOURCE_HOST_DATA | 2793 RADEON_GMC_CLR_CMP_CNTL_DIS | 2794 RADEON_GMC_WR_MSK_DIS | 2795 gmc); 2796 2797 PUT32(sc, RADEON_DP_CNTL, 2798 RADEON_DST_X_LEFT_TO_RIGHT | 2799 RADEON_DST_Y_TOP_TO_BOTTOM); 2800 2801 PUT32(sc, RADEON_SRC_X_Y, 0); 2802 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2803 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2804 2805 rf = (fg >> 16) & 0xff; 2806 rb = (bg >> 16) & 0xff; 2807 gf = (fg >> 8) & 0xff; 2808 gb = (bg >> 8) & 0xff; 2809 bf = fg & 0xff; 2810 bb = bg & 0xff; 2811 2812 /* 2813 * I doubt we can upload data faster than even the slowest Radeon 2814 * could process them, especially when doing the alpha blending stuff 2815 * along the way, so just make sure there's some room in the FIFO and 2816 * then hammer away 2817 * As it turns out we can, so make periodic stops to let the FIFO 2818 * drain. 2819 */ 2820 radeonfb_wait_fifo(sc, 20); 2821 for (i = 0; i < ri->ri_fontscale; i++) { 2822 aval = *data; 2823 data++; 2824 if (aval == 0) { 2825 pixel = bg; 2826 } else if (aval == 255) { 2827 pixel = fg; 2828 } else { 2829 r = aval * rf + (255 - aval) * rb; 2830 g = aval * gf + (255 - aval) * gb; 2831 b = aval * bf + (255 - aval) * bb; 2832 pixel = (r & 0xff00) << 8 | 2833 (g & 0xff00) | 2834 (b & 0xff00) >> 8; 2835 } 2836 if (i & 16) 2837 radeonfb_wait_fifo(sc, 20); 2838 PUT32(sc, RADEON_HOST_DATA0, pixel); 2839 } 2840 if (rv == GC_ADD) { 2841 glyphcache_add(&dp->rd_gc, c, xd, yd); 2842 } else 2843 if (attr & 1) 2844 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2845 2846 } 2847 2848 static void 2849 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2850 { 2851 struct rasops_info *ri = cookie; 2852 struct vcons_screen *scr = ri->ri_hw; 2853 struct radeonfb_display *dp = scr->scr_cookie; 2854 struct radeonfb_softc *sc = dp->rd_softc; 2855 struct wsdisplay_font *font = PICK_FONT(ri, c); 2856 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2857 int i, x, y, wi, he, r, g, b, aval; 2858 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2859 uint8_t *data8; 2860 int rv, cnt; 2861 2862 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2863 return; 2864 2865 if (!CHAR_IN_FONT(c, font)) 2866 return; 2867 2868 wi = font->fontwidth; 2869 he = font->fontheight; 2870 2871 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2872 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2873 2874 x = ri->ri_xorigin + col * wi; 2875 y = ri->ri_yorigin + row * he; 2876 2877 if (c == 0x20) { 2878 radeonfb_rectfill(dp, x, y, wi, he, bg); 2879 if (attr & 1) 2880 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2881 return; 2882 } 2883 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2884 if (rv == GC_OK) 2885 return; 2886 2887 data8 = WSFONT_GLYPH(c, font); 2888 2889 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2890 2891 radeonfb_wait_fifo(sc, 5); 2892 2893 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2894 RADEON_GMC_BRUSH_NONE | 2895 RADEON_GMC_SRC_DATATYPE_COLOR | 2896 RADEON_ROP3_S | 2897 RADEON_DP_SRC_SOURCE_HOST_DATA | 2898 RADEON_GMC_CLR_CMP_CNTL_DIS | 2899 RADEON_GMC_WR_MSK_DIS | 2900 gmc); 2901 2902 PUT32(sc, RADEON_DP_CNTL, 2903 RADEON_DST_X_LEFT_TO_RIGHT | 2904 RADEON_DST_Y_TOP_TO_BOTTOM); 2905 2906 PUT32(sc, RADEON_SRC_X_Y, 0); 2907 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2908 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2909 2910 /* 2911 * we need the RGB colours here, so get offsets into rasops_cmap 2912 */ 2913 fgo = ((attr >> 24) & 0xf) * 3; 2914 bgo = ((attr >> 16) & 0xf) * 3; 2915 2916 r0 = rasops_cmap[bgo]; 2917 r1 = rasops_cmap[fgo]; 2918 g0 = rasops_cmap[bgo + 1]; 2919 g1 = rasops_cmap[fgo + 1]; 2920 b0 = rasops_cmap[bgo + 2]; 2921 b1 = rasops_cmap[fgo + 2]; 2922 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2923 bg8 = R3G3B2(r0, g0, b0); 2924 fg8 = R3G3B2(r1, g1, b1); 2925 2926 radeonfb_wait_fifo(sc, 20); 2927 cnt = 0; 2928 for (i = 0; i < ri->ri_fontscale; i++) { 2929 aval = *data8; 2930 if (aval == 0) { 2931 pixel = bg8; 2932 } else if (aval == 255) { 2933 pixel = fg8; 2934 } else { 2935 r = aval * r1 + (255 - aval) * r0; 2936 g = aval * g1 + (255 - aval) * g0; 2937 b = aval * b1 + (255 - aval) * b0; 2938 pixel = ((r & 0xe000) >> 8) | 2939 ((g & 0xe000) >> 11) | 2940 ((b & 0xc000) >> 14); 2941 } 2942 latch |= pixel << (8 * (i & 3)); 2943 /* write in 32bit chunks */ 2944 if ((i & 3) == 3) { 2945 PUT32(sc, RADEON_HOST_DATA0, latch); 2946 /* 2947 * not strictly necessary, old data should be shifted 2948 * out 2949 */ 2950 latch = 0; 2951 cnt++; 2952 if (cnt > 16) { 2953 cnt = 0; 2954 radeonfb_wait_fifo(sc, 20); 2955 } 2956 } 2957 data8++; 2958 } 2959 /* if we have pixels left in latch write them out */ 2960 if ((i & 3) != 0) { 2961 /* 2962 * radeon is weird - apparently leftover pixels are written 2963 * from the middle, not from the left as everything else 2964 */ 2965 PUT32(sc, RADEON_HOST_DATA0, latch); 2966 } 2967 2968 if (rv == GC_ADD) { 2969 glyphcache_add(&dp->rd_gc, c, x, y); 2970 } else 2971 if (attr & 1) 2972 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2973 2974 } 2975 2976 /* 2977 * wrapper for software character drawing 2978 * just sync the engine and call rasops*_putchar() 2979 */ 2980 2981 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2982 static void 2983 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2984 { 2985 struct rasops_info *ri = cookie; 2986 struct vcons_screen *scr = ri->ri_hw; 2987 struct radeonfb_display *dp = scr->scr_cookie; 2988 2989 radeonfb_engine_idle(dp->rd_softc); 2990 dp->rd_putchar(ri, row, col, c, attr); 2991 } 2992 #endif 2993 2994 static void 2995 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2996 { 2997 struct rasops_info *ri = cookie; 2998 struct vcons_screen *scr = ri->ri_hw; 2999 struct radeonfb_display *dp = scr->scr_cookie; 3000 uint32_t x, y, w, h, fg, bg, ul; 3001 3002 /* XXX: check for full emulation mode? */ 3003 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3004 x = ri->ri_xorigin; 3005 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3006 w = ri->ri_emuwidth; 3007 h = ri->ri_font->fontheight * nrows; 3008 3009 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3010 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3011 } 3012 } 3013 3014 static void 3015 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3016 { 3017 struct rasops_info *ri = cookie; 3018 struct vcons_screen *scr = ri->ri_hw; 3019 struct radeonfb_display *dp = scr->scr_cookie; 3020 uint32_t x, ys, yd, w, h; 3021 3022 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3023 x = ri->ri_xorigin; 3024 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3025 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3026 w = ri->ri_emuwidth; 3027 h = ri->ri_font->fontheight * nrows; 3028 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3029 RADEON_ROP3_S); 3030 } 3031 } 3032 3033 static void 3034 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3035 { 3036 struct rasops_info *ri = cookie; 3037 struct vcons_screen *scr = ri->ri_hw; 3038 struct radeonfb_display *dp = scr->scr_cookie; 3039 uint32_t xs, xd, y, w, h; 3040 3041 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3042 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3043 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3044 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3045 w = ri->ri_font->fontwidth * ncols; 3046 h = ri->ri_font->fontheight; 3047 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3048 RADEON_ROP3_S); 3049 } 3050 } 3051 3052 static void 3053 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3054 long fillattr) 3055 { 3056 struct rasops_info *ri = cookie; 3057 struct vcons_screen *scr = ri->ri_hw; 3058 struct radeonfb_display *dp = scr->scr_cookie; 3059 uint32_t x, y, w, h, fg, bg, ul; 3060 3061 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3062 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3063 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3064 w = ri->ri_font->fontwidth * ncols; 3065 h = ri->ri_font->fontheight; 3066 3067 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3068 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3069 } 3070 } 3071 3072 static void 3073 radeonfb_cursor(void *cookie, int on, int row, int col) 3074 { 3075 struct rasops_info *ri = cookie; 3076 struct vcons_screen *scr = ri->ri_hw; 3077 struct radeonfb_display *dp = scr->scr_cookie; 3078 int x, y, wi, he; 3079 3080 wi = ri->ri_font->fontwidth; 3081 he = ri->ri_font->fontheight; 3082 3083 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3084 x = ri->ri_ccol * wi + ri->ri_xorigin; 3085 y = ri->ri_crow * he + ri->ri_yorigin; 3086 /* first turn off the old cursor */ 3087 if (ri->ri_flg & RI_CURSOR) { 3088 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3089 RADEON_ROP3_Dn); 3090 ri->ri_flg &= ~RI_CURSOR; 3091 } 3092 ri->ri_crow = row; 3093 ri->ri_ccol = col; 3094 /* then (possibly) turn on the new one */ 3095 if (on) { 3096 x = ri->ri_ccol * wi + ri->ri_xorigin; 3097 y = ri->ri_crow * he + ri->ri_yorigin; 3098 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3099 RADEON_ROP3_Dn); 3100 ri->ri_flg |= RI_CURSOR; 3101 } 3102 } else { 3103 scr->scr_ri.ri_crow = row; 3104 scr->scr_ri.ri_ccol = col; 3105 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3106 } 3107 } 3108 3109 /* 3110 * Underlying acceleration support. 3111 */ 3112 3113 static void 3114 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3115 int width, int height, uint32_t color) 3116 { 3117 struct radeonfb_softc *sc = dp->rd_softc; 3118 uint32_t gmc; 3119 3120 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3121 3122 radeonfb_wait_fifo(sc, 6); 3123 3124 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3125 RADEON_GMC_BRUSH_SOLID_COLOR | 3126 RADEON_GMC_SRC_DATATYPE_COLOR | 3127 RADEON_GMC_CLR_CMP_CNTL_DIS | 3128 RADEON_ROP3_P | gmc); 3129 3130 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3131 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3132 PUT32(sc, RADEON_DP_CNTL, 3133 RADEON_DST_X_LEFT_TO_RIGHT | 3134 RADEON_DST_Y_TOP_TO_BOTTOM); 3135 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3136 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3137 3138 } 3139 3140 static void 3141 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3142 int width, int height, long attr) 3143 { 3144 struct radeonfb_display *dp = cookie; 3145 3146 radeonfb_rectfill(dp, dstx, dsty, width, height, 3147 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3148 } 3149 3150 static void 3151 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3152 int dstx, int dsty, int width, int height, int rop) 3153 { 3154 struct radeonfb_display *dp = cookie; 3155 struct radeonfb_softc *sc = dp->rd_softc; 3156 uint32_t gmc; 3157 uint32_t dir; 3158 3159 if (dsty < srcy) { 3160 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3161 } else { 3162 srcy += height - 1; 3163 dsty += height - 1; 3164 dir = 0; 3165 } 3166 if (dstx < srcx) { 3167 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3168 } else { 3169 srcx += width - 1; 3170 dstx += width - 1; 3171 } 3172 3173 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3174 3175 radeonfb_wait_fifo(sc, 6); 3176 3177 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3178 RADEON_GMC_BRUSH_SOLID_COLOR | 3179 RADEON_GMC_SRC_DATATYPE_COLOR | 3180 RADEON_GMC_CLR_CMP_CNTL_DIS | 3181 RADEON_DP_SRC_SOURCE_MEMORY | 3182 rop | gmc); 3183 3184 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3185 PUT32(sc, RADEON_DP_CNTL, dir); 3186 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3187 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3188 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3189 } 3190 3191 static void 3192 radeonfb_engine_idle(struct radeonfb_softc *sc) 3193 { 3194 3195 radeonfb_wait_fifo(sc, 64); 3196 while ((GET32(sc, RADEON_RBBM_STATUS) & 3197 RADEON_RBBM_ACTIVE) != 0); 3198 radeonfb_engine_flush(sc); 3199 } 3200 3201 static inline void 3202 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3203 { 3204 int i; 3205 3206 for (i = RADEON_TIMEOUT; i; i--) { 3207 if ((GET32(sc, RADEON_RBBM_STATUS) & 3208 RADEON_RBBM_FIFOCNT_MASK) >= n) 3209 return; 3210 } 3211 #ifdef DIAGNOSTIC 3212 if (!i) 3213 printf("%s: timed out waiting for fifo (%x)\n", 3214 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3215 #endif 3216 } 3217 3218 static void 3219 radeonfb_engine_flush(struct radeonfb_softc *sc) 3220 { 3221 int i = 0; 3222 3223 if (IS_R300(sc)) { 3224 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3225 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3226 i++; 3227 } 3228 } else { 3229 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3230 RADEON_RB2D_DC_FLUSH_ALL); 3231 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3232 RADEON_RB2D_DC_BUSY) { 3233 i++; 3234 } 3235 } 3236 #ifdef DIAGNOSTIC 3237 if (i > RADEON_TIMEOUT) 3238 printf("%s: engine flush timed out!\n", XNAME(sc)); 3239 #endif 3240 } 3241 3242 static inline void 3243 radeonfb_unclip(struct radeonfb_softc *sc) 3244 { 3245 3246 radeonfb_wait_fifo(sc, 2); 3247 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3248 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3249 } 3250 3251 static void 3252 radeonfb_engine_init(struct radeonfb_display *dp) 3253 { 3254 struct radeonfb_softc *sc = dp->rd_softc; 3255 uint32_t pitch; 3256 3257 /* no 3D */ 3258 PUT32(sc, RADEON_RB3D_CNTL, 0); 3259 3260 radeonfb_engine_reset(sc); 3261 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3262 3263 radeonfb_wait_fifo(sc, 1); 3264 if (!IS_R300(sc)) 3265 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3266 3267 radeonfb_wait_fifo(sc, 3); 3268 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3269 (pitch << 22) | (sc->sc_aperbase >> 10)); 3270 3271 3272 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3273 (pitch << 22) | (sc->sc_aperbase >> 10)); 3274 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3275 (pitch << 22) | (sc->sc_aperbase >> 10)); 3276 3277 (void)GET32(sc, RADEON_DP_DATATYPE); 3278 3279 /* default scissors -- no clipping */ 3280 radeonfb_wait_fifo(sc, 1); 3281 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3282 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3283 3284 radeonfb_wait_fifo(sc, 1); 3285 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3286 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3287 RADEON_GMC_CLR_CMP_CNTL_DIS | 3288 RADEON_GMC_BRUSH_SOLID_COLOR | 3289 RADEON_GMC_SRC_DATATYPE_COLOR); 3290 3291 radeonfb_wait_fifo(sc, 10); 3292 PUT32(sc, RADEON_DST_LINE_START, 0); 3293 PUT32(sc, RADEON_DST_LINE_END, 0); 3294 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3295 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3296 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3297 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3298 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3299 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3300 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3301 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3302 radeonfb_engine_idle(sc); 3303 } 3304 3305 static void 3306 radeonfb_engine_reset(struct radeonfb_softc *sc) 3307 { 3308 uint32_t hpc, rbbm, mclkcntl, clkindex; 3309 3310 radeonfb_engine_flush(sc); 3311 3312 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3313 if (HAS_R300CG(sc)) 3314 radeonfb_r300cg_workaround(sc); 3315 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3316 3317 /* 3318 * According to comments in XFree code, resetting the HDP via 3319 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3320 * So we use HOST_PATH_CNTL instead. 3321 */ 3322 3323 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3324 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3325 if (IS_R300(sc)) { 3326 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3327 RADEON_SOFT_RESET_CP | 3328 RADEON_SOFT_RESET_HI | 3329 RADEON_SOFT_RESET_E2); 3330 GET32(sc, RADEON_RBBM_SOFT_RESET); 3331 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3332 /* 3333 * XXX: this bit is not defined in any ATI docs I have, 3334 * nor in the XFree code, but XFree does it. Why? 3335 */ 3336 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3337 } else { 3338 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3339 RADEON_SOFT_RESET_CP | 3340 RADEON_SOFT_RESET_SE | 3341 RADEON_SOFT_RESET_RE | 3342 RADEON_SOFT_RESET_PP | 3343 RADEON_SOFT_RESET_E2 | 3344 RADEON_SOFT_RESET_RB); 3345 GET32(sc, RADEON_RBBM_SOFT_RESET); 3346 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3347 ~(RADEON_SOFT_RESET_CP | 3348 RADEON_SOFT_RESET_SE | 3349 RADEON_SOFT_RESET_RE | 3350 RADEON_SOFT_RESET_PP | 3351 RADEON_SOFT_RESET_E2 | 3352 RADEON_SOFT_RESET_RB)); 3353 GET32(sc, RADEON_RBBM_SOFT_RESET); 3354 } 3355 3356 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3357 GET32(sc, RADEON_HOST_PATH_CNTL); 3358 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3359 3360 if (IS_R300(sc)) 3361 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3362 3363 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3364 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3365 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3366 3367 if (HAS_R300CG(sc)) 3368 radeonfb_r300cg_workaround(sc); 3369 } 3370 3371 static int 3372 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3373 { 3374 int x, y; 3375 3376 x = pos->x; 3377 y = pos->y; 3378 3379 /* 3380 * This doesn't let a cursor move off the screen. I'm not 3381 * sure if this will have negative effects for e.g. Xinerama. 3382 * I'd guess Xinerama handles it by changing the cursor shape, 3383 * but that needs verification. 3384 */ 3385 if (x >= dp->rd_virtx) 3386 x = dp->rd_virtx - 1; 3387 if (x < 0) 3388 x = 0; 3389 if (y >= dp->rd_virty) 3390 y = dp->rd_virty - 1; 3391 if (y < 0) 3392 y = 0; 3393 3394 dp->rd_cursor.rc_pos.x = x; 3395 dp->rd_cursor.rc_pos.y = y; 3396 3397 radeonfb_cursor_position(dp); 3398 return 0; 3399 } 3400 3401 static int 3402 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3403 { 3404 unsigned flags; 3405 3406 uint8_t r[2], g[2], b[2]; 3407 unsigned index, count; 3408 int i, err; 3409 int pitch, size; 3410 struct radeonfb_cursor nc; 3411 3412 flags = wc->which; 3413 3414 /* copy old values */ 3415 nc = dp->rd_cursor; 3416 3417 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3418 index = wc->cmap.index; 3419 count = wc->cmap.count; 3420 3421 if (index >= 2 || (index + count) > 2) 3422 return EINVAL; 3423 3424 err = copyin(wc->cmap.red, &r[index], count); 3425 if (err) 3426 return err; 3427 err = copyin(wc->cmap.green, &g[index], count); 3428 if (err) 3429 return err; 3430 err = copyin(wc->cmap.blue, &b[index], count); 3431 if (err) 3432 return err; 3433 3434 for (i = index; i < index + count; i++) { 3435 nc.rc_cmap[i] = 3436 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3437 } 3438 } 3439 3440 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3441 if ((wc->size.x > RADEON_CURSORMAXX) || 3442 (wc->size.y > RADEON_CURSORMAXY)) 3443 return EINVAL; 3444 3445 /* figure bytes per line */ 3446 pitch = (wc->size.x + 7) / 8; 3447 size = pitch * wc->size.y; 3448 3449 /* clear the old cursor and mask */ 3450 memset(nc.rc_image, 0, 512); 3451 memset(nc.rc_mask, 0, 512); 3452 3453 nc.rc_size = wc->size; 3454 3455 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3456 return err; 3457 3458 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3459 return err; 3460 } 3461 3462 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3463 nc.rc_hot = wc->hot; 3464 if (nc.rc_hot.x >= nc.rc_size.x) 3465 nc.rc_hot.x = nc.rc_size.x - 1; 3466 if (nc.rc_hot.y >= nc.rc_size.y) 3467 nc.rc_hot.y = nc.rc_size.y - 1; 3468 } 3469 3470 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3471 nc.rc_pos = wc->pos; 3472 if (nc.rc_pos.x >= dp->rd_virtx) 3473 nc.rc_pos.x = dp->rd_virtx - 1; 3474 #if 0 3475 if (nc.rc_pos.x < 0) 3476 nc.rc_pos.x = 0; 3477 #endif 3478 if (nc.rc_pos.y >= dp->rd_virty) 3479 nc.rc_pos.y = dp->rd_virty - 1; 3480 #if 0 3481 if (nc.rc_pos.y < 0) 3482 nc.rc_pos.y = 0; 3483 #endif 3484 } 3485 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3486 nc.rc_visible = wc->enable; 3487 } 3488 3489 dp->rd_cursor = nc; 3490 radeonfb_cursor_update(dp, wc->which); 3491 3492 return 0; 3493 } 3494 3495 /* 3496 * Change the cursor shape. Call this with the cursor locked to avoid 3497 * flickering/tearing. 3498 */ 3499 static void 3500 radeonfb_cursor_shape(struct radeonfb_display *dp) 3501 { 3502 uint8_t and[512], xor[512]; 3503 int i, j, src, dst /* , pitch */; 3504 const uint8_t *msk = dp->rd_cursor.rc_mask; 3505 const uint8_t *img = dp->rd_cursor.rc_image; 3506 3507 /* 3508 * Radeon cursor data interleaves one line of AND data followed 3509 * by a line of XOR data. (Each line corresponds to a whole hardware 3510 * pitch - i.e. 64 pixels or 8 bytes.) 3511 * 3512 * The cursor is displayed using the following table: 3513 * 3514 * AND XOR Result 3515 * ---------------------- 3516 * 0 0 Cursor color 0 3517 * 0 1 Cursor color 1 3518 * 1 0 Transparent 3519 * 1 1 Complement of background 3520 * 3521 * Our masks are therefore different from what we were passed. 3522 * Passed in, I'm assuming the data represents either color 0 or 1, 3523 * and a mask, so the passed in table looks like: 3524 * 3525 * IMG Mask Result 3526 * ----------------------- 3527 * 0 0 Transparent 3528 * 0 1 Cursor color 0 3529 * 1 0 Transparent 3530 * 1 1 Cursor color 1 3531 * 3532 * IF mask bit == 1, AND = 0, XOR = color. 3533 * IF mask bit == 0, AND = 1, XOR = 0. 3534 * 3535 * hence: AND = ~(mask); XOR = color & ~(mask); 3536 */ 3537 3538 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3539 3540 /* start by assuming all bits are transparent */ 3541 memset(and, 0xff, 512); 3542 memset(xor, 0x00, 512); 3543 3544 src = 0; 3545 dst = 0; 3546 for (i = 0; i < 64; i++) { 3547 for (j = 0; j < 64; j += 8) { 3548 if ((i < dp->rd_cursor.rc_size.y) && 3549 (j < dp->rd_cursor.rc_size.x)) { 3550 3551 /* take care to leave odd bits alone */ 3552 and[dst] &= ~(msk[src]); 3553 xor[dst] = img[src] & msk[src]; 3554 src++; 3555 } 3556 dst++; 3557 } 3558 } 3559 3560 /* copy the image into place */ 3561 for (i = 0; i < 64; i++) { 3562 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3563 &and[i * 8], 8); 3564 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3565 &xor[i * 8], 8); 3566 } 3567 } 3568 3569 static void 3570 radeonfb_cursor_position(struct radeonfb_display *dp) 3571 { 3572 struct radeonfb_softc *sc = dp->rd_softc; 3573 uint32_t offset, hvoff, hvpos; /* registers */ 3574 uint32_t coff; /* cursor offset */ 3575 int i, x, y, xoff, yoff, crtcoff; 3576 3577 /* 3578 * XXX: this also needs to handle pan/scan 3579 */ 3580 for (i = 0; i < dp->rd_ncrtcs; i++) { 3581 3582 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3583 3584 if (rcp->rc_number) { 3585 offset = RADEON_CUR2_OFFSET; 3586 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3587 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3588 crtcoff = RADEON_CRTC2_OFFSET; 3589 } else { 3590 offset = RADEON_CUR_OFFSET; 3591 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3592 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3593 crtcoff = RADEON_CRTC_OFFSET; 3594 } 3595 3596 x = dp->rd_cursor.rc_pos.x; 3597 y = dp->rd_cursor.rc_pos.y; 3598 3599 while (y < rcp->rc_yoffset) { 3600 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3601 } 3602 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3603 rcp->rc_yoffset += RADEON_PANINCREMENT; 3604 } 3605 while (x < rcp->rc_xoffset) { 3606 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3607 } 3608 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3609 rcp->rc_xoffset += RADEON_PANINCREMENT; 3610 } 3611 3612 /* adjust for the cursor's hotspot */ 3613 x -= dp->rd_cursor.rc_hot.x; 3614 y -= dp->rd_cursor.rc_hot.y; 3615 xoff = yoff = 0; 3616 3617 if (x >= dp->rd_virtx) 3618 x = dp->rd_virtx - 1; 3619 if (y >= dp->rd_virty) 3620 y = dp->rd_virty - 1; 3621 3622 /* now adjust cursor so it is relative to viewport */ 3623 x -= rcp->rc_xoffset; 3624 y -= rcp->rc_yoffset; 3625 3626 /* 3627 * no need to check for fall off, because we should 3628 * never move off the screen entirely! 3629 */ 3630 coff = 0; 3631 if (x < 0) { 3632 xoff = -x; 3633 x = 0; 3634 } 3635 if (y < 0) { 3636 yoff = -y; 3637 y = 0; 3638 coff = (yoff * 2) * 8; 3639 } 3640 3641 /* pan the display */ 3642 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3643 rcp->rc_xoffset); 3644 3645 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3646 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3647 /* NB: this unlocks the cursor */ 3648 PUT32(sc, hvpos, (x << 16) | y); 3649 } 3650 } 3651 3652 static void 3653 radeonfb_cursor_visible(struct radeonfb_display *dp) 3654 { 3655 int i; 3656 uint32_t gencntl, bit; 3657 3658 for (i = 0; i < dp->rd_ncrtcs; i++) { 3659 if (dp->rd_crtcs[i].rc_number) { 3660 gencntl = RADEON_CRTC2_GEN_CNTL; 3661 bit = RADEON_CRTC2_CUR_EN; 3662 } else { 3663 gencntl = RADEON_CRTC_GEN_CNTL; 3664 bit = RADEON_CRTC_CUR_EN; 3665 } 3666 3667 if (dp->rd_cursor.rc_visible) 3668 SET32(dp->rd_softc, gencntl, bit); 3669 else 3670 CLR32(dp->rd_softc, gencntl, bit); 3671 } 3672 } 3673 3674 static void 3675 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3676 { 3677 int i; 3678 uint32_t c0reg, c1reg; 3679 struct radeonfb_softc *sc = dp->rd_softc; 3680 3681 for (i = 0; i < dp->rd_ncrtcs; i++) { 3682 if (dp->rd_crtcs[i].rc_number) { 3683 c0reg = RADEON_CUR2_CLR0; 3684 c1reg = RADEON_CUR2_CLR1; 3685 } else { 3686 c0reg = RADEON_CUR_CLR0; 3687 c1reg = RADEON_CUR_CLR1; 3688 } 3689 3690 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3691 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3692 } 3693 } 3694 3695 static void 3696 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3697 { 3698 struct radeonfb_softc *sc; 3699 int i; 3700 3701 sc = dp->rd_softc; 3702 for (i = 0; i < dp->rd_ncrtcs; i++) { 3703 if (dp->rd_crtcs[i].rc_number) { 3704 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3705 } else { 3706 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3707 } 3708 } 3709 3710 if (which & WSDISPLAY_CURSOR_DOCMAP) 3711 radeonfb_cursor_cmap(dp); 3712 3713 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3714 radeonfb_cursor_shape(dp); 3715 3716 if (which & WSDISPLAY_CURSOR_DOCUR) 3717 radeonfb_cursor_visible(dp); 3718 3719 /* this one is unconditional, because it updates other stuff */ 3720 radeonfb_cursor_position(dp); 3721 } 3722 3723 static struct videomode * 3724 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3725 { 3726 int r1, r2; 3727 3728 /* otherwise pick the higher refresh rate */ 3729 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3730 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3731 3732 return (r1 < r2 ? m2 : m1); 3733 } 3734 3735 static const struct videomode * 3736 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3737 int x, int y) 3738 { 3739 struct edid_info *ep = &rp->rp_edid; 3740 struct videomode *vmp = NULL; 3741 int i; 3742 3743 if (!rp->rp_edid_valid) { 3744 /* fallback to safe mode */ 3745 return radeonfb_modelookup(sc->sc_defaultmode); 3746 } 3747 3748 /* always choose the preferred mode first! */ 3749 if (ep->edid_preferred_mode) { 3750 3751 /* XXX: add auto-stretching support for native mode */ 3752 3753 /* this may want panning to occur, btw */ 3754 if ((ep->edid_preferred_mode->hdisplay <= x) && 3755 (ep->edid_preferred_mode->vdisplay <= y)) 3756 return ep->edid_preferred_mode; 3757 } 3758 3759 for (i = 0; i < ep->edid_nmodes; i++) { 3760 /* 3761 * We elect to pick a resolution that is too large for 3762 * the monitor than one that is too small. This means 3763 * that we will prefer to pan rather than to try to 3764 * center a smaller display on a larger screen. In 3765 * practice, this shouldn't matter because if a 3766 * monitor can support a larger resolution, it can 3767 * probably also support the smaller. A specific 3768 * exception is fixed format panels, but hopefully 3769 * they are properly dealt with by the "autostretch" 3770 * logic above. 3771 */ 3772 if ((ep->edid_modes[i].hdisplay > x) || 3773 (ep->edid_modes[i].vdisplay > y)) { 3774 continue; 3775 } 3776 3777 /* 3778 * at this point, the display mode is no larger than 3779 * what we've requested. 3780 */ 3781 if (vmp == NULL) 3782 vmp = &ep->edid_modes[i]; 3783 3784 /* eliminate smaller modes */ 3785 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3786 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3787 continue; 3788 3789 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3790 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3791 vmp = &ep->edid_modes[i]; 3792 continue; 3793 } 3794 3795 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3796 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3797 3798 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3799 } 3800 3801 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3802 } 3803 3804 static int 3805 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3806 { 3807 int i; 3808 3809 for (i = 0; i < nlist; i++) { 3810 if ((x == list[i].hdisplay) && 3811 (y == list[i].vdisplay)) { 3812 return 1; 3813 } 3814 } 3815 return 0; 3816 } 3817 3818 static void 3819 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3820 int pan) 3821 { 3822 struct radeonfb_port *rp; 3823 struct edid_info *ep; 3824 int i, j; 3825 3826 *x = 0; 3827 *y = 0; 3828 3829 if (pan) { 3830 for (i = 0; i < dp->rd_ncrtcs; i++) { 3831 rp = dp->rd_crtcs[i].rc_port; 3832 ep = &rp->rp_edid; 3833 if (!rp->rp_edid_valid) { 3834 /* monitor not present */ 3835 continue; 3836 } 3837 3838 /* 3839 * For now we are ignoring "conflict" that 3840 * could occur when mixing some modes like 3841 * 1280x1024 and 1400x800. It isn't clear 3842 * which is better, so the first one wins. 3843 */ 3844 for (j = 0; j < ep->edid_nmodes; j++) { 3845 /* 3846 * ignore resolutions that are too big for 3847 * the radeon 3848 */ 3849 if (ep->edid_modes[j].hdisplay > 3850 dp->rd_softc->sc_maxx) 3851 continue; 3852 if (ep->edid_modes[j].vdisplay > 3853 dp->rd_softc->sc_maxy) 3854 continue; 3855 3856 /* 3857 * pick largest resolution, the 3858 * smaller monitor will pan 3859 */ 3860 if ((ep->edid_modes[j].hdisplay >= *x) && 3861 (ep->edid_modes[j].vdisplay >= *y)) { 3862 *x = ep->edid_modes[j].hdisplay; 3863 *y = ep->edid_modes[j].vdisplay; 3864 } 3865 } 3866 } 3867 3868 } else { 3869 struct videomode modes[64]; 3870 int nmodes = 0; 3871 int valid = 0; 3872 3873 for (i = 0; i < dp->rd_ncrtcs; i++) { 3874 /* 3875 * pick the largest resolution in common. 3876 */ 3877 rp = dp->rd_crtcs[i].rc_port; 3878 ep = &rp->rp_edid; 3879 3880 if (!rp->rp_edid_valid) 3881 continue; 3882 3883 if (!valid) { 3884 /* 3885 * Pick the preferred mode for this port 3886 * if available. 3887 */ 3888 if (ep->edid_preferred_mode) { 3889 struct videomode *vmp = 3890 ep->edid_preferred_mode; 3891 3892 if ((vmp->hdisplay <= 3893 dp->rd_softc->sc_maxx) && 3894 (vmp->vdisplay <= 3895 dp->rd_softc->sc_maxy)) 3896 modes[nmodes++] = *vmp; 3897 } else { 3898 3899 /* initialize starting list */ 3900 for (j = 0; j < ep->edid_nmodes; j++) { 3901 /* 3902 * ignore resolutions that are 3903 * too big for the radeon 3904 */ 3905 if (ep->edid_modes[j].hdisplay > 3906 dp->rd_softc->sc_maxx) 3907 continue; 3908 if (ep->edid_modes[j].vdisplay > 3909 dp->rd_softc->sc_maxy) 3910 continue; 3911 3912 modes[nmodes] = 3913 ep->edid_modes[j]; 3914 nmodes++; 3915 } 3916 } 3917 valid = 1; 3918 } else { 3919 /* merge into preexisting list */ 3920 for (j = 0; j < nmodes; j++) { 3921 if (!radeonfb_hasres(ep->edid_modes, 3922 ep->edid_nmodes, 3923 modes[j].hdisplay, 3924 modes[j].vdisplay)) { 3925 modes[j] = modes[nmodes]; 3926 j--; 3927 nmodes--; 3928 } 3929 } 3930 } 3931 } 3932 3933 /* now we have to pick from the merged list */ 3934 for (i = 0; i < nmodes; i++) { 3935 if ((modes[i].hdisplay >= *x) && 3936 (modes[i].vdisplay >= *y)) { 3937 *x = modes[i].hdisplay; 3938 *y = modes[i].vdisplay; 3939 } 3940 } 3941 } 3942 3943 if ((*x == 0) || (*y == 0)) { 3944 /* fallback to safe mode */ 3945 *x = 640; 3946 *y = 480; 3947 } 3948 } 3949 3950 /* 3951 * backlight levels are linear on: 3952 * - RV200, RV250, RV280, RV350 3953 * - but NOT on PowerBook4,3 6,3 6,5 3954 * according to Linux' radeonfb 3955 */ 3956 3957 /* Get the current backlight level for the display. */ 3958 3959 static int 3960 radeonfb_get_backlight(struct radeonfb_display *dp) 3961 { 3962 int s; 3963 uint32_t level; 3964 3965 s = spltty(); 3966 3967 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3968 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3969 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3970 3971 /* 3972 * On some chips, we should negate the backlight level. 3973 * XXX Find out on which chips. 3974 */ 3975 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3976 level = RADEONFB_BACKLIGHT_MAX - level; 3977 3978 splx(s); 3979 3980 return level; 3981 } 3982 3983 /* Set the backlight to the given level for the display. */ 3984 static void 3985 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3986 { 3987 if (dp->rd_bl_on == on) 3988 return; 3989 dp->rd_bl_on = on; 3990 radeonfb_set_backlight(dp, dp->rd_bl_level); 3991 } 3992 3993 static int 3994 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3995 { 3996 struct radeonfb_softc *sc; 3997 int rlevel, s; 3998 uint32_t lvds; 3999 4000 s = spltty(); 4001 4002 dp->rd_bl_level = level; 4003 if (dp->rd_bl_on == 0) 4004 level = 0; 4005 4006 if (level < 0) 4007 level = 0; 4008 else if (level >= RADEONFB_BACKLIGHT_MAX) 4009 level = RADEONFB_BACKLIGHT_MAX; 4010 4011 sc = dp->rd_softc; 4012 4013 /* On some chips, we should negate the backlight level. */ 4014 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4015 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4016 } else 4017 rlevel = level; 4018 4019 callout_stop(&dp->rd_bl_lvds_co); 4020 radeonfb_engine_idle(sc); 4021 4022 /* 4023 * Turn off the display if the backlight is set to 0, since the 4024 * display is useless without backlight anyway. 4025 */ 4026 if (level == 0) 4027 radeonfb_blank(dp, 1); 4028 else if (radeonfb_get_backlight(dp) == 0) 4029 radeonfb_blank(dp, 0); 4030 4031 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4032 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4033 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4034 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4035 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4036 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4037 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4038 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4039 lvds |= RADEON_LVDS_ON; 4040 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4041 } else { 4042 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4043 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4044 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4045 } 4046 4047 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4048 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4049 /* XXX What is the correct delay? */ 4050 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4051 4052 splx(s); 4053 4054 return 0; 4055 } 4056 4057 /* 4058 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4059 * Set the delayed bits in the register, and clear the stored delayed 4060 * value. 4061 */ 4062 4063 static void radeonfb_lvds_callout(void *arg) 4064 { 4065 struct radeonfb_display *dp = arg; 4066 int s; 4067 4068 s = splhigh(); 4069 4070 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4071 dp->rd_bl_lvds_val); 4072 dp->rd_bl_lvds_val = 0; 4073 4074 splx(s); 4075 } 4076 4077 static void 4078 radeonfb_brightness_up(device_t dev) 4079 { 4080 struct radeonfb_softc *sc = device_private(dev); 4081 struct radeonfb_display *dp = &sc->sc_displays[0]; 4082 int level; 4083 4084 /* we assume the main display is the first one - need a better way */ 4085 if (sc->sc_ndisplays < 1) return; 4086 /* make sure pushing the hotkeys always has an effect */ 4087 dp->rd_bl_on = 1; 4088 level = dp->rd_bl_level; 4089 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4090 radeonfb_set_backlight(dp, level); 4091 } 4092 4093 static void 4094 radeonfb_brightness_down(device_t dev) 4095 { 4096 struct radeonfb_softc *sc = device_private(dev); 4097 struct radeonfb_display *dp = &sc->sc_displays[0]; 4098 int level; 4099 4100 /* we assume the main display is the first one - need a better way */ 4101 if (sc->sc_ndisplays < 1) return; 4102 /* make sure pushing the hotkeys always has an effect */ 4103 dp->rd_bl_on = 1; 4104 level = dp->rd_bl_level; 4105 level = max(0, level - 5); 4106 radeonfb_set_backlight(dp, level); 4107 } 4108