1 /* $NetBSD: radeonfb.c,v 1.35 2010/05/04 05:00:33 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.35 2010/05/04 05:00:33 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 102 static int radeonfb_match(device_t, cfdata_t, void *); 103 static void radeonfb_attach(device_t, device_t, void *); 104 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 105 struct lwp *); 106 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 107 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 108 static void radeonfb_loadbios(struct radeonfb_softc *, 109 struct pci_attach_args *); 110 111 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 112 uintmax_t); 113 static int radeonfb_getclocks(struct radeonfb_softc *); 114 static int radeonfb_gettmds(struct radeonfb_softc *); 115 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 116 uint32_t *, uint32_t *); 117 static int radeonfb_getconnectors(struct radeonfb_softc *); 118 static const struct videomode *radeonfb_modelookup(const char *); 119 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 120 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 121 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 122 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 123 static void radeonfb_modeswitch(struct radeonfb_display *); 124 static void radeonfb_setcrtc(struct radeonfb_display *, int); 125 static void radeonfb_init_misc(struct radeonfb_softc *); 126 static void radeonfb_set_fbloc(struct radeonfb_softc *); 127 static void radeonfb_init_palette(struct radeonfb_softc *, int); 128 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 129 130 static int radeonfb_isblank(struct radeonfb_display *); 131 static void radeonfb_blank(struct radeonfb_display *, int); 132 static int radeonfb_set_cursor(struct radeonfb_display *, 133 struct wsdisplay_cursor *); 134 static int radeonfb_set_curpos(struct radeonfb_display *, 135 struct wsdisplay_curpos *); 136 137 /* acceleration support */ 138 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 139 int width, int height, uint32_t color); 140 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 141 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 142 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 143 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 144 int, uint32_t, uint32_t); 145 146 /* hw cursor support */ 147 static void radeonfb_cursor_cmap(struct radeonfb_display *); 148 static void radeonfb_cursor_shape(struct radeonfb_display *); 149 static void radeonfb_cursor_position(struct radeonfb_display *); 150 static void radeonfb_cursor_visible(struct radeonfb_display *); 151 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 152 153 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 154 static void radeonfb_engine_idle(struct radeonfb_softc *); 155 static void radeonfb_engine_flush(struct radeonfb_softc *); 156 static void radeonfb_engine_reset(struct radeonfb_softc *); 157 static void radeonfb_engine_init(struct radeonfb_display *); 158 static inline void radeonfb_unclip(struct radeonfb_softc *); 159 160 static void radeonfb_eraserows(void *, int, int, long); 161 static void radeonfb_erasecols(void *, int, int, int, long); 162 static void radeonfb_copyrows(void *, int, int, int); 163 static void radeonfb_copycols(void *, int, int, int, int); 164 static void radeonfb_cursor(void *, int, int, int); 165 static void radeonfb_putchar(void *, int, int, unsigned, long); 166 static int radeonfb_allocattr(void *, int, int, int, long *); 167 168 static int radeonfb_get_backlight(struct radeonfb_display *); 169 static int radeonfb_set_backlight(struct radeonfb_display *, int); 170 static void radeonfb_lvds_callout(void *); 171 172 static void radeonfb_brightness_up(device_t); 173 static void radeonfb_brightness_down(device_t); 174 175 static struct videomode *radeonfb_best_refresh(struct videomode *, 176 struct videomode *); 177 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 178 uint16_t *, int); 179 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 180 struct radeonfb_port *, int, int); 181 182 static int radeonfb_drm_print(void *, const char *); 183 184 #ifdef RADEON_DEBUG 185 int radeon_debug = 1; 186 #define DPRINTF(x) \ 187 if (radeon_debug) printf x 188 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 189 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 190 #else 191 #define DPRINTF(x) 192 #define PRINTREG(r) 193 #define PRINTPLL(r) 194 #endif 195 196 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 197 198 #ifndef RADEON_DEFAULT_MODE 199 /* any reasonably modern display should handle this */ 200 #define RADEON_DEFAULT_MODE "1024x768x60" 201 #endif 202 203 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 204 205 static struct { 206 int size; /* minimum memory size (MB) */ 207 int maxx; /* maximum x dimension */ 208 int maxy; /* maximum y dimension */ 209 int maxbpp; /* maximum bpp */ 210 int maxdisp; /* maximum logical display count */ 211 } radeonfb_limits[] = { 212 { 32, 2048, 1536, 32, 2 }, 213 { 16, 1600, 1200, 32, 2 }, 214 { 8, 1600, 1200, 32, 1 }, 215 { 0, 0, 0, 0, 0 }, 216 }; 217 218 static struct wsscreen_descr radeonfb_stdscreen = { 219 "fb", /* name */ 220 0, 0, /* ncols, nrows */ 221 NULL, /* textops */ 222 8, 16, /* fontwidth, fontheight */ 223 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 224 0, /* modecookie */ 225 }; 226 227 struct wsdisplay_accessops radeonfb_accessops = { 228 radeonfb_ioctl, 229 radeonfb_mmap, 230 NULL, /* vcons_alloc_screen */ 231 NULL, /* vcons_free_screen */ 232 NULL, /* vcons_show_screen */ 233 NULL, /* load_font */ 234 NULL, /* pollc */ 235 NULL, /* scroll */ 236 }; 237 238 static struct { 239 uint16_t devid; 240 uint16_t family; 241 uint16_t flags; 242 } radeonfb_devices[] = 243 { 244 /* R100 family */ 245 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 246 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 247 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 248 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 249 250 /* RV100 family */ 251 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 252 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 253 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 255 256 /* RS100 family */ 257 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 259 260 /* RS200/RS250 family */ 261 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 265 266 /* R200 family */ 267 /* add more R200 products? , 5148 */ 268 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 271 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 273 274 /* RV200 family */ 275 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 279 280 /* RV250 family */ 281 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 284 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 285 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 286 287 /* RS300 family */ 288 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 292 293 /* RV280 family */ 294 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 301 302 /* R300 family */ 303 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 311 312 /* RV350/RV360 family */ 313 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 325 326 /* R350/R360 family */ 327 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 335 336 /* RV380/RV370 family */ 337 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 346 347 /* R420/R423 family */ 348 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 365 366 { 0, 0, 0 } 367 }; 368 369 static struct { 370 int divider; 371 int mask; 372 } radeonfb_dividers[] = { 373 { 1, 0 }, 374 { 2, 1 }, 375 { 3, 4 }, 376 { 4, 2 }, 377 { 6, 6 }, 378 { 8, 3 }, 379 { 12, 7 }, 380 { 0, 0 } 381 }; 382 383 /* 384 * This table taken from X11. 385 */ 386 static const struct { 387 int family; 388 struct radeon_tmds_pll plls[4]; 389 } radeonfb_tmds_pll[] = { 390 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 392 { RADEON_RS100, {{0, 0}}}, 393 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 394 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 395 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 396 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 397 { RADEON_RS300, {{0, 0}}}, 398 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 399 { RADEON_R300, {{-1, 0xb01cb}}}, 400 { RADEON_R350, {{-1, 0xb01cb}}}, 401 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 402 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 403 { RADEON_R420, {{-1, 0xb01cb}}}, 404 }; 405 406 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 407 408 409 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 410 radeonfb_match, radeonfb_attach, NULL, NULL); 411 412 static int 413 radeonfb_match(device_t parent, cfdata_t match, void *aux) 414 { 415 struct pci_attach_args *pa = aux; 416 int i; 417 418 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 419 return 0; 420 421 for (i = 0; radeonfb_devices[i].devid; i++) { 422 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 423 return 100; /* high to defeat VGA/VESA */ 424 } 425 426 return 0; 427 } 428 429 static void 430 radeonfb_attach(device_t parent, device_t dev, void *aux) 431 { 432 struct radeonfb_softc *sc = device_private(dev); 433 struct pci_attach_args *pa = aux; 434 const char *mptr; 435 bus_size_t bsz; 436 pcireg_t screg; 437 int i, j, fg, bg, ul, flags; 438 uint32_t v; 439 440 sc->sc_id = pa->pa_id; 441 for (i = 0; radeonfb_devices[i].devid; i++) { 442 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 443 break; 444 } 445 446 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 447 sizeof(sc->sc_devinfo)); 448 449 aprint_naive("\n"); 450 aprint_normal(": %s\n", sc->sc_devinfo); 451 452 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 453 454 KASSERT(radeonfb_devices[i].devid != 0); 455 sc->sc_pt = pa->pa_tag; 456 sc->sc_iot = pa->pa_iot; 457 sc->sc_pc = pa->pa_pc; 458 sc->sc_family = radeonfb_devices[i].family; 459 sc->sc_flags = radeonfb_devices[i].flags; 460 461 /* enable memory and IO access */ 462 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 463 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 464 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 465 466 /* 467 * Some flags are general to entire chip families, and rather 468 * than clutter up the table with them, we go ahead and set 469 * them here. 470 */ 471 switch (sc->sc_family) { 472 case RADEON_RS100: 473 case RADEON_RS200: 474 sc->sc_flags |= RFB_IGP | RFB_RV100; 475 break; 476 477 case RADEON_RV100: 478 case RADEON_RV200: 479 case RADEON_RV250: 480 case RADEON_RV280: 481 sc->sc_flags |= RFB_RV100; 482 break; 483 484 case RADEON_RS300: 485 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 486 break; 487 488 case RADEON_R300: 489 case RADEON_RV350: 490 case RADEON_R350: 491 case RADEON_RV380: 492 case RADEON_R420: 493 /* newer chips */ 494 sc->sc_flags |= RFB_R300; 495 break; 496 497 case RADEON_R100: 498 sc->sc_flags |= RFB_NCRTC2; 499 break; 500 } 501 502 if ((sc->sc_family == RADEON_RV200) || 503 (sc->sc_family == RADEON_RV250) || 504 (sc->sc_family == RADEON_RV280) || 505 (sc->sc_family == RADEON_RV350)) { 506 bool inverted = 0; 507 /* backlight level is linear */ 508 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 509 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 510 "backlight_level_reverted", &inverted); 511 if (inverted) { 512 DPRINTF(("nope, it's inverted\n")); 513 sc->sc_flags |= RFB_INV_BLIGHT; 514 } 515 } else 516 sc->sc_flags |= RFB_INV_BLIGHT; 517 518 /* 519 * XXX: to support true multihead, this must change. 520 */ 521 sc->sc_ndisplays = 1; 522 523 /* XXX: */ 524 if (!HAS_CRTC2(sc)) { 525 sc->sc_ndisplays = 1; 526 } 527 528 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 529 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 530 &sc->sc_regsz) != 0) { 531 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 532 goto error; 533 } 534 535 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 536 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 537 { 538 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 539 goto error; 540 } 541 sc->sc_romt = sc->sc_memt; 542 543 /* scratch register test... */ 544 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 545 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 546 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 547 goto error; 548 } 549 550 PRINTREG(RADEON_BIOS_4_SCRATCH); 551 PRINTREG(RADEON_FP_GEN_CNTL); 552 PRINTREG(RADEON_FP2_GEN_CNTL); 553 PRINTREG(RADEON_TMDS_CNTL); 554 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 555 PRINTREG(RADEON_TMDS_PLL_CNTL); 556 PRINTREG(RADEON_LVDS_GEN_CNTL); 557 PRINTREG(RADEON_FP_HORZ_STRETCH); 558 PRINTREG(RADEON_FP_VERT_STRETCH); 559 560 /* XXX: RV100 specific */ 561 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 562 563 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 564 RADEON_TMDS_TRANSMITTER_PLLEN, 565 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 566 567 radeonfb_i2c_init(sc); 568 569 radeonfb_loadbios(sc, pa); 570 571 #ifdef RADEON_BIOS_INIT 572 if (radeonfb_bios_init(sc)) { 573 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 574 goto error; 575 } 576 #endif 577 578 if (radeonfb_getclocks(sc)) { 579 aprint_error("%s: Unable to get reference clocks from BIOS\n", 580 XNAME(sc)); 581 goto error; 582 } 583 584 if (radeonfb_gettmds(sc)) { 585 aprint_error("%s: Unable to identify TMDS PLL settings\n", 586 XNAME(sc)); 587 goto error; 588 } 589 590 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 591 "minpll = %d, maxpll = %d\n", XNAME(sc), 592 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 593 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 594 595 radeonfb_getconnectors(sc); 596 597 radeonfb_set_fbloc(sc); 598 599 for (i = 0; radeonfb_limits[i].size; i++) { 600 if (sc->sc_memsz >= radeonfb_limits[i].size) { 601 sc->sc_maxx = radeonfb_limits[i].maxx; 602 sc->sc_maxy = radeonfb_limits[i].maxy; 603 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 604 /* framebuffer offset, start at a 4K page */ 605 sc->sc_fboffset = sc->sc_memsz / 606 radeonfb_limits[i].maxdisp; 607 /* 608 * we use the fbsize to figure out where we can store 609 * things like cursor data. 610 */ 611 sc->sc_fbsize = 612 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 613 RADEON_STRIDEALIGN) * sc->sc_maxy, 614 4096); 615 break; 616 } 617 } 618 619 620 radeonfb_init_misc(sc); 621 radeonfb_init_palette(sc, 0); 622 if (HAS_CRTC2(sc)) 623 radeonfb_init_palette(sc, 1); 624 625 /* program the DAC wirings */ 626 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 627 switch (sc->sc_ports[i].rp_dac_type) { 628 case RADEON_DAC_PRIMARY: 629 PATCH32(sc, RADEON_DAC_CNTL2, 630 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 631 ~RADEON_DAC2_DAC_CLK_SEL); 632 break; 633 case RADEON_DAC_TVDAC: 634 /* we always use the TVDAC to drive a secondary analog 635 * CRT for now. if we ever support TV-out this will 636 * have to change. 637 */ 638 SET32(sc, RADEON_DAC_CNTL2, 639 RADEON_DAC2_DAC2_CLK_SEL); 640 PATCH32(sc, RADEON_DISP_HW_DEBUG, 641 i ? 0 : RADEON_CRT2_DISP1_SEL, 642 ~RADEON_CRT2_DISP1_SEL); 643 break; 644 } 645 } 646 PRINTREG(RADEON_DAC_CNTL2); 647 PRINTREG(RADEON_DISP_HW_DEBUG); 648 649 /* other DAC programming */ 650 v = GET32(sc, RADEON_DAC_CNTL); 651 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 652 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 653 PUT32(sc, RADEON_DAC_CNTL, v); 654 PRINTREG(RADEON_DAC_CNTL); 655 656 /* XXX: this may need more investigation */ 657 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 658 PRINTREG(RADEON_TV_DAC_CNTL); 659 660 /* enable TMDS */ 661 SET32(sc, RADEON_FP_GEN_CNTL, 662 RADEON_FP_TMDS_EN | 663 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 664 RADEON_FP_CRTC_DONT_SHADOW_HEND); 665 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 666 if (HAS_CRTC2(sc)) 667 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 668 669 /* 670 * we use bus_space_map instead of pci_mapreg, because we don't 671 * need the full aperature space. no point in wasting virtual 672 * address space we don't intend to use, right? 673 */ 674 if ((sc->sc_memsz < (4096 * 1024)) || 675 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 676 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 677 (bsz < sc->sc_memsz)) { 678 sc->sc_memsz = 0; 679 aprint_error("%s: Bad frame buffer configuration\n", 680 XNAME(sc)); 681 goto error; 682 } 683 684 /* 64 MB should be enough -- more just wastes map entries */ 685 if (sc->sc_memsz > (64 << 20)) 686 sc->sc_memsz = (64 << 20); 687 688 sc->sc_memt = pa->pa_memt; 689 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 690 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 691 sc->sc_memsz = 0; 692 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 693 goto error; 694 } 695 696 aprint_normal("%s: %d MB aperture at 0x%08x, " 697 "%d KB registers at 0x%08x\n", XNAME(sc), 698 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 699 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 700 701 /* setup default video mode from devprop (allows PROM override) */ 702 sc->sc_defaultmode = radeonfb_default_mode; 703 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 704 "videomode", &mptr)) { 705 706 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 707 sc->sc_defaultmode = sc->sc_modebuf; 708 } 709 710 /* initialize some basic display parameters */ 711 for (i = 0; i < sc->sc_ndisplays; i++) { 712 struct radeonfb_display *dp = &sc->sc_displays[i]; 713 struct rasops_info *ri; 714 long defattr; 715 struct wsemuldisplaydev_attach_args aa; 716 717 /* 718 * Figure out how many "displays" (desktops) we are going to 719 * support. If more than one, then each CRTC gets its own 720 * programming. 721 * 722 * XXX: this code needs to change to support mergedfb. 723 * XXX: would be nice to allow this to be overridden 724 */ 725 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 726 DPRINTF(("dual crtcs!\n")); 727 dp->rd_ncrtcs = 2; 728 dp->rd_crtcs[0].rc_number = 0; 729 dp->rd_crtcs[1].rc_number = 1; 730 } else { 731 dp->rd_ncrtcs = 1; 732 dp->rd_crtcs[0].rc_number = i; 733 } 734 735 /* set up port pointer */ 736 for (j = 0; j < dp->rd_ncrtcs; j++) { 737 dp->rd_crtcs[j].rc_port = 738 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 739 } 740 741 dp->rd_softc = sc; 742 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 743 dp->rd_bg = WS_DEFAULT_BG; 744 #if 0 745 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 746 #else 747 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 748 #endif 749 /* for text mode, we pick a resolution that won't 750 * require panning */ 751 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 752 753 aprint_normal("%s: display %d: " 754 "initial virtual resolution %dx%d at %d bpp\n", 755 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 756 757 /* now select the *video mode* that we will use */ 758 for (j = 0; j < dp->rd_ncrtcs; j++) { 759 const struct videomode *vmp; 760 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 761 dp->rd_virtx, dp->rd_virty); 762 763 /* 764 * virtual resolution should be at least as high as 765 * physical 766 */ 767 if (dp->rd_virtx < vmp->hdisplay || 768 dp->rd_virty < vmp->vdisplay) { 769 dp->rd_virtx = vmp->hdisplay; 770 dp->rd_virty = vmp->vdisplay; 771 } 772 773 dp->rd_crtcs[j].rc_videomode = *vmp; 774 printf("%s: port %d: physical %dx%d %dHz\n", 775 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 776 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 777 vmp->htotal), vmp->vtotal)); 778 } 779 780 /* N.B.: radeon wants 64-byte aligned stride */ 781 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 782 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 783 784 dp->rd_offset = sc->sc_fboffset * i; 785 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 786 sc->sc_memh) + dp->rd_offset; 787 dp->rd_curoff = sc->sc_fbsize; 788 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 789 790 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 791 792 switch (dp->rd_bpp) { 793 case 8: 794 dp->rd_format = 2; 795 break; 796 case 32: 797 dp->rd_format = 6; 798 break; 799 default: 800 aprint_error("%s: bad depth %d\n", XNAME(sc), 801 dp->rd_bpp); 802 goto error; 803 } 804 805 printf("init engine\n"); 806 /* XXX: this seems suspicious - per display engine 807 initialization? */ 808 radeonfb_engine_init(dp); 809 810 /* copy the template into place */ 811 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 812 dp->rd_wsscreens = dp->rd_wsscreens_storage; 813 814 /* and make up the list */ 815 dp->rd_wsscreenlist.nscreens = 1; 816 dp->rd_wsscreenlist.screens = 817 (const struct wsscreen_descr **)&dp->rd_wsscreens; 818 819 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 820 &radeonfb_accessops); 821 822 dp->rd_vd.init_screen = radeonfb_init_screen; 823 824 dp->rd_console = 0; 825 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 826 "is_console", &dp->rd_console); 827 828 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 829 830 831 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 832 dp->rd_console, &defattr); 833 834 ri = &dp->rd_vscreen.scr_ri; 835 836 /* clear the screen */ 837 rasops_unpack_attr(defattr, &fg, &bg, &ul); 838 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 839 ri->ri_devcmap[bg & 0xf]); 840 841 dp->rd_wsscreens->textops = &ri->ri_ops; 842 dp->rd_wsscreens->capabilities = ri->ri_caps; 843 dp->rd_wsscreens->nrows = ri->ri_rows; 844 dp->rd_wsscreens->ncols = ri->ri_cols; 845 846 #ifdef SPLASHSCREEN 847 dp->rd_splash.si_depth = ri->ri_depth; 848 dp->rd_splash.si_bits = ri->ri_bits; 849 dp->rd_splash.si_hwbits = ri->ri_hwbits; 850 dp->rd_splash.si_width = ri->ri_width; 851 dp->rd_splash.si_height = ri->ri_height; 852 dp->rd_splash.si_stride = ri->ri_stride; 853 dp->rd_splash.si_fillrect = NULL; 854 #endif 855 if (dp->rd_console) { 856 857 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 858 defattr); 859 #ifdef SPLASHSCREEN 860 splash_render(&dp->rd_splash, 861 SPLASH_F_CENTER|SPLASH_F_FILL); 862 #endif 863 864 #ifdef SPLASHSCREEN_PROGRESS 865 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 866 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 867 dp->rd_progress.sp_left = (dp->rd_virtx - 868 dp->rd_progress.sp_width) / 2; 869 dp->rd_progress.sp_height = 20; 870 dp->rd_progress.sp_state = -1; 871 dp->rd_progress.sp_si = &dp->rd_splash; 872 splash_progress_init(&dp->rd_progress); 873 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 874 #endif 875 876 } else { 877 878 /* 879 * since we're not the console we can postpone 880 * the rest until someone actually allocates a 881 * screen for us. but we do clear the screen 882 * at least. 883 */ 884 memset(ri->ri_bits, 0, 1024); 885 886 radeonfb_modeswitch(dp); 887 #ifdef SPLASHSCREEN 888 splash_render(&dp->rd_splash, 889 SPLASH_F_CENTER|SPLASH_F_FILL); 890 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 891 #endif 892 } 893 894 aa.console = dp->rd_console; 895 aa.scrdata = &dp->rd_wsscreenlist; 896 aa.accessops = &radeonfb_accessops; 897 aa.accesscookie = &dp->rd_vd; 898 899 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 900 radeonfb_blank(dp, 0); 901 902 /* Initialise delayed lvds operations for backlight. */ 903 callout_init(&dp->rd_bl_lvds_co, 0); 904 callout_setfunc(&dp->rd_bl_lvds_co, 905 radeonfb_lvds_callout, dp); 906 } 907 908 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 909 radeonfb_brightness_up, TRUE); 910 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 911 radeonfb_brightness_down, TRUE); 912 913 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 914 915 return; 916 917 error: 918 if (sc->sc_biossz) 919 free(sc->sc_bios, M_DEVBUF); 920 921 if (sc->sc_regsz) 922 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 923 924 if (sc->sc_memsz) 925 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 926 } 927 928 static int 929 radeonfb_drm_print(void *aux, const char *pnp) 930 { 931 if (pnp) 932 aprint_normal("drm at %s", pnp); 933 return (UNCONF); 934 } 935 936 int 937 radeonfb_ioctl(void *v, void *vs, 938 unsigned long cmd, void *d, int flag, struct lwp *l) 939 { 940 struct vcons_data *vd; 941 struct radeonfb_display *dp; 942 struct radeonfb_softc *sc; 943 struct wsdisplay_param *param; 944 945 vd = (struct vcons_data *)v; 946 dp = (struct radeonfb_display *)vd->cookie; 947 sc = dp->rd_softc; 948 949 switch (cmd) { 950 case WSDISPLAYIO_GTYPE: 951 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 952 return 0; 953 954 case WSDISPLAYIO_GINFO: 955 if (vd->active != NULL) { 956 struct wsdisplay_fbinfo *fb; 957 fb = (struct wsdisplay_fbinfo *)d; 958 fb->width = dp->rd_virtx; 959 fb->height = dp->rd_virty; 960 fb->depth = dp->rd_bpp; 961 fb->cmsize = 256; 962 return 0; 963 } else 964 return ENODEV; 965 case WSDISPLAYIO_GVIDEO: 966 if (radeonfb_isblank(dp)) 967 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 968 else 969 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 970 return 0; 971 972 case WSDISPLAYIO_SVIDEO: 973 radeonfb_blank(dp, 974 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 975 return 0; 976 977 case WSDISPLAYIO_GETCMAP: 978 #if 0 979 if (dp->rd_bpp == 8) 980 return radeonfb_getcmap(sc, 981 (struct wsdisplay_cmap *)d); 982 #endif 983 return EINVAL; 984 985 case WSDISPLAYIO_PUTCMAP: 986 #if 0 987 if (dp->rd_bpp == 8) 988 return radeonfb_putcmap(sc, 989 (struct wsdisplay_cmap *)d); 990 #endif 991 return EINVAL; 992 993 case WSDISPLAYIO_LINEBYTES: 994 *(unsigned *)d = dp->rd_stride; 995 return 0; 996 997 case WSDISPLAYIO_SMODE: 998 if (*(int *)d != dp->rd_wsmode) { 999 dp->rd_wsmode = *(int *)d; 1000 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1001 (dp->rd_vd.active)) { 1002 radeonfb_engine_init(dp); 1003 //radeonfb_modeswitch(dp); 1004 vcons_redraw_screen(dp->rd_vd.active); 1005 } 1006 } 1007 return 0; 1008 1009 case WSDISPLAYIO_GCURMAX: 1010 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1011 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1012 return 0; 1013 1014 case WSDISPLAYIO_SCURSOR: 1015 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1016 1017 case WSDISPLAYIO_GCURSOR: 1018 return EPASSTHROUGH; 1019 1020 case WSDISPLAYIO_GCURPOS: 1021 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1022 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1023 return 0; 1024 1025 case WSDISPLAYIO_SCURPOS: 1026 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1027 1028 case WSDISPLAYIO_SSPLASH: 1029 #if defined(SPLASHSCREEN) 1030 if (*(int *)d == 1) { 1031 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1032 splash_render(&dp->rd_splash, 1033 SPLASH_F_CENTER|SPLASH_F_FILL); 1034 } else 1035 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1036 return 0; 1037 #else 1038 return ENODEV; 1039 #endif 1040 case WSDISPLAYIO_SPROGRESS: 1041 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1042 dp->rd_progress.sp_force = 1; 1043 splash_progress_update(&dp->rd_progress); 1044 dp->rd_progress.sp_force = 0; 1045 return 0; 1046 #else 1047 return ENODEV; 1048 #endif 1049 case WSDISPLAYIO_GETPARAM: 1050 param = (struct wsdisplay_param *)d; 1051 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1052 param->min = 0; 1053 param->max = RADEONFB_BACKLIGHT_MAX; 1054 param->curval = radeonfb_get_backlight(dp); 1055 return 0; 1056 } 1057 return EPASSTHROUGH; 1058 1059 case WSDISPLAYIO_SETPARAM: 1060 param = (struct wsdisplay_param *)d; 1061 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1062 return radeonfb_set_backlight(dp, param->curval); 1063 } 1064 return EPASSTHROUGH; 1065 1066 /* PCI config read/write passthrough. */ 1067 case PCI_IOC_CFGREAD: 1068 case PCI_IOC_CFGWRITE: 1069 return (pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l)); 1070 1071 default: 1072 return EPASSTHROUGH; 1073 } 1074 } 1075 1076 paddr_t 1077 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1078 { 1079 struct vcons_data *vd; 1080 struct radeonfb_display *dp; 1081 struct radeonfb_softc *sc; 1082 paddr_t pa; 1083 1084 vd = (struct vcons_data *)v; 1085 dp = (struct radeonfb_display *)vd->cookie; 1086 sc = dp->rd_softc; 1087 1088 /* XXX: note that we don't allow mapping of registers right now */ 1089 /* XXX: this means that the XFree86 radeon driver won't work */ 1090 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1091 pa = bus_space_mmap(sc->sc_memt, 1092 sc->sc_memaddr + dp->rd_offset + offset, 0, 1093 prot, BUS_SPACE_MAP_LINEAR); 1094 return pa; 1095 } 1096 1097 #ifdef RADEONFB_MMAP_BARS 1098 /* 1099 * restrict all other mappings to processes with superuser privileges 1100 * or the kernel itself 1101 */ 1102 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1103 NULL) != 0) { 1104 aprint_error_dev(&sc->sc_dev, "mmap() rejected.\n"); 1105 return -1; 1106 } 1107 1108 if ((offset >= sc->sc_regaddr) && 1109 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1110 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1111 BUS_SPACE_MAP_LINEAR); 1112 } 1113 1114 if ((offset >= sc->sc_memaddr) && 1115 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1116 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1117 BUS_SPACE_MAP_LINEAR); 1118 } 1119 1120 if ((offset >= sc->sc_romaddr) && 1121 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1122 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1123 BUS_SPACE_MAP_LINEAR); 1124 } 1125 1126 #ifdef PCI_MAGIC_IO_RANGE 1127 /* allow mapping of IO space */ 1128 if ((offset >= PCI_MAGIC_IO_RANGE) && 1129 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1130 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1131 0, prot, 0); 1132 return pa; 1133 } 1134 #endif /* macppc */ 1135 1136 #endif /* RADEONFB_MMAP_BARS */ 1137 1138 return -1; 1139 } 1140 1141 static void 1142 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1143 { 1144 bus_space_tag_t romt; 1145 bus_space_handle_t romh, biosh; 1146 bus_size_t romsz; 1147 bus_addr_t ptr; 1148 1149 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1150 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1151 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1152 return; 1153 } 1154 1155 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1156 &sc->sc_biossz); 1157 if (sc->sc_biossz == 0) { 1158 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1159 return; 1160 } 1161 1162 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1163 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1164 1165 /* unmap the PCI expansion rom */ 1166 bus_space_unmap(romt, romh, romsz); 1167 1168 /* turn off rom decoder now */ 1169 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1170 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1171 ~PCI_MAPREG_ROM_ENABLE); 1172 1173 ptr = GETBIOS16(sc, 0x48); 1174 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1175 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1176 sc->sc_flags |= RFB_ATOM; 1177 } 1178 1179 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1180 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1181 } 1182 1183 1184 uint32_t 1185 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1186 { 1187 1188 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1189 } 1190 1191 void 1192 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1193 { 1194 1195 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1196 } 1197 1198 void 1199 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1200 uint32_t andmask, uint32_t ormask) 1201 { 1202 int s; 1203 uint32_t val; 1204 1205 s = splhigh(); 1206 val = radeonfb_get32(sc, reg); 1207 val = (val & andmask) | ormask; 1208 radeonfb_put32(sc, reg, val); 1209 splx(s); 1210 } 1211 1212 uint32_t 1213 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1214 { 1215 int s; 1216 uint32_t val; 1217 1218 s = splhigh(); 1219 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1220 val = radeonfb_get32(sc, RADEON_MM_DATA); 1221 splx(s); 1222 1223 return (val); 1224 } 1225 1226 void 1227 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1228 { 1229 int s; 1230 1231 s = splhigh(); 1232 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1233 radeonfb_put32(sc, RADEON_MM_DATA, val); 1234 splx(s); 1235 } 1236 1237 void 1238 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1239 uint32_t andmask, uint32_t ormask) 1240 { 1241 int s; 1242 uint32_t val; 1243 1244 s = splhigh(); 1245 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1246 val = radeonfb_get32(sc, RADEON_MM_DATA); 1247 val = (val & andmask) | ormask; 1248 radeonfb_put32(sc, RADEON_MM_DATA, val); 1249 splx(s); 1250 } 1251 1252 uint32_t 1253 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1254 { 1255 int s; 1256 uint32_t val; 1257 1258 s = splhigh(); 1259 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1260 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1261 if (HAS_R300CG(sc)) 1262 radeonfb_r300cg_workaround(sc); 1263 splx(s); 1264 1265 return (val); 1266 } 1267 1268 void 1269 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1270 { 1271 int s; 1272 1273 s = splhigh(); 1274 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1275 RADEON_PLL_WR_EN); 1276 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1277 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1278 splx(s); 1279 } 1280 1281 void 1282 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1283 uint32_t andmask, uint32_t ormask) 1284 { 1285 int s; 1286 uint32_t val; 1287 1288 s = splhigh(); 1289 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1290 RADEON_PLL_WR_EN); 1291 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1292 val = (val & andmask) | ormask; 1293 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1294 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1295 splx(s); 1296 } 1297 1298 int 1299 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1300 { 1301 uint32_t saved; 1302 1303 saved = GET32(sc, reg); 1304 PUT32(sc, reg, v); 1305 if (GET32(sc, reg) != v) { 1306 return -1; 1307 } 1308 PUT32(sc, reg, saved); 1309 return 0; 1310 } 1311 1312 uintmax_t 1313 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1314 uintmax_t defval) 1315 { 1316 prop_number_t pn; 1317 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1318 if (pn == NULL) { 1319 return defval; 1320 } 1321 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1322 return (prop_number_integer_value(pn)); 1323 } 1324 1325 int 1326 radeonfb_getclocks(struct radeonfb_softc *sc) 1327 { 1328 bus_addr_t ptr; 1329 int refclk = 0; 1330 int refdiv = 0; 1331 int minpll = 0; 1332 int maxpll = 0; 1333 1334 /* load initial property values if port/board provides them */ 1335 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1336 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1337 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1338 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1339 1340 if (refclk && refdiv && minpll && maxpll) 1341 goto dontprobe; 1342 1343 if (!sc->sc_biossz) { 1344 /* no BIOS */ 1345 aprint_verbose("%s: No video BIOS, using default clocks\n", 1346 XNAME(sc)); 1347 if (IS_IGP(sc)) 1348 refclk = refclk ? refclk : 1432; 1349 else 1350 refclk = refclk ? refclk : 2700; 1351 refdiv = refdiv ? refdiv : 12; 1352 minpll = minpll ? minpll : 12500; 1353 maxpll = maxpll ? maxpll : 35000; 1354 } else if (IS_ATOM(sc)) { 1355 /* ATOM BIOS */ 1356 ptr = GETBIOS16(sc, 0x48); 1357 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1358 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1359 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1360 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1361 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1362 /* 1363 * ATOM BIOS doesn't supply a reference divider, so we 1364 * have to probe for it. 1365 */ 1366 if (refdiv < 2) 1367 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1368 RADEON_PPLL_REF_DIV_MASK; 1369 /* 1370 * if probe is zero, just assume one that should work 1371 * for most parts 1372 */ 1373 if (refdiv < 2) 1374 refdiv = 12; 1375 1376 } else { 1377 /* Legacy BIOS */ 1378 ptr = GETBIOS16(sc, 0x48); 1379 ptr = GETBIOS16(sc, ptr + 0x30); 1380 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1381 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1382 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1383 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1384 } 1385 1386 1387 dontprobe: 1388 sc->sc_refclk = refclk * 10; 1389 sc->sc_refdiv = refdiv; 1390 sc->sc_minpll = minpll * 10; 1391 sc->sc_maxpll = maxpll * 10; 1392 return 0; 1393 } 1394 1395 int 1396 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1397 uint32_t *postdivbit, uint32_t *feedbackdiv) 1398 { 1399 int i; 1400 uint32_t outfreq; 1401 int div; 1402 1403 DPRINTF(("dot clock: %u\n", dotclock)); 1404 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1405 outfreq = div * dotclock; 1406 if ((outfreq >= sc->sc_minpll) && 1407 (outfreq <= sc->sc_maxpll)) { 1408 DPRINTF(("outfreq: %u\n", outfreq)); 1409 *postdivbit = 1410 ((uint32_t)radeonfb_dividers[i].mask << 16); 1411 DPRINTF(("post divider: %d (mask %x)\n", div, 1412 *postdivbit)); 1413 break; 1414 } 1415 } 1416 1417 if (div == 0) 1418 return 1; 1419 1420 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1421 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1422 return 0; 1423 } 1424 1425 #if 0 1426 #ifdef RADEON_DEBUG 1427 static void 1428 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1429 { 1430 char asc[17]; 1431 unsigned ptr = (unsigned)buffer; 1432 char *start = (char *)(ptr & ~0xf); 1433 char *end = (char *)(ptr + size); 1434 1435 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1436 1437 if (pfx == NULL) { 1438 pfx = ""; 1439 } 1440 1441 while (start < end) { 1442 unsigned offset = (unsigned)start & 0xf; 1443 if (offset == 0) { 1444 printf("%s%x: ", pfx, (unsigned)start); 1445 } 1446 if (((unsigned)start < ptr) || 1447 ((unsigned)start >= (ptr + size))) { 1448 printf(" "); 1449 asc[offset] = ' '; 1450 } else { 1451 printf("%02x", *(unsigned char *)start); 1452 if ((*start >= ' ') && (*start <= '~')) { 1453 asc[offset] = *start; 1454 } else { 1455 asc[offset] = '.'; 1456 } 1457 } 1458 asc[offset + 1] = 0; 1459 if (offset % 2) { 1460 printf(" "); 1461 } 1462 if (offset == 15) { 1463 printf(" %s\n", asc); 1464 } 1465 start++; 1466 } 1467 } 1468 #endif 1469 #endif 1470 1471 int 1472 radeonfb_getconnectors(struct radeonfb_softc *sc) 1473 { 1474 int i; 1475 int found = 0; 1476 1477 for (i = 0; i < 2; i++) { 1478 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1479 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1480 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1481 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1482 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1483 } 1484 1485 /* 1486 * This logic is borrowed from Xorg's radeon driver. 1487 */ 1488 if (!sc->sc_biossz) 1489 goto nobios; 1490 1491 if (IS_ATOM(sc)) { 1492 /* not done yet */ 1493 } else { 1494 uint16_t ptr; 1495 int port = 0; 1496 1497 ptr = GETBIOS16(sc, 0x48); 1498 ptr = GETBIOS16(sc, ptr + 0x50); 1499 for (i = 1; i < 4; i++) { 1500 uint16_t entry; 1501 uint8_t conn, ddc, dac, tmds; 1502 1503 /* 1504 * Parse the connector table. From reading the code, 1505 * it appears to made up of 16-bit entries for each 1506 * connector. The 16-bits are defined as: 1507 * 1508 * bits 12-15 - connector type (0 == end of table) 1509 * bits 8-11 - DDC type 1510 * bits 5-7 - ??? 1511 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1512 * bits 1-3 - ??? 1513 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1514 */ 1515 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1516 break; 1517 entry = GETBIOS16(sc, ptr + i * 2); 1518 1519 conn = (entry >> 12) & 0xf; 1520 ddc = (entry >> 8) & 0xf; 1521 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1522 RADEON_DAC_PRIMARY; 1523 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1524 RADEON_TMDS_INT; 1525 1526 if (conn == RADEON_CONN_NONE) 1527 continue; /* no connector */ 1528 1529 if ((found > 0) && 1530 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1531 /* duplicate entry for same connector */ 1532 continue; 1533 } 1534 1535 /* internal DDC_DVI port gets priority */ 1536 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1537 port = 0; 1538 else 1539 port = 1; 1540 1541 sc->sc_ports[port].rp_ddc_type = 1542 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1543 sc->sc_ports[port].rp_dac_type = dac; 1544 sc->sc_ports[port].rp_conn_type = 1545 min(conn, RADEON_CONN_UNSUPPORTED) ; 1546 1547 sc->sc_ports[port].rp_tmds_type = tmds; 1548 1549 if ((conn != RADEON_CONN_DVI_I) && 1550 (conn != RADEON_CONN_DVI_D) && 1551 (tmds == RADEON_TMDS_INT)) 1552 sc->sc_ports[port].rp_tmds_type = 1553 RADEON_TMDS_UNKNOWN; 1554 1555 found += (port + 1); 1556 } 1557 } 1558 1559 nobios: 1560 if (!found) { 1561 DPRINTF(("No connector info in BIOS!\n")); 1562 /* default, port 0 = internal TMDS, port 1 = CRT */ 1563 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1564 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1565 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1566 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1567 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1568 1569 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1570 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1571 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1572 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1573 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1574 } 1575 1576 /* 1577 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1578 * these chips should use TVDAC for the VGA port. 1579 */ 1580 if (HAS_SDAC(sc)) { 1581 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1582 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1583 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1584 } else { 1585 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1586 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1587 } 1588 } else if (!HAS_CRTC2(sc)) { 1589 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1590 } 1591 1592 for (i = 0; i < 2; i++) { 1593 char edid[128]; 1594 uint8_t ddc; 1595 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1596 prop_data_t edid_data; 1597 1598 DPRINTF(("Port #%d:\n", i)); 1599 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1600 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1601 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1602 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1603 1604 sc->sc_ports[i].rp_edid_valid = 0; 1605 /* first look for static EDID data */ 1606 if ((edid_data = prop_dictionary_get(device_properties( 1607 &sc->sc_dev), "EDID")) != NULL) { 1608 1609 aprint_normal_dev(&sc->sc_dev, "using static EDID\n"); 1610 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1611 if (edid_parse(edid, eip) == 0) { 1612 1613 sc->sc_ports[i].rp_edid_valid = 1; 1614 } 1615 } 1616 /* if we didn't find any we'll try to talk to the monitor */ 1617 if (sc->sc_ports[i].rp_edid_valid != 1) { 1618 1619 ddc = sc->sc_ports[i].rp_ddc_type; 1620 if (ddc != RADEON_DDC_NONE) { 1621 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1622 == 0) && (edid_parse(edid, eip) == 0)) { 1623 1624 sc->sc_ports[i].rp_edid_valid = 1; 1625 edid_print(eip); 1626 } 1627 } 1628 } 1629 } 1630 1631 return found; 1632 } 1633 1634 int 1635 radeonfb_gettmds(struct radeonfb_softc *sc) 1636 { 1637 int i; 1638 1639 if (!sc->sc_biossz) { 1640 goto nobios; 1641 } 1642 1643 if (IS_ATOM(sc)) { 1644 /* XXX: not done yet */ 1645 } else { 1646 uint16_t ptr; 1647 int n; 1648 1649 ptr = GETBIOS16(sc, 0x48); 1650 ptr = GETBIOS16(sc, ptr + 0x34); 1651 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1652 if (GETBIOS8(sc, ptr) == 3) { 1653 /* revision three table */ 1654 n = GETBIOS8(sc, ptr + 5) + 1; 1655 n = min(n, 4); 1656 1657 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1658 for (i = 0; i < n; i++) { 1659 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1660 ptr + i * 10 + 8); 1661 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1662 ptr + i * 10 + 0x10); 1663 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1664 sc->sc_tmds_pll[i].rtp_freq, 1665 sc->sc_tmds_pll[i].rtp_pll)); 1666 } 1667 return 0; 1668 } 1669 } 1670 1671 nobios: 1672 DPRINTF(("no suitable DFP table present\n")); 1673 for (i = 0; 1674 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1675 i++) { 1676 int j; 1677 1678 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1679 continue; 1680 1681 for (j = 0; j < 4; j++) { 1682 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1683 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1684 sc->sc_tmds_pll[j].rtp_freq, 1685 sc->sc_tmds_pll[j].rtp_pll)); 1686 } 1687 return 0; 1688 } 1689 1690 return -1; 1691 } 1692 1693 const struct videomode * 1694 radeonfb_modelookup(const char *name) 1695 { 1696 int i; 1697 1698 for (i = 0; i < videomode_count; i++) 1699 if (!strcmp(name, videomode_list[i].name)) 1700 return &videomode_list[i]; 1701 1702 return NULL; 1703 } 1704 1705 void 1706 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1707 { 1708 if (crtc) { 1709 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1710 RADEON_P2PLL_ATOMIC_UPDATE_R); 1711 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1712 } else { 1713 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1714 RADEON_PPLL_ATOMIC_UPDATE_R); 1715 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1716 } 1717 } 1718 1719 void 1720 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1721 { 1722 int i; 1723 1724 for (i = 10000; i; i--) { 1725 if (crtc) { 1726 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1727 RADEON_P2PLL_ATOMIC_UPDATE_R) 1728 break; 1729 } else { 1730 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1731 RADEON_PPLL_ATOMIC_UPDATE_R) 1732 break; 1733 } 1734 } 1735 } 1736 1737 void 1738 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1739 { 1740 uint32_t pbit = 0; 1741 uint32_t feed = 0; 1742 uint32_t data; 1743 #if 1 1744 int i; 1745 #endif 1746 1747 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1748 1749 if (crtc == 0) { 1750 1751 /* XXXX: mobility workaround missing */ 1752 /* XXXX: R300 stuff missing */ 1753 1754 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1755 RADEON_VCLK_SRC_SEL_CPUCLK, 1756 ~RADEON_VCLK_SRC_SEL_MASK); 1757 1758 /* put vclk into reset, use atomic updates */ 1759 SETPLL(sc, RADEON_PPLL_CNTL, 1760 RADEON_PPLL_REFCLK_SEL | 1761 RADEON_PPLL_FBCLK_SEL | 1762 RADEON_PPLL_RESET | 1763 RADEON_PPLL_ATOMIC_UPDATE_EN | 1764 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1765 1766 /* select clock 3 */ 1767 #if 0 1768 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1769 ~RADEON_PLL_DIV_SEL); 1770 #else 1771 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1772 ~RADEON_PLL_DIV_SEL); 1773 #endif 1774 1775 /* XXX: R300 family -- program divider differently? */ 1776 1777 /* program reference divider */ 1778 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1779 ~RADEON_PPLL_REF_DIV_MASK); 1780 PRINTPLL(RADEON_PPLL_REF_DIV); 1781 1782 #if 0 1783 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1784 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1785 RADEON_PPLL_POST3_DIV_MASK); 1786 data |= pbit; 1787 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1788 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1789 #else 1790 for (i = 0; i < 4; i++) { 1791 } 1792 #endif 1793 1794 /* use the atomic update */ 1795 radeonfb_pllwriteupdate(sc, crtc); 1796 1797 /* and wait for it to complete */ 1798 radeonfb_pllwaitatomicread(sc, crtc); 1799 1800 /* program HTOTAL (why?) */ 1801 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1802 1803 /* drop reset */ 1804 CLRPLL(sc, RADEON_PPLL_CNTL, 1805 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1806 RADEON_PPLL_ATOMIC_UPDATE_EN | 1807 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1808 1809 PRINTPLL(RADEON_PPLL_CNTL); 1810 1811 /* give clock time to lock */ 1812 delay(50000); 1813 1814 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1815 RADEON_VCLK_SRC_SEL_PPLLCLK, 1816 ~RADEON_VCLK_SRC_SEL_MASK); 1817 1818 } else { 1819 1820 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1821 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1822 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1823 1824 /* put vclk into reset, use atomic updates */ 1825 SETPLL(sc, RADEON_P2PLL_CNTL, 1826 RADEON_P2PLL_RESET | 1827 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1828 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1829 1830 /* XXX: R300 family -- program divider differently? */ 1831 1832 /* program reference divider */ 1833 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1834 ~RADEON_P2PLL_REF_DIV_MASK); 1835 1836 /* program feedback and post dividers */ 1837 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1838 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1839 RADEON_P2PLL_POST0_DIV_MASK); 1840 data |= pbit; 1841 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1842 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1843 1844 /* use the atomic update */ 1845 radeonfb_pllwriteupdate(sc, crtc); 1846 1847 /* and wait for it to complete */ 1848 radeonfb_pllwaitatomicread(sc, crtc); 1849 1850 /* program HTOTAL (why?) */ 1851 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1852 1853 /* drop reset */ 1854 CLRPLL(sc, RADEON_P2PLL_CNTL, 1855 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1856 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1857 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1858 1859 /* allow time for clock to lock */ 1860 delay(50000); 1861 1862 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1863 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1864 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1865 } 1866 PRINTREG(RADEON_CRTC_MORE_CNTL); 1867 } 1868 1869 void 1870 radeonfb_modeswitch(struct radeonfb_display *dp) 1871 { 1872 struct radeonfb_softc *sc = dp->rd_softc; 1873 int i; 1874 1875 /* blank the display while we switch modes */ 1876 //radeonfb_blank(dp, 1); 1877 1878 #if 0 1879 SET32(sc, RADEON_CRTC_EXT_CNTL, 1880 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1881 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1882 #endif 1883 1884 /* these registers might get in the way... */ 1885 PUT32(sc, RADEON_OVR_CLR, 0); 1886 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1887 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1888 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1889 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1890 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1891 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1892 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1893 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1894 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1895 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1896 1897 for (i = 0; i < dp->rd_ncrtcs; i++) 1898 radeonfb_setcrtc(dp, i); 1899 1900 /* activate the display */ 1901 //radeonfb_blank(dp, 0); 1902 } 1903 1904 void 1905 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1906 { 1907 int crtc; 1908 struct videomode *mode; 1909 struct radeonfb_softc *sc; 1910 struct radeonfb_crtc *cp; 1911 uint32_t v; 1912 uint32_t gencntl; 1913 uint32_t htotaldisp; 1914 uint32_t hsyncstrt; 1915 uint32_t vtotaldisp; 1916 uint32_t vsyncstrt; 1917 uint32_t fphsyncstrt; 1918 uint32_t fpvsyncstrt; 1919 uint32_t fphtotaldisp; 1920 uint32_t fpvtotaldisp; 1921 uint32_t pitch; 1922 1923 sc = dp->rd_softc; 1924 cp = &dp->rd_crtcs[index]; 1925 crtc = cp->rc_number; 1926 mode = &cp->rc_videomode; 1927 1928 #if 1 1929 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1930 (dp->rd_bpp * 8)); 1931 #else 1932 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1933 (sc->sc_maxbpp * 8)); 1934 #endif 1935 //pitch = pitch | (pitch << 16); 1936 1937 switch (crtc) { 1938 case 0: 1939 gencntl = RADEON_CRTC_GEN_CNTL; 1940 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1941 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1942 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1943 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1944 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1945 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1946 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1947 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1948 break; 1949 case 1: 1950 gencntl = RADEON_CRTC2_GEN_CNTL; 1951 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1952 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1953 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1954 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1955 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1956 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1957 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1958 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1959 break; 1960 default: 1961 panic("Bad CRTC!"); 1962 break; 1963 } 1964 1965 /* 1966 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1967 */ 1968 /* only bother with 32bpp and 8bpp */ 1969 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1970 1971 if (crtc == 1) { 1972 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1973 } else { 1974 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1975 } 1976 1977 if (mode->flags & VID_DBLSCAN) 1978 v |= RADEON_CRTC2_DBL_SCAN_EN; 1979 1980 if (mode->flags & VID_INTERLACE) 1981 v |= RADEON_CRTC2_INTERLACE_EN; 1982 1983 if (mode->flags & VID_CSYNC) { 1984 v |= RADEON_CRTC2_CSYNC_EN; 1985 if (crtc == 1) 1986 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1987 } 1988 1989 PUT32(sc, gencntl, v); 1990 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1991 1992 /* 1993 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1994 */ 1995 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1996 if (crtc == 0) { 1997 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1998 RADEON_CRTC_DISPLAY_DIS); 1999 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2000 if (mode->flags & VID_CSYNC) 2001 v |= RADEON_CRTC_VSYNC_TRISTAT; 2002 } 2003 /* unconditional turn on CRT, in case first CRTC is DFP */ 2004 v |= RADEON_CRTC_CRT_ON; 2005 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2006 PRINTREG(RADEON_CRTC_EXT_CNTL); 2007 2008 /* 2009 * H_TOTAL_DISP 2010 */ 2011 v = ((mode->hdisplay / 8) - 1) << 16; 2012 v |= (mode->htotal / 8) - 1; 2013 PUT32(sc, htotaldisp, v); 2014 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2015 PUT32(sc, fphtotaldisp, v); 2016 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2017 2018 /* 2019 * H_SYNC_STRT_WID 2020 */ 2021 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2022 v |= mode->hsync_start; 2023 if (mode->flags & VID_NHSYNC) 2024 v |= RADEON_CRTC_H_SYNC_POL; 2025 PUT32(sc, hsyncstrt, v); 2026 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2027 PUT32(sc, fphsyncstrt, v); 2028 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2029 2030 /* 2031 * V_TOTAL_DISP 2032 */ 2033 v = ((mode->vdisplay - 1) << 16); 2034 v |= (mode->vtotal - 1); 2035 PUT32(sc, vtotaldisp, v); 2036 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2037 PUT32(sc, fpvtotaldisp, v); 2038 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2039 2040 /* 2041 * V_SYNC_STRT_WID 2042 */ 2043 v = ((mode->vsync_end - mode->vsync_start) << 16); 2044 v |= (mode->vsync_start - 1); 2045 if (mode->flags & VID_NVSYNC) 2046 v |= RADEON_CRTC_V_SYNC_POL; 2047 PUT32(sc, vsyncstrt, v); 2048 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2049 PUT32(sc, fpvsyncstrt, v); 2050 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2051 2052 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2053 2054 switch (crtc) { 2055 case 0: 2056 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2057 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2058 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2059 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2060 2061 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2062 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2063 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2064 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2065 PRINTREG(RADEON_CRTC_EXT_CNTL); 2066 PRINTREG(RADEON_CRTC_GEN_CNTL); 2067 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2068 break; 2069 2070 case 1: 2071 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2072 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2073 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2074 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2075 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2076 RADEON_CRTC2_VSYNC_DIS | 2077 RADEON_CRTC2_HSYNC_DIS | 2078 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2079 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2080 break; 2081 } 2082 } 2083 2084 int 2085 radeonfb_isblank(struct radeonfb_display *dp) 2086 { 2087 uint32_t reg, mask; 2088 2089 if (dp->rd_crtcs[0].rc_number) { 2090 reg = RADEON_CRTC2_GEN_CNTL; 2091 mask = RADEON_CRTC2_DISP_DIS; 2092 } else { 2093 reg = RADEON_CRTC_EXT_CNTL; 2094 mask = RADEON_CRTC_DISPLAY_DIS; 2095 } 2096 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2097 } 2098 2099 void 2100 radeonfb_blank(struct radeonfb_display *dp, int blank) 2101 { 2102 struct radeonfb_softc *sc = dp->rd_softc; 2103 uint32_t reg, mask; 2104 uint32_t fpreg, fpval; 2105 int i; 2106 2107 for (i = 0; i < dp->rd_ncrtcs; i++) { 2108 2109 if (dp->rd_crtcs[i].rc_number) { 2110 reg = RADEON_CRTC2_GEN_CNTL; 2111 mask = RADEON_CRTC2_DISP_DIS; 2112 fpreg = RADEON_FP2_GEN_CNTL; 2113 fpval = RADEON_FP2_ON; 2114 } else { 2115 reg = RADEON_CRTC_EXT_CNTL; 2116 mask = RADEON_CRTC_DISPLAY_DIS; 2117 fpreg = RADEON_FP_GEN_CNTL; 2118 fpval = RADEON_FP_FPON; 2119 } 2120 2121 if (blank) { 2122 SET32(sc, reg, mask); 2123 CLR32(sc, fpreg, fpval); 2124 } else { 2125 CLR32(sc, reg, mask); 2126 SET32(sc, fpreg, fpval); 2127 } 2128 } 2129 PRINTREG(RADEON_FP_GEN_CNTL); 2130 PRINTREG(RADEON_FP2_GEN_CNTL); 2131 } 2132 2133 void 2134 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2135 long *defattr) 2136 { 2137 struct radeonfb_display *dp = cookie; 2138 struct rasops_info *ri = &scr->scr_ri; 2139 2140 /* initialize font subsystem */ 2141 wsfont_init(); 2142 2143 DPRINTF(("init screen called, existing %d\n", existing)); 2144 2145 ri->ri_depth = dp->rd_bpp; 2146 ri->ri_width = dp->rd_virtx; 2147 ri->ri_height = dp->rd_virty; 2148 ri->ri_stride = dp->rd_stride; 2149 ri->ri_flg = RI_CENTER; 2150 ri->ri_bits = (void *)dp->rd_fbptr; 2151 2152 /* XXX: 32 bpp only */ 2153 /* this is rgb in "big-endian order..." */ 2154 ri->ri_rnum = 8; 2155 ri->ri_gnum = 8; 2156 ri->ri_bnum = 8; 2157 ri->ri_rpos = 16; 2158 ri->ri_gpos = 8; 2159 ri->ri_bpos = 0; 2160 2161 if (existing) { 2162 ri->ri_flg |= RI_CLEAR; 2163 2164 /* start a modeswitch now */ 2165 radeonfb_modeswitch(dp); 2166 } 2167 2168 /* 2169 * XXX: font selection should be based on properties, with some 2170 * normal/reasonable default. 2171 */ 2172 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2173 2174 /* initialize and look for an initial font */ 2175 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2176 2177 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2178 dp->rd_virtx / ri->ri_font->fontwidth); 2179 2180 /* enable acceleration */ 2181 ri->ri_ops.copyrows = radeonfb_copyrows; 2182 ri->ri_ops.copycols = radeonfb_copycols; 2183 ri->ri_ops.eraserows = radeonfb_eraserows; 2184 ri->ri_ops.erasecols = radeonfb_erasecols; 2185 ri->ri_ops.allocattr = radeonfb_allocattr; 2186 if (!IS_R300(dp->rd_softc)) { 2187 ri->ri_ops.putchar = radeonfb_putchar; 2188 } 2189 ri->ri_ops.cursor = radeonfb_cursor; 2190 } 2191 2192 void 2193 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2194 { 2195 uint32_t gen, ext, gen2 = 0; 2196 uint32_t agploc, aperbase, apersize, mcfbloc; 2197 2198 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2199 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2200 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2201 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2202 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2203 2204 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2205 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2206 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2207 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2208 2209 if (HAS_CRTC2(sc)) { 2210 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2211 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2212 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2213 } 2214 2215 delay(100000); 2216 2217 mcfbloc = (aperbase >> 16) | 2218 ((aperbase + (apersize - 1)) & 0xffff0000); 2219 2220 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2221 sc->sc_memsz = apersize; 2222 2223 if (((agploc & 0xffff) << 16) != 2224 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2225 agploc = mcfbloc & 0xffff0000U; 2226 agploc |= ((agploc + 0x10000) >> 16); 2227 } 2228 2229 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2230 2231 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2232 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2233 2234 DPRINTF(("aperbase = %u\n", aperbase)); 2235 PRINTREG(RADEON_MC_FB_LOCATION); 2236 PRINTREG(RADEON_MC_AGP_LOCATION); 2237 2238 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2239 2240 if (HAS_CRTC2(sc)) 2241 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2242 2243 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2244 2245 #if 0 2246 /* XXX: what is this AGP garbage? :-) */ 2247 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2248 #endif 2249 2250 delay(100000); 2251 2252 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2253 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2254 2255 if (HAS_CRTC2(sc)) 2256 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2257 } 2258 2259 void 2260 radeonfb_init_misc(struct radeonfb_softc *sc) 2261 { 2262 PUT32(sc, RADEON_BUS_CNTL, 2263 RADEON_BUS_MASTER_DIS | 2264 RADEON_BUS_PREFETCH_MODE_ACT | 2265 RADEON_BUS_PCI_READ_RETRY_EN | 2266 RADEON_BUS_PCI_WRT_RETRY_EN | 2267 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2268 RADEON_BUS_MSTR_RD_MULT | 2269 RADEON_BUS_MSTR_RD_LINE | 2270 RADEON_BUS_RD_DISCARD_EN | 2271 RADEON_BUS_MSTR_DISCONNECT_EN | 2272 RADEON_BUS_READ_BURST); 2273 2274 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2275 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2276 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2277 PUT32(sc, RADEON_RBBM_CNTL, 2278 (3 << RADEON_RB_SETTLE_SHIFT) | 2279 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2280 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2281 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2282 2283 /* XXX: figure out what these mean! */ 2284 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2285 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2286 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2287 2288 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2289 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2290 } 2291 2292 /* 2293 * This loads a linear color map for true color. 2294 */ 2295 void 2296 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2297 { 2298 int i; 2299 uint32_t vclk; 2300 2301 #define DAC_WIDTH ((1 << 10) - 1) 2302 #define CLUT_WIDTH ((1 << 8) - 1) 2303 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2304 2305 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2306 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2307 2308 if (crtc) 2309 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2310 else 2311 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2312 2313 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2314 for (i = 0; i <= CLUT_WIDTH; ++i) { 2315 PUT32(sc, RADEON_PALETTE_30_DATA, 2316 (CLUT_COLOR(i) << 10) | 2317 (CLUT_COLOR(i) << 20) | 2318 (CLUT_COLOR(i))); 2319 } 2320 2321 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2322 PRINTREG(RADEON_DAC_CNTL2); 2323 2324 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2325 } 2326 2327 /* 2328 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2329 */ 2330 void 2331 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2332 { 2333 uint32_t tmp, save; 2334 2335 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2336 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2337 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2338 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2339 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2340 } 2341 2342 /* 2343 * Acceleration entry points. 2344 */ 2345 static void 2346 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2347 { 2348 struct rasops_info *ri = cookie; 2349 struct vcons_screen *scr = ri->ri_hw; 2350 struct radeonfb_display *dp = scr->scr_cookie; 2351 struct wsdisplay_font *font = PICK_FONT(ri, c); 2352 uint32_t x, y, w, h; 2353 uint32_t bg, fg, flg; 2354 uint8_t *data; 2355 2356 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2357 return; 2358 2359 if (!CHAR_IN_FONT(c, font)) 2360 return; 2361 2362 w = font->fontwidth; 2363 h = font->fontheight; 2364 2365 flg = attr & 0xff; 2366 if (flg & WSATTR_REVERSE) { 2367 fg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2368 bg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2369 } else { 2370 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2371 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2372 } 2373 2374 x = ri->ri_xorigin + col * w; 2375 y = ri->ri_yorigin + row * h; 2376 2377 if (c == 0x20) { 2378 radeonfb_rectfill(dp, x, y, w, h, bg); 2379 } else { 2380 data = (uint8_t *)font->data + 2381 (c - font->firstchar) * ri->ri_fontscale; 2382 2383 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2384 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2385 } 2386 } 2387 2388 static void 2389 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2390 { 2391 struct rasops_info *ri = cookie; 2392 struct vcons_screen *scr = ri->ri_hw; 2393 struct radeonfb_display *dp = scr->scr_cookie; 2394 uint32_t x, y, w, h, fg, bg, ul; 2395 2396 /* XXX: check for full emulation mode? */ 2397 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2398 x = ri->ri_xorigin; 2399 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2400 w = ri->ri_emuwidth; 2401 h = ri->ri_font->fontheight * nrows; 2402 2403 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2404 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2405 } 2406 } 2407 2408 static void 2409 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2410 { 2411 struct rasops_info *ri = cookie; 2412 struct vcons_screen *scr = ri->ri_hw; 2413 struct radeonfb_display *dp = scr->scr_cookie; 2414 uint32_t x, ys, yd, w, h; 2415 2416 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2417 x = ri->ri_xorigin; 2418 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2419 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2420 w = ri->ri_emuwidth; 2421 h = ri->ri_font->fontheight * nrows; 2422 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2423 RADEON_ROP3_S, 0xffffffff); 2424 } 2425 } 2426 2427 static void 2428 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2429 { 2430 struct rasops_info *ri = cookie; 2431 struct vcons_screen *scr = ri->ri_hw; 2432 struct radeonfb_display *dp = scr->scr_cookie; 2433 uint32_t xs, xd, y, w, h; 2434 2435 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2436 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2437 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2438 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2439 w = ri->ri_font->fontwidth * ncols; 2440 h = ri->ri_font->fontheight; 2441 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2442 RADEON_ROP3_S, 0xffffffff); 2443 } 2444 } 2445 2446 static void 2447 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2448 long fillattr) 2449 { 2450 struct rasops_info *ri = cookie; 2451 struct vcons_screen *scr = ri->ri_hw; 2452 struct radeonfb_display *dp = scr->scr_cookie; 2453 uint32_t x, y, w, h, fg, bg, ul; 2454 2455 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2456 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2457 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2458 w = ri->ri_font->fontwidth * ncols; 2459 h = ri->ri_font->fontheight; 2460 2461 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2462 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2463 } 2464 } 2465 2466 static void 2467 radeonfb_cursor(void *cookie, int on, int row, int col) 2468 { 2469 struct rasops_info *ri = cookie; 2470 struct vcons_screen *scr = ri->ri_hw; 2471 struct radeonfb_display *dp = scr->scr_cookie; 2472 int x, y, wi, he; 2473 2474 wi = ri->ri_font->fontwidth; 2475 he = ri->ri_font->fontheight; 2476 2477 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2478 x = ri->ri_ccol * wi + ri->ri_xorigin; 2479 y = ri->ri_crow * he + ri->ri_yorigin; 2480 /* first turn off the old cursor */ 2481 if (ri->ri_flg & RI_CURSOR) { 2482 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2483 RADEON_ROP3_Dn, 0xffffffff); 2484 ri->ri_flg &= ~RI_CURSOR; 2485 } 2486 ri->ri_crow = row; 2487 ri->ri_ccol = col; 2488 /* then (possibly) turn on the new one */ 2489 if (on) { 2490 x = ri->ri_ccol * wi + ri->ri_xorigin; 2491 y = ri->ri_crow * he + ri->ri_yorigin; 2492 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2493 RADEON_ROP3_Dn, 0xffffffff); 2494 ri->ri_flg |= RI_CURSOR; 2495 } 2496 } else { 2497 scr->scr_ri.ri_crow = row; 2498 scr->scr_ri.ri_ccol = col; 2499 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2500 } 2501 } 2502 2503 static int 2504 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2505 { 2506 if ((fg == 0) && (bg == 0)) { 2507 fg = WS_DEFAULT_FG; 2508 bg = WS_DEFAULT_BG; 2509 } 2510 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2511 return 0; 2512 } 2513 2514 /* 2515 * Underlying acceleration support. 2516 */ 2517 static void 2518 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2519 int height, uint32_t fg, uint32_t bg) 2520 { 2521 struct radeonfb_softc *sc = dp->rd_softc; 2522 uint32_t gmc; 2523 uint32_t padded_width = (width+7) & 0xfff8; 2524 uint32_t topleft, bottomright; 2525 2526 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2527 2528 if (width != padded_width) { 2529 2530 radeonfb_wait_fifo(sc, 2); 2531 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2532 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2533 ((xd + width) & 0x1fff); 2534 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2535 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2536 } 2537 2538 radeonfb_wait_fifo(sc, 5); 2539 2540 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2541 RADEON_GMC_BRUSH_NONE | 2542 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2543 //RADEON_GMC_BYTE_LSB_TO_MSB | 2544 RADEON_GMC_DST_CLIPPING | 2545 RADEON_ROP3_S | 2546 RADEON_DP_SRC_SOURCE_HOST_DATA | 2547 RADEON_GMC_CLR_CMP_CNTL_DIS | 2548 RADEON_GMC_WR_MSK_DIS | 2549 gmc); 2550 2551 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2552 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2553 2554 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2555 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2556 2557 } 2558 2559 static void 2560 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2561 { 2562 struct radeonfb_softc *sc = dp->rd_softc; 2563 int i; 2564 uint32_t latch = 0; 2565 int shift = 0; 2566 2567 for (i = 0; i < count; i++) { 2568 latch |= (data[i] << shift); 2569 if (shift == 24) { 2570 radeonfb_wait_fifo(sc, 1); 2571 PUT32(sc, RADEON_HOST_DATA0, latch); 2572 latch = 0; 2573 shift = 0; 2574 } else 2575 shift += 8; 2576 } 2577 if (shift != 0) { 2578 radeonfb_wait_fifo(sc, 1); 2579 PUT32(sc, RADEON_HOST_DATA0, latch); 2580 } 2581 radeonfb_unclip(sc); 2582 } 2583 2584 static void 2585 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2586 int width, int height, uint32_t color) 2587 { 2588 struct radeonfb_softc *sc = dp->rd_softc; 2589 uint32_t gmc; 2590 2591 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2592 2593 radeonfb_wait_fifo(sc, 6); 2594 2595 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2596 RADEON_GMC_BRUSH_SOLID_COLOR | 2597 RADEON_GMC_SRC_DATATYPE_COLOR | 2598 RADEON_GMC_CLR_CMP_CNTL_DIS | 2599 RADEON_ROP3_P | gmc); 2600 2601 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2602 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2603 PUT32(sc, RADEON_DP_CNTL, 2604 RADEON_DST_X_LEFT_TO_RIGHT | 2605 RADEON_DST_Y_TOP_TO_BOTTOM); 2606 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2607 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2608 2609 /* 2610 * XXX: we don't wait for the fifo to empty -- that would slow 2611 * things down! The linux radeonfb driver waits, but xfree doesn't 2612 */ 2613 /* XXX: for now we do, to make it safe for direct drawing */ 2614 radeonfb_engine_idle(sc); 2615 } 2616 2617 static void 2618 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2619 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2620 { 2621 struct radeonfb_softc *sc = dp->rd_softc; 2622 uint32_t gmc; 2623 uint32_t dir; 2624 2625 if (dsty < srcy) { 2626 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2627 } else { 2628 srcy += height - 1; 2629 dsty += height - 1; 2630 dir = 0; 2631 } 2632 if (dstx < srcx) { 2633 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2634 } else { 2635 srcx += width - 1; 2636 dstx += width - 1; 2637 } 2638 2639 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2640 2641 radeonfb_wait_fifo(sc, 6); 2642 2643 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2644 //RADEON_GMC_SRC_CLIPPING | 2645 RADEON_GMC_BRUSH_SOLID_COLOR | 2646 RADEON_GMC_SRC_DATATYPE_COLOR | 2647 RADEON_GMC_CLR_CMP_CNTL_DIS | 2648 RADEON_DP_SRC_SOURCE_MEMORY | 2649 rop | gmc); 2650 2651 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2652 PUT32(sc, RADEON_DP_CNTL, dir); 2653 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2654 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2655 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2656 2657 /* 2658 * XXX: we don't wait for the fifo to empty -- that would slow 2659 * things down! The linux radeonfb driver waits, but xfree doesn't 2660 */ 2661 /* XXX: for now we do, to make it safe for direct drawing */ 2662 radeonfb_engine_idle(sc); 2663 } 2664 2665 static void 2666 radeonfb_engine_idle(struct radeonfb_softc *sc) 2667 { 2668 int i; 2669 2670 radeonfb_wait_fifo(sc, 64); 2671 for (i = RADEON_TIMEOUT; i; i--) { 2672 if ((GET32(sc, RADEON_RBBM_STATUS) & 2673 RADEON_RBBM_ACTIVE) == 0) { 2674 radeonfb_engine_flush(sc); 2675 break; 2676 } 2677 } 2678 } 2679 2680 static void 2681 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2682 { 2683 int i; 2684 2685 for (i = RADEON_TIMEOUT; i; i--) { 2686 if ((GET32(sc, RADEON_RBBM_STATUS) & 2687 RADEON_RBBM_FIFOCNT_MASK) >= n) 2688 return; 2689 } 2690 #ifdef DIAGNOSTIC 2691 if (!i) 2692 printf("%s: timed out waiting for fifo (%x)\n", 2693 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2694 #endif 2695 } 2696 2697 static void 2698 radeonfb_engine_flush(struct radeonfb_softc *sc) 2699 { 2700 int i; 2701 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2702 for (i = RADEON_TIMEOUT; i; i--) { 2703 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2704 RADEON_RB2D_DC_BUSY) == 0) 2705 break; 2706 } 2707 #ifdef DIAGNOSTIC 2708 if (!i) 2709 printf("%s: engine flush timed out!\n", XNAME(sc)); 2710 #endif 2711 } 2712 2713 static inline void 2714 radeonfb_unclip(struct radeonfb_softc *sc) 2715 { 2716 2717 radeonfb_wait_fifo(sc, 2); 2718 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2719 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2720 } 2721 2722 static void 2723 radeonfb_engine_init(struct radeonfb_display *dp) 2724 { 2725 struct radeonfb_softc *sc = dp->rd_softc; 2726 uint32_t pitch; 2727 2728 /* no 3D */ 2729 PUT32(sc, RADEON_RB3D_CNTL, 0); 2730 2731 radeonfb_engine_reset(sc); 2732 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2733 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2734 2735 radeonfb_wait_fifo(sc, 1); 2736 if (!IS_R300(sc)) 2737 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2738 2739 radeonfb_wait_fifo(sc, 3); 2740 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2741 (pitch << 22) | (sc->sc_aperbase >> 10)); 2742 2743 2744 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2745 (pitch << 22) | (sc->sc_aperbase >> 10)); 2746 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2747 (pitch << 22) | (sc->sc_aperbase >> 10)); 2748 2749 radeonfb_wait_fifo(sc, 1); 2750 #if _BYTE_ORDER == _BIG_ENDIAN 2751 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2752 #else 2753 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2754 #endif 2755 2756 /* default scissors -- no clipping */ 2757 radeonfb_wait_fifo(sc, 1); 2758 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2759 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2760 2761 radeonfb_wait_fifo(sc, 1); 2762 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2763 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2764 RADEON_GMC_CLR_CMP_CNTL_DIS | 2765 RADEON_GMC_BRUSH_SOLID_COLOR | 2766 RADEON_GMC_SRC_DATATYPE_COLOR); 2767 2768 radeonfb_wait_fifo(sc, 7); 2769 PUT32(sc, RADEON_DST_LINE_START, 0); 2770 PUT32(sc, RADEON_DST_LINE_END, 0); 2771 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2772 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2773 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2774 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2775 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2776 2777 radeonfb_engine_idle(sc); 2778 } 2779 2780 static void 2781 radeonfb_engine_reset(struct radeonfb_softc *sc) 2782 { 2783 uint32_t hpc, rbbm, mclkcntl, clkindex; 2784 2785 radeonfb_engine_flush(sc); 2786 2787 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2788 if (HAS_R300CG(sc)) 2789 radeonfb_r300cg_workaround(sc); 2790 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2791 2792 /* 2793 * According to comments in XFree code, resetting the HDP via 2794 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2795 * So we use HOST_PATH_CNTL instead. 2796 */ 2797 2798 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2799 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2800 if (IS_R300(sc)) { 2801 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2802 RADEON_SOFT_RESET_CP | 2803 RADEON_SOFT_RESET_HI | 2804 RADEON_SOFT_RESET_E2); 2805 GET32(sc, RADEON_RBBM_SOFT_RESET); 2806 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2807 /* 2808 * XXX: this bit is not defined in any ATI docs I have, 2809 * nor in the XFree code, but XFree does it. Why? 2810 */ 2811 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2812 } else { 2813 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2814 RADEON_SOFT_RESET_CP | 2815 RADEON_SOFT_RESET_SE | 2816 RADEON_SOFT_RESET_RE | 2817 RADEON_SOFT_RESET_PP | 2818 RADEON_SOFT_RESET_E2 | 2819 RADEON_SOFT_RESET_RB); 2820 GET32(sc, RADEON_RBBM_SOFT_RESET); 2821 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2822 ~(RADEON_SOFT_RESET_CP | 2823 RADEON_SOFT_RESET_SE | 2824 RADEON_SOFT_RESET_RE | 2825 RADEON_SOFT_RESET_PP | 2826 RADEON_SOFT_RESET_E2 | 2827 RADEON_SOFT_RESET_RB)); 2828 GET32(sc, RADEON_RBBM_SOFT_RESET); 2829 } 2830 2831 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2832 GET32(sc, RADEON_HOST_PATH_CNTL); 2833 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2834 2835 if (IS_R300(sc)) 2836 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2837 2838 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2839 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2840 2841 if (HAS_R300CG(sc)) 2842 radeonfb_r300cg_workaround(sc); 2843 } 2844 2845 static int 2846 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2847 { 2848 int x, y; 2849 2850 x = pos->x; 2851 y = pos->y; 2852 2853 /* 2854 * This doesn't let a cursor move off the screen. I'm not 2855 * sure if this will have negative effects for e.g. Xinerama. 2856 * I'd guess Xinerama handles it by changing the cursor shape, 2857 * but that needs verification. 2858 */ 2859 if (x >= dp->rd_virtx) 2860 x = dp->rd_virtx - 1; 2861 if (x < 0) 2862 x = 0; 2863 if (y >= dp->rd_virty) 2864 y = dp->rd_virty - 1; 2865 if (y < 0) 2866 y = 0; 2867 2868 dp->rd_cursor.rc_pos.x = x; 2869 dp->rd_cursor.rc_pos.y = y; 2870 2871 radeonfb_cursor_position(dp); 2872 return 0; 2873 } 2874 2875 static int 2876 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2877 { 2878 unsigned flags; 2879 2880 uint8_t r[2], g[2], b[2]; 2881 unsigned index, count; 2882 int i, err; 2883 int pitch, size; 2884 struct radeonfb_cursor nc; 2885 2886 flags = wc->which; 2887 2888 /* copy old values */ 2889 nc = dp->rd_cursor; 2890 2891 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2892 index = wc->cmap.index; 2893 count = wc->cmap.count; 2894 2895 if (index >= 2 || (index + count) > 2) 2896 return EINVAL; 2897 2898 err = copyin(wc->cmap.red, &r[index], count); 2899 if (err) 2900 return err; 2901 err = copyin(wc->cmap.green, &g[index], count); 2902 if (err) 2903 return err; 2904 err = copyin(wc->cmap.blue, &b[index], count); 2905 if (err) 2906 return err; 2907 2908 for (i = index; i < index + count; i++) { 2909 nc.rc_cmap[i] = 2910 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2911 } 2912 } 2913 2914 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2915 if ((wc->size.x > RADEON_CURSORMAXX) || 2916 (wc->size.y > RADEON_CURSORMAXY)) 2917 return EINVAL; 2918 2919 /* figure bytes per line */ 2920 pitch = (wc->size.x + 7) / 8; 2921 size = pitch * wc->size.y; 2922 2923 /* clear the old cursor and mask */ 2924 memset(nc.rc_image, 0, 512); 2925 memset(nc.rc_mask, 0, 512); 2926 2927 nc.rc_size = wc->size; 2928 2929 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2930 return err; 2931 2932 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2933 return err; 2934 } 2935 2936 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2937 nc.rc_hot = wc->hot; 2938 if (nc.rc_hot.x >= nc.rc_size.x) 2939 nc.rc_hot.x = nc.rc_size.x - 1; 2940 if (nc.rc_hot.y >= nc.rc_size.y) 2941 nc.rc_hot.y = nc.rc_size.y - 1; 2942 } 2943 2944 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2945 nc.rc_pos = wc->pos; 2946 if (nc.rc_pos.x >= dp->rd_virtx) 2947 nc.rc_pos.x = dp->rd_virtx - 1; 2948 #if 0 2949 if (nc.rc_pos.x < 0) 2950 nc.rc_pos.x = 0; 2951 #endif 2952 if (nc.rc_pos.y >= dp->rd_virty) 2953 nc.rc_pos.y = dp->rd_virty - 1; 2954 #if 0 2955 if (nc.rc_pos.y < 0) 2956 nc.rc_pos.y = 0; 2957 #endif 2958 } 2959 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2960 nc.rc_visible = wc->enable; 2961 } 2962 2963 dp->rd_cursor = nc; 2964 radeonfb_cursor_update(dp, wc->which); 2965 2966 return 0; 2967 } 2968 2969 /* 2970 * Change the cursor shape. Call this with the cursor locked to avoid 2971 * flickering/tearing. 2972 */ 2973 static void 2974 radeonfb_cursor_shape(struct radeonfb_display *dp) 2975 { 2976 uint8_t and[512], xor[512]; 2977 int i, j, src, dst, pitch; 2978 const uint8_t *msk = dp->rd_cursor.rc_mask; 2979 const uint8_t *img = dp->rd_cursor.rc_image; 2980 2981 /* 2982 * Radeon cursor data interleaves one line of AND data followed 2983 * by a line of XOR data. (Each line corresponds to a whole hardware 2984 * pitch - i.e. 64 pixels or 8 bytes.) 2985 * 2986 * The cursor is displayed using the following table: 2987 * 2988 * AND XOR Result 2989 * ---------------------- 2990 * 0 0 Cursor color 0 2991 * 0 1 Cursor color 1 2992 * 1 0 Transparent 2993 * 1 1 Complement of background 2994 * 2995 * Our masks are therefore different from what we were passed. 2996 * Passed in, I'm assuming the data represents either color 0 or 1, 2997 * and a mask, so the passed in table looks like: 2998 * 2999 * IMG Mask Result 3000 * ----------------------- 3001 * 0 0 Transparent 3002 * 0 1 Cursor color 0 3003 * 1 0 Transparent 3004 * 1 1 Cursor color 1 3005 * 3006 * IF mask bit == 1, AND = 0, XOR = color. 3007 * IF mask bit == 0, AND = 1, XOR = 0. 3008 * 3009 * hence: AND = ~(mask); XOR = color & ~(mask); 3010 */ 3011 3012 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3013 3014 /* start by assuming all bits are transparent */ 3015 memset(and, 0xff, 512); 3016 memset(xor, 0x00, 512); 3017 3018 src = 0; 3019 dst = 0; 3020 for (i = 0; i < 64; i++) { 3021 for (j = 0; j < 64; j += 8) { 3022 if ((i < dp->rd_cursor.rc_size.y) && 3023 (j < dp->rd_cursor.rc_size.x)) { 3024 3025 /* take care to leave odd bits alone */ 3026 and[dst] &= ~(msk[src]); 3027 xor[dst] = img[src] & msk[src]; 3028 src++; 3029 } 3030 dst++; 3031 } 3032 } 3033 3034 /* copy the image into place */ 3035 for (i = 0; i < 64; i++) { 3036 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3037 &and[i * 8], 8); 3038 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3039 &xor[i * 8], 8); 3040 } 3041 } 3042 3043 static void 3044 radeonfb_cursor_position(struct radeonfb_display *dp) 3045 { 3046 struct radeonfb_softc *sc = dp->rd_softc; 3047 uint32_t offset, hvoff, hvpos; /* registers */ 3048 uint32_t coff; /* cursor offset */ 3049 int i, x, y, xoff, yoff, crtcoff; 3050 3051 /* 3052 * XXX: this also needs to handle pan/scan 3053 */ 3054 for (i = 0; i < dp->rd_ncrtcs; i++) { 3055 3056 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3057 3058 if (rcp->rc_number) { 3059 offset = RADEON_CUR2_OFFSET; 3060 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3061 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3062 crtcoff = RADEON_CRTC2_OFFSET; 3063 } else { 3064 offset = RADEON_CUR_OFFSET; 3065 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3066 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3067 crtcoff = RADEON_CRTC_OFFSET; 3068 } 3069 3070 x = dp->rd_cursor.rc_pos.x; 3071 y = dp->rd_cursor.rc_pos.y; 3072 3073 while (y < rcp->rc_yoffset) { 3074 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3075 } 3076 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3077 rcp->rc_yoffset += RADEON_PANINCREMENT; 3078 } 3079 while (x < rcp->rc_xoffset) { 3080 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3081 } 3082 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3083 rcp->rc_xoffset += RADEON_PANINCREMENT; 3084 } 3085 3086 /* adjust for the cursor's hotspot */ 3087 x -= dp->rd_cursor.rc_hot.x; 3088 y -= dp->rd_cursor.rc_hot.y; 3089 xoff = yoff = 0; 3090 3091 if (x >= dp->rd_virtx) 3092 x = dp->rd_virtx - 1; 3093 if (y >= dp->rd_virty) 3094 y = dp->rd_virty - 1; 3095 3096 /* now adjust cursor so it is relative to viewport */ 3097 x -= rcp->rc_xoffset; 3098 y -= rcp->rc_yoffset; 3099 3100 /* 3101 * no need to check for fall off, because we should 3102 * never move off the screen entirely! 3103 */ 3104 coff = 0; 3105 if (x < 0) { 3106 xoff = -x; 3107 x = 0; 3108 } 3109 if (y < 0) { 3110 yoff = -y; 3111 y = 0; 3112 coff = (yoff * 2) * 8; 3113 } 3114 3115 /* pan the display */ 3116 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3117 rcp->rc_xoffset); 3118 3119 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3120 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3121 /* NB: this unlocks the cursor */ 3122 PUT32(sc, hvpos, (x << 16) | y); 3123 } 3124 } 3125 3126 static void 3127 radeonfb_cursor_visible(struct radeonfb_display *dp) 3128 { 3129 int i; 3130 uint32_t gencntl, bit; 3131 3132 for (i = 0; i < dp->rd_ncrtcs; i++) { 3133 if (dp->rd_crtcs[i].rc_number) { 3134 gencntl = RADEON_CRTC2_GEN_CNTL; 3135 bit = RADEON_CRTC2_CUR_EN; 3136 } else { 3137 gencntl = RADEON_CRTC_GEN_CNTL; 3138 bit = RADEON_CRTC_CUR_EN; 3139 } 3140 3141 if (dp->rd_cursor.rc_visible) 3142 SET32(dp->rd_softc, gencntl, bit); 3143 else 3144 CLR32(dp->rd_softc, gencntl, bit); 3145 } 3146 } 3147 3148 static void 3149 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3150 { 3151 int i; 3152 uint32_t c0reg, c1reg; 3153 struct radeonfb_softc *sc = dp->rd_softc; 3154 3155 for (i = 0; i < dp->rd_ncrtcs; i++) { 3156 if (dp->rd_crtcs[i].rc_number) { 3157 c0reg = RADEON_CUR2_CLR0; 3158 c1reg = RADEON_CUR2_CLR1; 3159 } else { 3160 c0reg = RADEON_CUR_CLR0; 3161 c1reg = RADEON_CUR_CLR1; 3162 } 3163 3164 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3165 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3166 } 3167 } 3168 3169 static void 3170 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3171 { 3172 struct radeonfb_softc *sc; 3173 int i; 3174 3175 sc = dp->rd_softc; 3176 for (i = 0; i < dp->rd_ncrtcs; i++) { 3177 if (dp->rd_crtcs[i].rc_number) { 3178 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3179 } else { 3180 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3181 } 3182 } 3183 3184 if (which & WSDISPLAY_CURSOR_DOCMAP) 3185 radeonfb_cursor_cmap(dp); 3186 3187 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3188 radeonfb_cursor_shape(dp); 3189 3190 if (which & WSDISPLAY_CURSOR_DOCUR) 3191 radeonfb_cursor_visible(dp); 3192 3193 /* this one is unconditional, because it updates other stuff */ 3194 radeonfb_cursor_position(dp); 3195 } 3196 3197 static struct videomode * 3198 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3199 { 3200 int r1, r2; 3201 3202 /* otherwise pick the higher refresh rate */ 3203 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3204 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3205 3206 return (r1 < r2 ? m2 : m1); 3207 } 3208 3209 static const struct videomode * 3210 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3211 int x, int y) 3212 { 3213 struct edid_info *ep = &rp->rp_edid; 3214 struct videomode *vmp = NULL; 3215 int i; 3216 3217 if (!rp->rp_edid_valid) { 3218 /* fallback to safe mode */ 3219 return radeonfb_modelookup(sc->sc_defaultmode); 3220 } 3221 3222 /* always choose the preferred mode first! */ 3223 if (ep->edid_preferred_mode) { 3224 3225 /* XXX: add auto-stretching support for native mode */ 3226 3227 /* this may want panning to occur, btw */ 3228 if ((ep->edid_preferred_mode->hdisplay <= x) && 3229 (ep->edid_preferred_mode->vdisplay <= y)) 3230 return ep->edid_preferred_mode; 3231 } 3232 3233 for (i = 0; i < ep->edid_nmodes; i++) { 3234 /* 3235 * We elect to pick a resolution that is too large for 3236 * the monitor than one that is too small. This means 3237 * that we will prefer to pan rather than to try to 3238 * center a smaller display on a larger screen. In 3239 * practice, this shouldn't matter because if a 3240 * monitor can support a larger resolution, it can 3241 * probably also support the smaller. A specific 3242 * exception is fixed format panels, but hopefully 3243 * they are properly dealt with by the "autostretch" 3244 * logic above. 3245 */ 3246 if ((ep->edid_modes[i].hdisplay > x) || 3247 (ep->edid_modes[i].vdisplay > y)) { 3248 continue; 3249 } 3250 3251 /* 3252 * at this point, the display mode is no larger than 3253 * what we've requested. 3254 */ 3255 if (vmp == NULL) 3256 vmp = &ep->edid_modes[i]; 3257 3258 /* eliminate smaller modes */ 3259 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3260 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3261 continue; 3262 3263 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3264 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3265 vmp = &ep->edid_modes[i]; 3266 continue; 3267 } 3268 3269 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3270 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3271 3272 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3273 } 3274 3275 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3276 } 3277 3278 static int 3279 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3280 { 3281 int i; 3282 3283 for (i = 0; i < nlist; i++) { 3284 if ((x == list[i].hdisplay) && 3285 (y == list[i].vdisplay)) { 3286 return 1; 3287 } 3288 } 3289 return 0; 3290 } 3291 3292 static void 3293 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3294 int pan) 3295 { 3296 struct radeonfb_port *rp; 3297 struct edid_info *ep; 3298 int i, j; 3299 3300 *x = 0; 3301 *y = 0; 3302 3303 if (pan) { 3304 for (i = 0; i < dp->rd_ncrtcs; i++) { 3305 rp = dp->rd_crtcs[i].rc_port; 3306 ep = &rp->rp_edid; 3307 if (!rp->rp_edid_valid) { 3308 /* monitor not present */ 3309 continue; 3310 } 3311 3312 /* 3313 * For now we are ignoring "conflict" that 3314 * could occur when mixing some modes like 3315 * 1280x1024 and 1400x800. It isn't clear 3316 * which is better, so the first one wins. 3317 */ 3318 for (j = 0; j < ep->edid_nmodes; j++) { 3319 /* 3320 * ignore resolutions that are too big for 3321 * the radeon 3322 */ 3323 if (ep->edid_modes[j].hdisplay > 3324 dp->rd_softc->sc_maxx) 3325 continue; 3326 if (ep->edid_modes[j].vdisplay > 3327 dp->rd_softc->sc_maxy) 3328 continue; 3329 3330 /* 3331 * pick largest resolution, the 3332 * smaller monitor will pan 3333 */ 3334 if ((ep->edid_modes[j].hdisplay >= *x) && 3335 (ep->edid_modes[j].vdisplay >= *y)) { 3336 *x = ep->edid_modes[j].hdisplay; 3337 *y = ep->edid_modes[j].vdisplay; 3338 } 3339 } 3340 } 3341 3342 } else { 3343 struct videomode modes[64]; 3344 int nmodes = 0; 3345 int valid = 0; 3346 3347 for (i = 0; i < dp->rd_ncrtcs; i++) { 3348 /* 3349 * pick the largest resolution in common. 3350 */ 3351 rp = dp->rd_crtcs[i].rc_port; 3352 ep = &rp->rp_edid; 3353 3354 if (!rp->rp_edid_valid) 3355 continue; 3356 3357 if (!valid) { 3358 /* 3359 * Pick the preferred mode for this port 3360 * if available. 3361 */ 3362 if (ep->edid_preferred_mode) { 3363 struct videomode *vmp = 3364 ep->edid_preferred_mode; 3365 3366 if ((vmp->hdisplay <= 3367 dp->rd_softc->sc_maxx) && 3368 (vmp->vdisplay <= 3369 dp->rd_softc->sc_maxy)) 3370 modes[nmodes++] = *vmp; 3371 } else { 3372 3373 /* initialize starting list */ 3374 for (j = 0; j < ep->edid_nmodes; j++) { 3375 /* 3376 * ignore resolutions that are 3377 * too big for the radeon 3378 */ 3379 if (ep->edid_modes[j].hdisplay > 3380 dp->rd_softc->sc_maxx) 3381 continue; 3382 if (ep->edid_modes[j].vdisplay > 3383 dp->rd_softc->sc_maxy) 3384 continue; 3385 3386 modes[nmodes] = 3387 ep->edid_modes[j]; 3388 nmodes++; 3389 } 3390 } 3391 valid = 1; 3392 } else { 3393 /* merge into preexisting list */ 3394 for (j = 0; j < nmodes; j++) { 3395 if (!radeonfb_hasres(ep->edid_modes, 3396 ep->edid_nmodes, 3397 modes[j].hdisplay, 3398 modes[j].vdisplay)) { 3399 modes[j] = modes[nmodes]; 3400 j--; 3401 nmodes--; 3402 } 3403 } 3404 } 3405 } 3406 3407 /* now we have to pick from the merged list */ 3408 for (i = 0; i < nmodes; i++) { 3409 if ((modes[i].hdisplay >= *x) && 3410 (modes[i].vdisplay >= *y)) { 3411 *x = modes[i].hdisplay; 3412 *y = modes[i].vdisplay; 3413 } 3414 } 3415 } 3416 3417 if ((*x == 0) || (*y == 0)) { 3418 /* fallback to safe mode */ 3419 *x = 640; 3420 *y = 480; 3421 } 3422 } 3423 3424 /* 3425 * backlight levels are linear on: 3426 * - RV200, RV250, RV280, RV350 3427 * - but NOT on PowerBook4,3 6,3 6,5 3428 * according to Linux' radeonfb 3429 */ 3430 3431 /* Get the current backlight level for the display. */ 3432 3433 static int 3434 radeonfb_get_backlight(struct radeonfb_display *dp) 3435 { 3436 int s; 3437 uint32_t level; 3438 3439 s = spltty(); 3440 3441 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3442 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3443 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3444 3445 /* 3446 * On some chips, we should negate the backlight level. 3447 * XXX Find out on which chips. 3448 */ 3449 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3450 level = RADEONFB_BACKLIGHT_MAX - level; 3451 3452 splx(s); 3453 3454 return level; 3455 } 3456 3457 /* Set the backlight to the given level for the display. */ 3458 3459 static int 3460 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3461 { 3462 struct radeonfb_softc *sc; 3463 int rlevel, s; 3464 uint32_t lvds; 3465 3466 s = spltty(); 3467 3468 if (level < 0) 3469 level = 0; 3470 else if (level >= RADEONFB_BACKLIGHT_MAX) 3471 level = RADEONFB_BACKLIGHT_MAX; 3472 3473 sc = dp->rd_softc; 3474 3475 /* On some chips, we should negate the backlight level. */ 3476 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3477 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3478 } else 3479 rlevel = level; 3480 3481 callout_stop(&dp->rd_bl_lvds_co); 3482 radeonfb_engine_idle(sc); 3483 3484 /* 3485 * Turn off the display if the backlight is set to 0, since the 3486 * display is useless without backlight anyway. 3487 */ 3488 if (level == 0) 3489 radeonfb_blank(dp, 1); 3490 else if (radeonfb_get_backlight(dp) == 0) 3491 radeonfb_blank(dp, 0); 3492 3493 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3494 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3495 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3496 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3497 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3498 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3499 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3500 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3501 lvds |= RADEON_LVDS_ON; 3502 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3503 } else { 3504 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3505 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3506 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3507 } 3508 3509 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3510 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3511 /* XXX What is the correct delay? */ 3512 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3513 3514 splx(s); 3515 3516 return 0; 3517 } 3518 3519 /* 3520 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3521 * Set the delayed bits in the register, and clear the stored delayed 3522 * value. 3523 */ 3524 3525 static void radeonfb_lvds_callout(void *arg) 3526 { 3527 struct radeonfb_display *dp = arg; 3528 int s; 3529 3530 s = splhigh(); 3531 3532 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3533 dp->rd_bl_lvds_val); 3534 dp->rd_bl_lvds_val = 0; 3535 3536 splx(s); 3537 } 3538 3539 static void 3540 radeonfb_brightness_up(device_t dev) 3541 { 3542 struct radeonfb_softc *sc = device_private(dev); 3543 int level; 3544 3545 /* we assume the main display is the first one - need a better way */ 3546 if (sc->sc_ndisplays < 1) return; 3547 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3548 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3549 radeonfb_set_backlight(&sc->sc_displays[0], level); 3550 } 3551 3552 static void 3553 radeonfb_brightness_down(device_t dev) 3554 { 3555 struct radeonfb_softc *sc = device_private(dev); 3556 int level; 3557 3558 /* we assume the main display is the first one - need a better way */ 3559 if (sc->sc_ndisplays < 1) return; 3560 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3561 level = max(0, level - 5); 3562 radeonfb_set_backlight(&sc->sc_displays[0], level); 3563 } 3564