xref: /netbsd-src/sys/dev/pci/ppb.c (revision b1c86f5f087524e68db12794ee9c3e3da1ab17a0)
1 /*	$NetBSD: ppb.c,v 1.42 2010/02/24 22:38:01 dyoung Exp $	*/
2 
3 /*
4  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Christopher G. Demetriou
17  *	for the NetBSD Project.
18  * 4. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.42 2010/02/24 22:38:01 dyoung Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/device.h>
40 
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/ppbreg.h>
44 #include <dev/pci/pcidevs.h>
45 
46 struct ppb_softc {
47 	device_t sc_dev;		/* generic device glue */
48 	pci_chipset_tag_t sc_pc;	/* our PCI chipset... */
49 	pcitag_t sc_tag;		/* ...and tag. */
50 
51 	pcireg_t sc_pciconfext[48];
52 };
53 
54 static bool		ppb_resume(device_t, const pmf_qual_t *);
55 static bool		ppb_suspend(device_t, const pmf_qual_t *);
56 
57 static int
58 ppbmatch(device_t parent, cfdata_t match, void *aux)
59 {
60 	struct pci_attach_args *pa = aux;
61 
62 	/*
63 	 * Check the ID register to see that it's a PCI bridge.
64 	 * If it is, we assume that we can deal with it; it _should_
65 	 * work in a standardized way...
66 	 */
67 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
68 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI)
69 		return 1;
70 
71 	return 0;
72 }
73 
74 static void
75 ppb_fix_pcix(device_t self)
76 {
77 	struct ppb_softc *sc = device_private(self);
78 	pcireg_t reg;
79 	int off;
80 
81 	if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS,
82 				&off, &reg))
83 		return; /* Not a PCIe device */
84 
85 	if ((reg & 0x000f0000) != 0x00010000) {
86 		aprint_normal_dev(self, "unsupported PCI Express version\n");
87 		return;
88 	}
89 	reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x18);
90 	if (reg & 0x003f) {
91 		aprint_normal_dev(self, "disabling notification events\n");
92 		reg &= ~0x003f;
93 		pci_conf_write(sc->sc_pc, sc->sc_tag, off + 0x18, reg);
94 	}
95 }
96 
97 static void
98 ppbattach(device_t parent, device_t self, void *aux)
99 {
100 	struct ppb_softc *sc = device_private(self);
101 	struct pci_attach_args *pa = aux;
102 	pci_chipset_tag_t pc = pa->pa_pc;
103 	struct pcibus_attach_args pba;
104 	pcireg_t busdata;
105 	char devinfo[256];
106 
107 	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
108 	aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
109 	    PCI_REVISION(pa->pa_class));
110 	aprint_naive("\n");
111 
112 	sc->sc_pc = pc;
113 	sc->sc_tag = pa->pa_tag;
114 	sc->sc_dev = self;
115 
116 	busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
117 
118 	if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
119 		aprint_normal_dev(self, "not configured by system firmware\n");
120 		return;
121 	}
122 
123 	ppb_fix_pcix(self);
124 
125 #if 0
126 	/*
127 	 * XXX can't do this, because we're not given our bus number
128 	 * (we shouldn't need it), and because we've no way to
129 	 * decompose our tag.
130 	 */
131 	/* sanity check. */
132 	if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
133 		panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
134 		    pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
135 #endif
136 
137 	if (!pmf_device_register(self, ppb_suspend, ppb_resume))
138 		aprint_error_dev(self, "couldn't establish power handler\n");
139 
140 	/*
141 	 * Attach the PCI bus than hangs off of it.
142 	 *
143 	 * XXX Don't pass-through Memory Read Multiple.  Should we?
144 	 * XXX Consult the spec...
145 	 */
146 	pba.pba_iot = pa->pa_iot;
147 	pba.pba_memt = pa->pa_memt;
148 	pba.pba_dmat = pa->pa_dmat;
149 	pba.pba_dmat64 = pa->pa_dmat64;
150 	pba.pba_pc = pc;
151 	pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
152 	pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
153 	pba.pba_bridgetag = &sc->sc_tag;
154 	pba.pba_intrswiz = pa->pa_intrswiz;
155 	pba.pba_intrtag = pa->pa_intrtag;
156 
157 	config_found_ia(self, "pcibus", &pba, pcibusprint);
158 }
159 
160 static int
161 ppbdetach(device_t self, int flags)
162 {
163 	int rc;
164 
165 	if ((rc = config_detach_children(self, flags)) != 0)
166 		return rc;
167 	pmf_device_deregister(self);
168 	return 0;
169 }
170 
171 static bool
172 ppb_resume(device_t dv, const pmf_qual_t *qual)
173 {
174 	struct ppb_softc *sc = device_private(dv);
175 	int off;
176 	pcireg_t val;
177 
178         for (off = 0x40; off <= 0xff; off += 4) {
179 		val = pci_conf_read(sc->sc_pc, sc->sc_tag, off);
180 		if (val != sc->sc_pciconfext[(off - 0x40) / 4])
181 			pci_conf_write(sc->sc_pc, sc->sc_tag, off,
182 			    sc->sc_pciconfext[(off - 0x40)/4]);
183 	}
184 
185 	ppb_fix_pcix(dv);
186 
187 	return true;
188 }
189 
190 static bool
191 ppb_suspend(device_t dv, const pmf_qual_t *qual)
192 {
193 	struct ppb_softc *sc = device_private(dv);
194 	int off;
195 
196 	for (off = 0x40; off <= 0xff; off += 4)
197 		sc->sc_pciconfext[(off - 0x40) / 4] =
198 		    pci_conf_read(sc->sc_pc, sc->sc_tag, off);
199 
200 	return true;
201 }
202 
203 static void
204 ppbchilddet(device_t self, device_t child)
205 {
206 	/* we keep no references to child devices, so do nothing */
207 }
208 
209 CFATTACH_DECL3_NEW(ppb, sizeof(struct ppb_softc),
210     ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet,
211     DVF_DETACH_SHUTDOWN);
212