xref: /netbsd-src/sys/dev/pci/ppb.c (revision 9ddb6ab554e70fb9bbd90c3d96b812bc57755a14)
1 /*	$NetBSD: ppb.c,v 1.49 2012/01/29 11:31:38 drochner Exp $	*/
2 
3 /*
4  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Christopher G. Demetriou
17  *	for the NetBSD Project.
18  * 4. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.49 2012/01/29 11:31:38 drochner Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/device.h>
40 
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/ppbreg.h>
44 #include <dev/pci/pcidevs.h>
45 
46 #define	PCI_PCIE_SLCSR_NOTIFY_MASK					\
47 	(PCI_PCIE_SLCSR_ABE | PCI_PCIE_SLCSR_PFE | PCI_PCIE_SLCSR_MSE |	\
48 	 PCI_PCIE_SLCSR_PDE | PCI_PCIE_SLCSR_CCE | PCI_PCIE_SLCSR_HPE)
49 
50 struct ppb_softc {
51 	device_t sc_dev;		/* generic device glue */
52 	pci_chipset_tag_t sc_pc;	/* our PCI chipset... */
53 	pcitag_t sc_tag;		/* ...and tag. */
54 
55 	pcireg_t sc_pciconfext[48];
56 };
57 
58 static bool		ppb_resume(device_t, const pmf_qual_t *);
59 static bool		ppb_suspend(device_t, const pmf_qual_t *);
60 
61 static int
62 ppbmatch(device_t parent, cfdata_t match, void *aux)
63 {
64 	struct pci_attach_args *pa = aux;
65 
66 	/*
67 	 * Check the ID register to see that it's a PCI bridge.
68 	 * If it is, we assume that we can deal with it; it _should_
69 	 * work in a standardized way...
70 	 */
71 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
72 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI)
73 		return 1;
74 
75 #ifdef __powerpc__
76 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PROCESSOR &&
77 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PROCESSOR_POWERPC) {
78 		pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag,
79 		    PCI_BHLC_REG);
80 		if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_FREESCALE
81 		    && PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC)
82 		return 1;
83 	}
84 #endif
85 
86 	return 0;
87 }
88 
89 static void
90 ppb_fix_pcie(device_t self)
91 {
92 	struct ppb_softc *sc = device_private(self);
93 	pcireg_t reg;
94 	int off;
95 
96 	if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS,
97 				&off, &reg))
98 		return; /* Not a PCIe device */
99 
100 	aprint_normal_dev(self, "PCI Express ");
101 	switch (reg & PCI_PCIE_XCAP_VER_MASK) {
102 	case PCI_PCIE_XCAP_VER_1_0:
103 		aprint_normal("1.0");
104 		break;
105 	case PCI_PCIE_XCAP_VER_2_0:
106 		aprint_normal("2.0");
107 		break;
108 	default:
109 		aprint_normal_dev(self,
110 		    "version unsupported (0x%" PRIxMAX ")\n",
111 		    __SHIFTOUT(reg, PCI_PCIE_XCAP_VER_MASK));
112 		return;
113 	}
114 	aprint_normal(" <");
115 	switch (reg & PCI_PCIE_XCAP_TYPE_MASK) {
116 	case PCI_PCIE_XCAP_TYPE_PCIE_DEV:
117 		aprint_normal("PCI-E Endpoint device");
118 		break;
119 	case PCI_PCIE_XCAP_TYPE_PCI_DEV:
120 		aprint_normal("Legacy PCI-E Endpoint device");
121 		break;
122 	case PCI_PCIE_XCAP_TYPE_ROOT:
123 		aprint_normal("Root Port of PCI-E Root Complex");
124 		break;
125 	case PCI_PCIE_XCAP_TYPE_UP:
126 		aprint_normal("Upstream Port of PCI-E Switch");
127 		break;
128 	case PCI_PCIE_XCAP_TYPE_DOWN:
129 		aprint_normal("Downstream Port of PCI-E Switch");
130 		break;
131 	case PCI_PCIE_XCAP_TYPE_PCIE2PCI:
132 		aprint_normal("PCI-E to PCI/PCI-X Bridge");
133 		break;
134 	case PCI_PCIE_XCAP_TYPE_PCI2PCIE:
135 		aprint_normal("PCI/PCI-X to PCI-E Bridge");
136 		break;
137 	default:
138 		aprint_normal("Device/Port Type 0x%" PRIxMAX,
139 		    __SHIFTOUT(reg, PCI_PCIE_XCAP_TYPE_MASK));
140 		break;
141 	}
142 	aprint_normal(">\n");
143 
144 	reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCI_PCIE_SLCSR);
145 	if (reg & PCI_PCIE_SLCSR_NOTIFY_MASK) {
146 		aprint_debug_dev(self, "disabling notification events\n");
147 		reg &= ~PCI_PCIE_SLCSR_NOTIFY_MASK;
148 		pci_conf_write(sc->sc_pc, sc->sc_tag,
149 		    off + PCI_PCIE_SLCSR, reg);
150 	}
151 }
152 
153 static void
154 ppbattach(device_t parent, device_t self, void *aux)
155 {
156 	struct ppb_softc *sc = device_private(self);
157 	struct pci_attach_args *pa = aux;
158 	pci_chipset_tag_t pc = pa->pa_pc;
159 	struct pcibus_attach_args pba;
160 	pcireg_t busdata;
161 
162 	pci_aprint_devinfo(pa, NULL);
163 
164 	sc->sc_pc = pc;
165 	sc->sc_tag = pa->pa_tag;
166 	sc->sc_dev = self;
167 
168 	busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
169 
170 	if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
171 		aprint_normal_dev(self, "not configured by system firmware\n");
172 		return;
173 	}
174 
175 	ppb_fix_pcie(self);
176 
177 #if 0
178 	/*
179 	 * XXX can't do this, because we're not given our bus number
180 	 * (we shouldn't need it), and because we've no way to
181 	 * decompose our tag.
182 	 */
183 	/* sanity check. */
184 	if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
185 		panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
186 		    pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
187 #endif
188 
189 	if (!pmf_device_register(self, ppb_suspend, ppb_resume))
190 		aprint_error_dev(self, "couldn't establish power handler\n");
191 
192 	/*
193 	 * Attach the PCI bus than hangs off of it.
194 	 *
195 	 * XXX Don't pass-through Memory Read Multiple.  Should we?
196 	 * XXX Consult the spec...
197 	 */
198 	pba.pba_iot = pa->pa_iot;
199 	pba.pba_memt = pa->pa_memt;
200 	pba.pba_dmat = pa->pa_dmat;
201 	pba.pba_dmat64 = pa->pa_dmat64;
202 	pba.pba_pc = pc;
203 	pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
204 	pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
205 	pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata);
206 	pba.pba_bridgetag = &sc->sc_tag;
207 	pba.pba_intrswiz = pa->pa_intrswiz;
208 	pba.pba_intrtag = pa->pa_intrtag;
209 
210 	config_found_ia(self, "pcibus", &pba, pcibusprint);
211 }
212 
213 static int
214 ppbdetach(device_t self, int flags)
215 {
216 	int rc;
217 
218 	if ((rc = config_detach_children(self, flags)) != 0)
219 		return rc;
220 	pmf_device_deregister(self);
221 	return 0;
222 }
223 
224 static bool
225 ppb_resume(device_t dv, const pmf_qual_t *qual)
226 {
227 	struct ppb_softc *sc = device_private(dv);
228 	int off;
229 	pcireg_t val;
230 
231         for (off = 0x40; off <= 0xff; off += 4) {
232 		val = pci_conf_read(sc->sc_pc, sc->sc_tag, off);
233 		if (val != sc->sc_pciconfext[(off - 0x40) / 4])
234 			pci_conf_write(sc->sc_pc, sc->sc_tag, off,
235 			    sc->sc_pciconfext[(off - 0x40)/4]);
236 	}
237 
238 	ppb_fix_pcie(dv);
239 
240 	return true;
241 }
242 
243 static bool
244 ppb_suspend(device_t dv, const pmf_qual_t *qual)
245 {
246 	struct ppb_softc *sc = device_private(dv);
247 	int off;
248 
249 	for (off = 0x40; off <= 0xff; off += 4)
250 		sc->sc_pciconfext[(off - 0x40) / 4] =
251 		    pci_conf_read(sc->sc_pc, sc->sc_tag, off);
252 
253 	return true;
254 }
255 
256 static void
257 ppbchilddet(device_t self, device_t child)
258 {
259 	/* we keep no references to child devices, so do nothing */
260 }
261 
262 CFATTACH_DECL3_NEW(ppb, sizeof(struct ppb_softc),
263     ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet,
264     DVF_DETACH_SHUTDOWN);
265