1 /* $NetBSD: pm3fb.c,v 1.9 2022/09/25 17:52:25 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Naruaki Etomi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * A console driver for Permedia 3 graphics controllers 30 * most of the following was adapted from the xf86-video-glint driver's 31 * pm3_accel.c, pm3_dac.c and pm2fb framebuffer console driver 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pm3fb.c,v 1.9 2022/09/25 17:52:25 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/lwp.h> 42 #include <sys/kauth.h> 43 #include <sys/atomic.h> 44 45 #include <dev/videomode/videomode.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciio.h> 51 #include <dev/pci/pm3reg.h> 52 53 #include <dev/wscons/wsdisplayvar.h> 54 #include <dev/wscons/wsconsio.h> 55 #include <dev/wsfont/wsfont.h> 56 #include <dev/rasops/rasops.h> 57 #include <dev/wscons/wsdisplay_vconsvar.h> 58 #include <dev/pci/wsdisplay_pci.h> 59 60 #include <dev/i2c/i2cvar.h> 61 #include <dev/i2c/i2c_bitbang.h> 62 #include <dev/i2c/ddcvar.h> 63 #include <dev/videomode/videomode.h> 64 #include <dev/videomode/edidvar.h> 65 #include <dev/videomode/edidreg.h> 66 67 struct pm3fb_softc { 68 device_t sc_dev; 69 70 pci_chipset_tag_t sc_pc; 71 pcitag_t sc_pcitag; 72 73 bus_space_tag_t sc_memt; 74 bus_space_tag_t sc_iot; 75 76 bus_space_handle_t sc_regh; 77 bus_addr_t sc_fb, sc_reg; 78 bus_size_t sc_fbsize, sc_regsize; 79 80 int sc_width, sc_height, sc_depth, sc_stride; 81 int sc_locked; 82 struct vcons_screen sc_console_screen; 83 struct wsscreen_descr sc_defaultscreen_descr; 84 const struct wsscreen_descr *sc_screens[1]; 85 struct wsscreen_list sc_screenlist; 86 struct vcons_data vd; 87 int sc_mode; 88 u_char sc_cmap_red[256]; 89 u_char sc_cmap_green[256]; 90 u_char sc_cmap_blue[256]; 91 /* i2c stuff */ 92 struct i2c_controller sc_i2c; 93 uint8_t sc_edid_data[128]; 94 struct edid_info sc_ei; 95 const struct videomode *sc_videomode; 96 }; 97 98 static int pm3fb_match(device_t, cfdata_t, void *); 99 static void pm3fb_attach(device_t, device_t, void *); 100 101 CFATTACH_DECL_NEW(pm3fb, sizeof(struct pm3fb_softc), 102 pm3fb_match, pm3fb_attach, NULL, NULL); 103 104 extern const u_char rasops_cmap[768]; 105 106 static int pm3fb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 107 static paddr_t pm3fb_mmap(void *, void *, off_t, int); 108 static void pm3fb_init_screen(void *, struct vcons_screen *, int, long *); 109 110 static int pm3fb_putcmap(struct pm3fb_softc *, struct wsdisplay_cmap *); 111 static int pm3fb_getcmap(struct pm3fb_softc *, struct wsdisplay_cmap *); 112 static void pm3fb_init_palette(struct pm3fb_softc *); 113 static int pm3fb_putpalreg(struct pm3fb_softc *, uint8_t, uint8_t, uint8_t, uint8_t); 114 115 static void pm3fb_init(struct pm3fb_softc *); 116 static inline void pm3fb_wait(struct pm3fb_softc *, int); 117 static void pm3fb_flush_engine(struct pm3fb_softc *); 118 static void pm3fb_rectfill(struct pm3fb_softc *, int, int, int, int, uint32_t); 119 static void pm3fb_bitblt(void *, int, int, int, int, int, int, int); 120 121 static void pm3fb_cursor(void *, int, int, int); 122 static void pm3fb_putchar(void *, int, int, u_int, long); 123 static void pm3fb_copycols(void *, int, int, int, int); 124 static void pm3fb_erasecols(void *, int, int, int, long); 125 static void pm3fb_copyrows(void *, int, int, int); 126 static void pm3fb_eraserows(void *, int, int, long); 127 128 struct wsdisplay_accessops pm3fb_accessops = { 129 pm3fb_ioctl, 130 pm3fb_mmap, 131 NULL, /* alloc_screen */ 132 NULL, /* free_screen */ 133 NULL, /* show_screen */ 134 NULL, /* load_font */ 135 NULL, /* pollc */ 136 NULL /* scroll */ 137 }; 138 139 /* I2C glue */ 140 static int pm3fb_i2c_send_start(void *, int); 141 static int pm3fb_i2c_send_stop(void *, int); 142 static int pm3fb_i2c_initiate_xfer(void *, i2c_addr_t, int); 143 static int pm3fb_i2c_read_byte(void *, uint8_t *, int); 144 static int pm3fb_i2c_write_byte(void *, uint8_t, int); 145 146 /* I2C bitbang glue */ 147 static void pm3fb_i2cbb_set_bits(void *, uint32_t); 148 static void pm3fb_i2cbb_set_dir(void *, uint32_t); 149 static uint32_t pm3fb_i2cbb_read(void *); 150 151 static void pm3_setup_i2c(struct pm3fb_softc *); 152 153 static const struct i2c_bitbang_ops pm3fb_i2cbb_ops = { 154 pm3fb_i2cbb_set_bits, 155 pm3fb_i2cbb_set_dir, 156 pm3fb_i2cbb_read, 157 { 158 PM3_DD_SDA_IN, 159 PM3_DD_SCL_IN, 160 0, 161 0 162 } 163 }; 164 165 /* mode setting stuff */ 166 static int pm3fb_set_pll(struct pm3fb_softc *, int); 167 static void pm3fb_write_dac(struct pm3fb_softc *, int, uint8_t); 168 static void pm3fb_set_mode(struct pm3fb_softc *, const struct videomode *); 169 170 static inline void 171 pm3fb_wait(struct pm3fb_softc *sc, int slots) 172 { 173 uint32_t reg; 174 175 do { 176 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, 177 PM3_INPUT_FIFO_SPACE); 178 } while (reg <= slots); 179 } 180 181 static void 182 pm3fb_flush_engine(struct pm3fb_softc *sc) 183 { 184 185 pm3fb_wait(sc, 2); 186 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FILTER_MODE, PM3_FM_PASS_SYNC); 187 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SYNC, 0); 188 189 do { 190 while (bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_OUTPUT_FIFO_WORDS) == 0); 191 } while (bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_OUTPUT_FIFO) != 192 PM3_SYNC_TAG); 193 } 194 195 static int 196 pm3fb_match(device_t parent, cfdata_t match, void *aux) 197 { 198 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 199 200 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 201 return 0; 202 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3DLABS) 203 return 0; 204 205 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DLABS_PERMEDIA3) 206 return 100; 207 return (0); 208 } 209 210 static void 211 pm3fb_attach(device_t parent, device_t self, void *aux) 212 { 213 struct pm3fb_softc *sc = device_private(self); 214 struct pci_attach_args *pa = aux; 215 struct rasops_info *ri; 216 struct wsemuldisplaydev_attach_args aa; 217 prop_dictionary_t dict; 218 unsigned long defattr; 219 bool is_console; 220 uint32_t flags; 221 222 sc->sc_pc = pa->pa_pc; 223 sc->sc_pcitag = pa->pa_tag; 224 sc->sc_memt = pa->pa_memt; 225 sc->sc_iot = pa->pa_iot; 226 sc->sc_dev = self; 227 228 pci_aprint_devinfo(pa, NULL); 229 230 /* 231 * fill in parameters from properties 232 * if we can't get a usable mode via DDC2 we'll use this to pick one, 233 * which is why we fill them in with some conservative values that 234 * hopefully work as a last resort 235 */ 236 dict = device_properties(self); 237 if (!prop_dictionary_get_uint32(dict, "width", &sc->sc_width)) { 238 aprint_error("%s: no width property\n", device_xname(self)); 239 sc->sc_width = 1280; 240 } 241 if (!prop_dictionary_get_uint32(dict, "height", &sc->sc_height)) { 242 aprint_error("%s: no height property\n", device_xname(self)); 243 sc->sc_height = 1024; 244 } 245 if (!prop_dictionary_get_uint32(dict, "depth", &sc->sc_depth)) { 246 aprint_error("%s: no depth property\n", device_xname(self)); 247 sc->sc_depth = 8; 248 } 249 250 sc->sc_stride = sc->sc_width * (sc->sc_depth >> 3); 251 252 prop_dictionary_get_bool(dict, "is_console", &is_console); 253 254 pci_mapreg_info(pa->pa_pc, pa->pa_tag, 0x14, PCI_MAPREG_TYPE_MEM, 255 &sc->sc_fb, &sc->sc_fbsize, &flags); 256 257 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0, 258 &sc->sc_memt, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) { 259 aprint_error("%s: failed to map registers.\n", 260 device_xname(sc->sc_dev)); 261 } 262 263 /* 264 * Permedia 3 always return 64MB fbsize 265 * 16 MB should be enough -- more just wastes map entries 266 */ 267 if (sc->sc_fbsize != 0) 268 sc->sc_fbsize = (16 << 20); 269 270 /* 271 * Some Power Mac G4 model could not initialize these registers, 272 * Power Mac G4 (Mirrored Drive Doors), for example 273 */ 274 #if defined(__powerpc__) 275 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOCALMEMCAPS, 0x02e311B8); 276 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOCALMEMTIMINGS, 0x07424905); 277 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOCALMEMCONTROL, 0x0c000003); 278 #endif 279 280 aprint_normal("%s: %d MB aperture at 0x%08x\n", device_xname(self), 281 (int)(sc->sc_fbsize >> 20), (uint32_t)sc->sc_fb); 282 283 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 284 "default", 285 0, 0, 286 NULL, 287 8, 16, 288 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 289 NULL 290 }; 291 292 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 293 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 294 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 295 sc->sc_locked = 0; 296 297 pm3_setup_i2c(sc); 298 299 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 300 &pm3fb_accessops); 301 302 sc->vd.init_screen = pm3fb_init_screen; 303 304 /* init engine here */ 305 pm3fb_init(sc); 306 307 ri = &sc->sc_console_screen.scr_ri; 308 309 if (is_console) { 310 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 311 &defattr); 312 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 313 314 pm3fb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height, 315 ri->ri_devcmap[(defattr >> 16) & 0xff]); 316 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 317 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 318 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 319 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 320 321 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 322 defattr); 323 vcons_replay_msgbuf(&sc->sc_console_screen); 324 } else { 325 if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 326 /* do some minimal setup to avoid weirdnesses later */ 327 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 328 &defattr); 329 } 330 } 331 332 pm3fb_init_palette(sc); 333 334 aa.console = is_console; 335 aa.scrdata = &sc->sc_screenlist; 336 aa.accessops = &pm3fb_accessops; 337 aa.accesscookie = &sc->vd; 338 339 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, CFARGS_NONE); 340 } 341 342 static int 343 pm3fb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 344 struct lwp *l) 345 { 346 struct vcons_data *vd = v; 347 struct pm3fb_softc *sc = vd->cookie; 348 struct wsdisplay_fbinfo *wdf; 349 struct vcons_screen *ms = vd->active; 350 351 switch (cmd) { 352 case WSDISPLAYIO_GTYPE: 353 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 354 return 0; 355 356 /* PCI config read/write passthrough. */ 357 case PCI_IOC_CFGREAD: 358 case PCI_IOC_CFGWRITE: 359 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 360 cmd, data, flag, l); 361 362 case WSDISPLAYIO_GET_BUSID: 363 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 364 sc->sc_pcitag, data); 365 366 case WSDISPLAYIO_GINFO: 367 if (ms == NULL) 368 return ENODEV; 369 wdf = (void *)data; 370 wdf->height = ms->scr_ri.ri_height; 371 wdf->width = ms->scr_ri.ri_width; 372 wdf->depth = ms->scr_ri.ri_depth; 373 wdf->cmsize = 256; 374 return 0; 375 376 case WSDISPLAYIO_GETCMAP: 377 return pm3fb_getcmap(sc, 378 (struct wsdisplay_cmap *)data); 379 380 case WSDISPLAYIO_PUTCMAP: 381 return pm3fb_putcmap(sc, 382 (struct wsdisplay_cmap *)data); 383 384 case WSDISPLAYIO_LINEBYTES: 385 *(u_int *)data = sc->sc_stride; 386 return 0; 387 388 case WSDISPLAYIO_SMODE: { 389 int new_mode = *(int*)data; 390 if (new_mode != sc->sc_mode) { 391 sc->sc_mode = new_mode; 392 if(new_mode == WSDISPLAYIO_MODE_EMUL) { 393 /* first set the video mode */ 394 if (sc->sc_videomode != NULL) { 395 pm3fb_set_mode(sc, sc->sc_videomode); 396 } 397 /* then initialize the drawing engine */ 398 pm3fb_init(sc); 399 pm3fb_init_palette(sc); 400 vcons_redraw_screen(ms); 401 } else 402 pm3fb_flush_engine(sc); 403 } 404 } 405 return 0; 406 case WSDISPLAYIO_GET_EDID: { 407 struct wsdisplayio_edid_info *d = data; 408 d->data_size = 128; 409 if (d->buffer_size < 128) 410 return EAGAIN; 411 return copyout(sc->sc_edid_data, d->edid_data, 128); 412 } 413 414 case WSDISPLAYIO_GET_FBINFO: { 415 struct wsdisplayio_fbinfo *fbi = data; 416 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 417 } 418 } 419 return EPASSTHROUGH; 420 } 421 422 static paddr_t 423 pm3fb_mmap(void *v, void *vs, off_t offset, int prot) 424 { 425 struct vcons_data *vd = v; 426 struct pm3fb_softc *sc = vd->cookie; 427 paddr_t pa; 428 429 /* 'regular' framebuffer mmap()ing */ 430 if (offset < sc->sc_fbsize) { 431 pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset, 0, prot, 432 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 433 return pa; 434 } 435 436 /* 437 * restrict all other mappings to processes with superuser privileges 438 * or the kernel itself 439 */ 440 if (kauth_authorize_machdep(kauth_cred_get(), 441 KAUTH_MACHDEP_UNMANAGEDMEM, 442 NULL, NULL, NULL, NULL) != 0) { 443 aprint_normal("%s: mmap() rejected.\n", 444 device_xname(sc->sc_dev)); 445 return -1; 446 } 447 448 if ((offset >= sc->sc_fb) && (offset < (sc->sc_fb + sc->sc_fbsize))) { 449 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 450 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 451 return pa; 452 } 453 454 if ((offset >= sc->sc_reg) && 455 (offset < (sc->sc_reg + sc->sc_regsize))) { 456 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 457 BUS_SPACE_MAP_LINEAR); 458 return pa; 459 } 460 461 #ifdef PCI_MAGIC_IO_RANGE 462 /* allow mapping of IO space */ 463 if ((offset >= PCI_MAGIC_IO_RANGE) && 464 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 465 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 466 0, prot, BUS_SPACE_MAP_LINEAR); 467 return pa; 468 } 469 #endif 470 return -1; 471 } 472 473 static void 474 pm3fb_init_screen(void *cookie, struct vcons_screen *scr, 475 int existing, long *defattr) 476 { 477 struct pm3fb_softc *sc = cookie; 478 struct rasops_info *ri = &scr->scr_ri; 479 480 ri->ri_depth = sc->sc_depth; 481 ri->ri_width = sc->sc_width; 482 ri->ri_height = sc->sc_height; 483 ri->ri_stride = sc->sc_stride; 484 ri->ri_flg = RI_CENTER; 485 if (sc->sc_depth == 8) 486 ri->ri_flg |= RI_8BIT_IS_RGB; 487 488 rasops_init(ri, 0, 0); 489 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE; 490 491 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 492 sc->sc_width / ri->ri_font->fontwidth); 493 494 ri->ri_hw = scr; 495 ri->ri_ops.copyrows = pm3fb_copyrows; 496 ri->ri_ops.copycols = pm3fb_copycols; 497 ri->ri_ops.cursor = pm3fb_cursor; 498 ri->ri_ops.eraserows = pm3fb_eraserows; 499 ri->ri_ops.erasecols = pm3fb_erasecols; 500 ri->ri_ops.putchar = pm3fb_putchar; 501 } 502 503 static int 504 pm3fb_putcmap(struct pm3fb_softc *sc, struct wsdisplay_cmap *cm) 505 { 506 u_char *r, *g, *b; 507 u_int index = cm->index; 508 u_int count = cm->count; 509 int i, error; 510 u_char rbuf[256], gbuf[256], bbuf[256]; 511 512 if (cm->index >= 256 || cm->count > 256 || 513 (cm->index + cm->count) > 256) 514 return EINVAL; 515 error = copyin(cm->red, &rbuf[index], count); 516 if (error) 517 return error; 518 error = copyin(cm->green, &gbuf[index], count); 519 if (error) 520 return error; 521 error = copyin(cm->blue, &bbuf[index], count); 522 if (error) 523 return error; 524 525 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 526 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 527 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 528 529 r = &sc->sc_cmap_red[index]; 530 g = &sc->sc_cmap_green[index]; 531 b = &sc->sc_cmap_blue[index]; 532 533 for (i = 0; i < count; i++) { 534 pm3fb_putpalreg(sc, index, *r, *g, *b); 535 index++; 536 r++, g++, b++; 537 } 538 return 0; 539 } 540 541 static int 542 pm3fb_getcmap(struct pm3fb_softc *sc, struct wsdisplay_cmap *cm) 543 { 544 u_int index = cm->index; 545 u_int count = cm->count; 546 int error; 547 548 if (index >= 255 || count > 256 || index + count > 256) 549 return EINVAL; 550 551 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 552 if (error) 553 return error; 554 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 555 if (error) 556 return error; 557 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 558 if (error) 559 return error; 560 561 return 0; 562 } 563 564 static void 565 pm3fb_init_palette(struct pm3fb_softc *sc) 566 { 567 struct rasops_info *ri = &sc->sc_console_screen.scr_ri; 568 int i, j = 0; 569 uint8_t cmap[768]; 570 571 rasops_get_cmap(ri, cmap, sizeof(cmap)); 572 573 for (i = 0; i < 256; i++) { 574 sc->sc_cmap_red[i] = cmap[j]; 575 sc->sc_cmap_green[i] = cmap[j + 1]; 576 sc->sc_cmap_blue[i] = cmap[j + 2]; 577 pm3fb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]); 578 j += 3; 579 } 580 } 581 582 static int 583 pm3fb_putpalreg(struct pm3fb_softc *sc, uint8_t idx, uint8_t r, uint8_t g, uint8_t b) 584 { 585 586 pm3fb_wait(sc, 4); 587 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_WRITE_IDX, idx); 588 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_DATA, r); 589 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_DATA, g); 590 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_DATA, b); 591 return 0; 592 } 593 594 static void 595 pm3fb_write_dac(struct pm3fb_softc *sc, int reg, uint8_t data) 596 { 597 598 pm3fb_wait(sc, 3); 599 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_LOW, reg & 0xff); 600 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_HIGH, (reg >> 8) & 0xff); 601 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_DATA, data); 602 } 603 604 static void 605 pm3fb_init(struct pm3fb_softc *sc) 606 { 607 608 pm3fb_wait(sc, 16); 609 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_DESTREAD_MODE, 0); 610 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_DESTREAD_ENABLES, 0); 611 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_SOURCEREAD_MODE, 0); 612 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_WRITE_MODE, 0); 613 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FILTER_MODE, PM3_FM_PASS_SYNC); 614 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STATISTIC_MODE, 0); 615 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DELTA_MODE, 0); 616 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RASTERIZER_MODE, 0); 617 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCISSOR_MODE, 0); 618 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LINESTIPPLE_MODE, 0); 619 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_AREASTIPPLE_MODE, 0); 620 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_GID_MODE, 0); 621 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DEPTH_MODE, 0); 622 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STENCIL_MODE, 0); 623 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STENCIL_DATA, 0); 624 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_COLORDDA_MODE, 0); 625 626 pm3fb_wait(sc, 16); 627 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREADDRESS_MODE, 0); 628 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREINDEX_MODE0, 0); 629 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREINDEX_MODE1, 0); 630 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREREAD_MODE, 0); 631 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXELLUT_MODE, 0); 632 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREFILTER_MODE, 0); 633 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITE_MODE, 0); 634 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOLOR_MODE, 0); 635 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITECOLOR_MODE1, 0); 636 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITEALPHA_MODE1, 0); 637 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITECOLOR_MODE0, 0); 638 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITEALPHA_MODE0, 0); 639 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FOG_MODE, 0); 640 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CHROMATEST_MODE, 0); 641 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ALPHATEST_MODE, 0); 642 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ANTIALIAS_MODE, 0); 643 644 pm3fb_wait(sc, 16); 645 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_YUV_MODE, 0); 646 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ALPHABLENDCOLOR_MODE, 0); 647 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ALPHABLENDALPHA_MODE, 0); 648 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DITHER_MODE, 0); 649 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOGICALOP_MODE, 0); 650 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ROUTER_MODE, 0); 651 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_WINDOW, 0); 652 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 0); 653 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SPANCOLORMASK, 0xffffffff); 654 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_XBIAS, 0); 655 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_YBIAS, 0); 656 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DELTACONTROL, 0); 657 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_BITMASKPATTERN, 0xffffffff); 658 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_ENABLE, 659 PM3_FBDESTREAD_SET(0xff, 0xff, 0xff)); 660 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_BUFFERADDRESS0, 0); 661 662 pm3fb_wait(sc, 16); 663 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_BUFFEROFFSET0, 0); 664 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_BUFFERWIDTH0, 665 PM3_FBDESTREAD_BUFFERWIDTH_WIDTH(sc->sc_stride)); 666 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FB_DESTREAD_MODE, 667 PM3_FBDRM_ENABLE | PM3_FBDRM_ENABLE0); 668 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFERADDRESS, 0); 669 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFEROFFSET, 0); 670 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFERWIDTH, 671 PM3_FBSOURCEREAD_BUFFERWIDTH_WIDTH(sc->sc_stride)); 672 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_MODE, 673 PM3_FBSOURCEREAD_MODE_BLOCKING | PM3_FBSOURCEREAD_MODE_ENABLE); 674 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_PIXEL_SIZE, PM3_PS_8BIT); 675 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOFTWAREWRITEMASK, 0xffffffff); 676 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBHARDWAREWRITEMASK, 0xffffffff); 677 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITE_MODE, 678 PM3_FBWRITEMODE_WRITEENABLE | PM3_FBWRITEMODE_OPAQUESPAN | PM3_FBWRITEMODE_ENABLE0); 679 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITEBUFFERADDRESS0, 0); 680 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITEBUFFEROFFSET0, 0); 681 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITEBUFFERWIDTH0, 682 PM3_FBWRITEBUFFERWIDTH_WIDTH(sc->sc_stride)); 683 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SIZEOF_FRAMEBUFFER, 4095); 684 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DITHER_MODE, PM3_CF_TO_DIM_CF(4)); 685 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DXDOM, 0); 686 687 pm3fb_wait(sc, 6); 688 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DXSUB, 0); 689 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DY, 1 << 16); 690 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STARTXDOM, 0); 691 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STARTXSUB, 0); 692 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STARTY, 0); 693 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_COUNT, 0); 694 } 695 696 static void 697 pm3fb_rectfill(struct pm3fb_softc *sc, int x, int y, int wi, int he, 698 uint32_t colour) 699 { 700 pm3fb_wait(sc, 4); 701 702 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 703 PM3_CONFIG2D_USECONSTANTSOURCE | PM3_CONFIG2D_FOREGROUNDROP_ENABLE | 704 (PM3_CONFIG2D_FOREGROUNDROP(0x3)) | PM3_CONFIG2D_FBWRITE_ENABLE); 705 706 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FOREGROUNDCOLOR, colour); 707 708 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RECTANGLEPOSITION, 709 (((y) & 0xffff) << 16) | ((x) & 0xffff) ); 710 711 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RENDER2D, 712 PM3_RENDER2D_XPOSITIVE | PM3_RENDER2D_YPOSITIVE | 713 PM3_RENDER2D_OPERATION_NORMAL | PM3_RENDER2D_SPANOPERATION | 714 (((he) & 0x0fff) << 16) | ((wi) & 0x0fff)); 715 716 #ifdef PM3FB_DEBUG 717 pm3fb_flush_engine(sc); 718 #endif 719 } 720 721 static void 722 pm3fb_bitblt(void *cookie, int srcx, int srcy, int dstx, int dsty, 723 int width, int height, int rop) 724 { 725 struct pm3fb_softc *sc = cookie; 726 int x_align, offset_x, offset_y; 727 uint32_t dir = 0; 728 729 offset_x = srcx - dstx; 730 offset_y = srcy - dsty; 731 732 if (dsty <= srcy) { 733 dir |= PM3_RENDER2D_YPOSITIVE; 734 } 735 736 if (dstx <= srcx) { 737 dir |= PM3_RENDER2D_XPOSITIVE; 738 } 739 740 x_align = (srcx & 0x1f); 741 742 pm3fb_wait(sc, 6); 743 744 if (rop == 3){ 745 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 746 PM3_CONFIG2D_USERSCISSOR_ENABLE | PM3_CONFIG2D_FOREGROUNDROP_ENABLE | PM3_CONFIG2D_BLOCKING | 747 PM3_CONFIG2D_FOREGROUNDROP(rop) | PM3_CONFIG2D_FBWRITE_ENABLE); 748 } else { 749 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 750 PM3_CONFIG2D_USERSCISSOR_ENABLE | PM3_CONFIG2D_FOREGROUNDROP_ENABLE | PM3_CONFIG2D_BLOCKING | 751 PM3_CONFIG2D_FOREGROUNDROP(rop) | PM3_CONFIG2D_FBWRITE_ENABLE | PM3_CONFIG2D_FBDESTREAD_ENABLE); 752 } 753 754 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCISSORMINXY, 755 ((dsty & 0x0fff) << 16) | (dstx & 0x0fff)); 756 757 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCISSORMAXXY, 758 (((dsty + height) & 0x0fff) << 16) | ((dstx + width) & 0x0fff)); 759 760 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFEROFFSET, 761 (((offset_y) & 0xffff) << 16) | ((offset_x) & 0xffff)); 762 763 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RECTANGLEPOSITION, 764 (((dsty) & 0xffff) << 16) | ((dstx - x_align) & 0xffff)); 765 766 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RENDER2D, 767 dir | 768 PM3_RENDER2D_OPERATION_NORMAL | PM3_RENDER2D_SPANOPERATION | PM3_RENDER2D_FBSOURCEREADENABLE | 769 (((height) & 0x0fff) << 16) | ((width + x_align) & 0x0fff)); 770 771 #ifdef PM3FB_DEBUG 772 pm3fb_flush_engine(sc); 773 #endif 774 } 775 776 static void 777 pm3fb_cursor(void *cookie, int on, int row, int col) 778 { 779 struct rasops_info *ri = cookie; 780 struct vcons_screen *scr = ri->ri_hw; 781 struct pm3fb_softc *sc = scr->scr_cookie; 782 int x, y, wi, he; 783 784 wi = ri->ri_font->fontwidth; 785 he = ri->ri_font->fontheight; 786 787 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 788 x = ri->ri_ccol * wi + ri->ri_xorigin; 789 y = ri->ri_crow * he + ri->ri_yorigin; 790 if (ri->ri_flg & RI_CURSOR) { 791 pm3fb_bitblt(sc, x, y, x, y, wi, he, 12); 792 ri->ri_flg &= ~RI_CURSOR; 793 } 794 ri->ri_crow = row; 795 ri->ri_ccol = col; 796 if (on) { 797 x = ri->ri_ccol * wi + ri->ri_xorigin; 798 y = ri->ri_crow * he + ri->ri_yorigin; 799 pm3fb_bitblt(sc, x, y, x, y, wi, he, 12); 800 ri->ri_flg |= RI_CURSOR; 801 } 802 } else { 803 scr->scr_ri.ri_crow = row; 804 scr->scr_ri.ri_ccol = col; 805 scr->scr_ri.ri_flg &= ~RI_CURSOR; 806 } 807 } 808 809 static void 810 pm3fb_putchar(void *cookie, int row, int col, u_int c, long attr) 811 { 812 struct rasops_info *ri = cookie; 813 struct wsdisplay_font *font = PICK_FONT(ri, c); 814 struct vcons_screen *scr = ri->ri_hw; 815 struct pm3fb_softc *sc = scr->scr_cookie; 816 uint32_t mode; 817 818 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 819 void *data; 820 uint32_t fg, bg; 821 int uc, i; 822 int x, y, wi, he; 823 824 wi = font->fontwidth; 825 he = font->fontheight; 826 827 if (!CHAR_IN_FONT(c, font)) 828 return; 829 830 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 831 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 832 x = ri->ri_xorigin + col * wi; 833 y = ri->ri_yorigin + row * he; 834 if (c == 0x20) { 835 pm3fb_rectfill(sc, x, y, wi, he, bg); 836 } else { 837 uc = c - font->firstchar; 838 data = (uint8_t *)font->data + uc * ri->ri_fontscale; 839 mode = PM3_RM_MASK_MIRROR; 840 841 #if BYTE_ORDER == LITTLE_ENDIAN 842 switch (ri->ri_font->stride) { 843 case 1: 844 mode |= 4 << 7; 845 break; 846 case 2: 847 mode |= 3 << 7; 848 break; 849 } 850 #else 851 switch (ri->ri_font->stride) { 852 case 1: 853 mode |= 3 << 7; 854 break; 855 case 2: 856 mode |= 2 << 7; 857 break; 858 } 859 #endif 860 pm3fb_wait(sc, 8); 861 bus_space_write_4(sc->sc_memt, sc->sc_regh, 862 PM3_FOREGROUNDCOLOR, fg); 863 bus_space_write_4(sc->sc_memt, sc->sc_regh, 864 PM3_BACKGROUNDCOLOR, bg); 865 866 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RASTERIZER_MODE, mode); 867 868 bus_space_write_4(sc->sc_memt, sc->sc_regh, 869 PM3_CONFIG2D, 870 PM3_CONFIG2D_USERSCISSOR_ENABLE | 871 PM3_CONFIG2D_USECONSTANTSOURCE | 872 PM3_CONFIG2D_FOREGROUNDROP_ENABLE | 873 PM3_CONFIG2D_FOREGROUNDROP(0x03) | 874 PM3_CONFIG2D_OPAQUESPAN | 875 PM3_CONFIG2D_FBWRITE_ENABLE); 876 877 bus_space_write_4(sc->sc_memt, sc->sc_regh, 878 PM3_SCISSORMINXY, ((y & 0x0fff) << 16) | (x & 0x0fff)); 879 880 bus_space_write_4(sc->sc_memt, sc->sc_regh, 881 PM3_SCISSORMAXXY, (((y + he) & 0x0fff) << 16) | ((x + wi) & 0x0fff)); 882 883 bus_space_write_4(sc->sc_memt, sc->sc_regh, 884 PM3_RECTANGLEPOSITION, (((y) & 0xffff)<<16) | ((x) & 0xffff)); 885 886 bus_space_write_4(sc->sc_memt, sc->sc_regh, 887 PM3_RENDER2D, 888 PM3_RENDER2D_XPOSITIVE | 889 PM3_RENDER2D_YPOSITIVE | 890 PM3_RENDER2D_OPERATION_SYNCONBITMASK | 891 PM3_RENDER2D_SPANOPERATION | 892 ((wi) & 0x0fff) | (((he) & 0x0fff) << 16)); 893 894 pm3fb_wait(sc, he); 895 896 switch (ri->ri_font->stride) { 897 case 1: { 898 uint8_t *data8 = data; 899 uint32_t reg; 900 for (i = 0; i < he; i++) { 901 reg = *data8; 902 bus_space_write_4(sc->sc_memt, 903 sc->sc_regh, 904 PM3_BITMASKPATTERN, reg); 905 data8++; 906 } 907 break; 908 } 909 case 2: { 910 uint16_t *data16 = data; 911 uint32_t reg; 912 for (i = 0; i < he; i++) { 913 reg = *data16; 914 bus_space_write_4(sc->sc_memt, 915 sc->sc_regh, 916 PM3_BITMASKPATTERN, reg); 917 data16++; 918 } 919 break; 920 } 921 } 922 } 923 } 924 } 925 926 static void 927 pm3fb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 928 { 929 struct rasops_info *ri = cookie; 930 struct vcons_screen *scr = ri->ri_hw; 931 struct pm3fb_softc *sc = scr->scr_cookie; 932 int32_t xs, xd, y, width, height; 933 934 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 935 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 936 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 937 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 938 width = ri->ri_font->fontwidth * ncols; 939 height = ri->ri_font->fontheight; 940 pm3fb_bitblt(sc, xs, y, xd, y, width, height, 3); 941 } 942 } 943 944 static void 945 pm3fb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 946 { 947 struct rasops_info *ri = cookie; 948 struct vcons_screen *scr = ri->ri_hw; 949 struct pm3fb_softc *sc = scr->scr_cookie; 950 int32_t x, y, width, height, fg, bg, ul; 951 952 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 953 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 954 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 955 width = ri->ri_font->fontwidth * ncols; 956 height = ri->ri_font->fontheight; 957 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 958 959 pm3fb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 960 } 961 } 962 963 static void 964 pm3fb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 965 { 966 struct rasops_info *ri = cookie; 967 struct vcons_screen *scr = ri->ri_hw; 968 struct pm3fb_softc *sc = scr->scr_cookie; 969 int32_t x, ys, yd, width, height; 970 971 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 972 x = ri->ri_xorigin; 973 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 974 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 975 width = ri->ri_emuwidth; 976 height = ri->ri_font->fontheight*nrows; 977 pm3fb_bitblt(sc, x, ys, x, yd, width, height, 3); 978 } 979 } 980 981 static void 982 pm3fb_eraserows(void *cookie, int row, int nrows, long fillattr) 983 { 984 struct rasops_info *ri = cookie; 985 struct vcons_screen *scr = ri->ri_hw; 986 struct pm3fb_softc *sc = scr->scr_cookie; 987 int32_t x, y, width, height, fg, bg, ul; 988 989 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 990 x = ri->ri_xorigin; 991 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 992 width = ri->ri_emuwidth; 993 height = ri->ri_font->fontheight * nrows; 994 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 995 996 pm3fb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 997 } 998 } 999 1000 /* should be enough */ 1001 #define MODE_IS_VALID(m) (((m)->hdisplay < 2048)) 1002 1003 static void 1004 pm3_setup_i2c(struct pm3fb_softc *sc) 1005 { 1006 int i; 1007 1008 /* Fill in the i2c tag */ 1009 iic_tag_init(&sc->sc_i2c); 1010 sc->sc_i2c.ic_cookie = sc; 1011 sc->sc_i2c.ic_send_start = pm3fb_i2c_send_start; 1012 sc->sc_i2c.ic_send_stop = pm3fb_i2c_send_stop; 1013 sc->sc_i2c.ic_initiate_xfer = pm3fb_i2c_initiate_xfer; 1014 sc->sc_i2c.ic_read_byte = pm3fb_i2c_read_byte; 1015 sc->sc_i2c.ic_write_byte = pm3fb_i2c_write_byte; 1016 sc->sc_i2c.ic_exec = NULL; 1017 1018 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DISPLAY_DATA, 0); 1019 1020 /* zero out the EDID buffer */ 1021 memset(sc->sc_edid_data, 0, 128); 1022 1023 /* Some monitors don't respond first time */ 1024 i = 0; 1025 while (sc->sc_edid_data[1] == 0 && i < 10) { 1026 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, 128); 1027 i++; 1028 } 1029 1030 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_ei) != -1) { 1031 /* 1032 * Now pick a mode. 1033 */ 1034 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 1035 struct videomode *m = sc->sc_ei.edid_preferred_mode; 1036 if (MODE_IS_VALID(m)) { 1037 sc->sc_videomode = m; 1038 } else { 1039 aprint_error_dev(sc->sc_dev, 1040 "unable to use preferred mode\n"); 1041 } 1042 } 1043 /* 1044 * if we can't use the preferred mode go look for the 1045 * best one we can support 1046 */ 1047 if (sc->sc_videomode == NULL) { 1048 struct videomode *m = sc->sc_ei.edid_modes; 1049 1050 sort_modes(sc->sc_ei.edid_modes, 1051 &sc->sc_ei.edid_preferred_mode, 1052 sc->sc_ei.edid_nmodes); 1053 if (sc->sc_videomode == NULL) 1054 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 1055 if (MODE_IS_VALID(&m[n])) { 1056 sc->sc_videomode = &m[n]; 1057 break; 1058 } 1059 } 1060 } 1061 if (sc->sc_videomode == NULL) { 1062 /* no EDID data? */ 1063 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, 1064 sc->sc_height, 60); 1065 } 1066 if (sc->sc_videomode != NULL) { 1067 pm3fb_set_mode(sc, sc->sc_videomode); 1068 } 1069 } 1070 1071 /* I2C bitbanging */ 1072 static void pm3fb_i2cbb_set_bits(void *cookie, uint32_t bits) 1073 { 1074 struct pm3fb_softc *sc = cookie; 1075 uint32_t out; 1076 1077 out = bits << 2; /* bitmasks match the IN bits */ 1078 1079 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DISPLAY_DATA, out); 1080 delay(100); 1081 } 1082 1083 static void pm3fb_i2cbb_set_dir(void *cookie, uint32_t dir) 1084 { 1085 /* Nothing to do */ 1086 } 1087 1088 static uint32_t pm3fb_i2cbb_read(void *cookie) 1089 { 1090 struct pm3fb_softc *sc = cookie; 1091 uint32_t bits; 1092 1093 bits = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_DISPLAY_DATA); 1094 return bits; 1095 } 1096 1097 /* higher level I2C stuff */ 1098 static int 1099 pm3fb_i2c_send_start(void *cookie, int flags) 1100 { 1101 1102 return (i2c_bitbang_send_start(cookie, flags, &pm3fb_i2cbb_ops)); 1103 } 1104 1105 static int 1106 pm3fb_i2c_send_stop(void *cookie, int flags) 1107 { 1108 1109 return (i2c_bitbang_send_stop(cookie, flags, &pm3fb_i2cbb_ops)); 1110 } 1111 1112 static int 1113 pm3fb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1114 { 1115 1116 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1117 &pm3fb_i2cbb_ops)); 1118 } 1119 1120 static int 1121 pm3fb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1122 { 1123 1124 return (i2c_bitbang_read_byte(cookie, valp, flags, &pm3fb_i2cbb_ops)); 1125 } 1126 1127 static int 1128 pm3fb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1129 { 1130 return (i2c_bitbang_write_byte(cookie, val, flags, &pm3fb_i2cbb_ops)); 1131 } 1132 1133 static int 1134 pm3fb_set_pll(struct pm3fb_softc *sc, int freq) 1135 { 1136 uint8_t bf = 0, bpre = 0, bpost = 0; 1137 int count; 1138 unsigned long feedback, prescale, postscale, IntRef, VCO, out_freq, diff, VCOlow, VCOhigh, bdiff = 1000000; 1139 1140 freq *= 10; /* convert into 100Hz units */ 1141 1142 for (postscale = 0; postscale <= 5; postscale++) { 1143 /* 1144 * It is pointless going through the main loop if all values of 1145 * prescale produce an VCO outside the acceptable range 1146 */ 1147 prescale = 1; 1148 feedback = (prescale * (1UL << postscale) * freq) / (2 * PM3_EXT_CLOCK_FREQ); 1149 VCOlow = (2 * PM3_EXT_CLOCK_FREQ * feedback) / prescale; 1150 if (VCOlow > PM3_VCO_FREQ_MAX) 1151 continue; 1152 1153 prescale = 255; 1154 feedback = (prescale * (1UL << postscale) * freq) / (2 * PM3_EXT_CLOCK_FREQ); 1155 VCOhigh = (2 * PM3_EXT_CLOCK_FREQ * feedback) / prescale; 1156 if (VCOhigh < PM3_VCO_FREQ_MIN) 1157 continue; 1158 1159 for (prescale = 1; prescale <= 255; prescale++) { 1160 IntRef = PM3_EXT_CLOCK_FREQ / prescale; 1161 if (IntRef < PM3_INTREF_MIN || IntRef > PM3_INTREF_MAX) { 1162 if (IntRef > PM3_INTREF_MAX) { 1163 /* 1164 * Hopefully we will get into range as the prescale 1165 * value increases 1166 */ 1167 continue; 1168 } else { 1169 /* 1170 * already below minimum and it will only get worse 1171 * move to the next postscale value 1172 */ 1173 break; 1174 } 1175 } 1176 1177 feedback = (prescale * (1UL << postscale) * freq) / (2 * PM3_EXT_CLOCK_FREQ); 1178 1179 if (feedback > 255) { 1180 /* 1181 * prescale, feedbackscale & postscale registers 1182 * are only 8 bits wide 1183 */ 1184 break; 1185 } else if (feedback == 255) { 1186 count = 1; 1187 } else { 1188 count = 2; 1189 } 1190 1191 do { 1192 VCO = (2 * PM3_EXT_CLOCK_FREQ * feedback) / prescale; 1193 if (VCO >= PM3_VCO_FREQ_MIN && VCO <= PM3_VCO_FREQ_MAX) { 1194 out_freq = VCO / (1UL << postscale); 1195 diff = abs(out_freq - freq); 1196 if (diff < bdiff) { 1197 bdiff = diff; 1198 bf = feedback; 1199 bpre = prescale; 1200 bpost = postscale; 1201 if (diff == 0) 1202 goto out; 1203 } 1204 } 1205 feedback++; 1206 } while (--count >= 0); 1207 } 1208 } 1209 out: 1210 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_CLOCK0_PRE_SCALE, bpre); 1211 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_CLOCK0_FEEDBACK_SCALE, bf); 1212 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_CLOCK0_POST_SCALE, bpost); 1213 return 0; 1214 } 1215 1216 static void 1217 pm3fb_set_mode(struct pm3fb_softc *sc, const struct videomode *mode) 1218 { 1219 int t1, t2, t3, t4, stride; 1220 uint32_t vclk, tmp1; 1221 uint8_t sync = 0; 1222 1223 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_BYPASS_MASK, 0xffffffff); 1224 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_APERTURE1_CONTROL, 0x00000000); 1225 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_APERTURE2_CONTROL, 0x00000000); 1226 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FIFODISCONNECT, 0x00000007); 1227 1228 t1 = mode->hsync_start - mode->hdisplay; 1229 t2 = mode->vsync_start - mode->vdisplay; 1230 t3 = mode->hsync_end - mode->hsync_start; 1231 t4 = mode->vsync_end - mode->vsync_start; 1232 stride = (mode->hdisplay + 31) & ~31; 1233 1234 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_TOTAL, 1235 ((mode->htotal - 1) >> 4)); 1236 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_SYNC_END, 1237 (t1 + t3) >> 4); 1238 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_SYNC_START, 1239 (t1 >> 4)); 1240 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_BLANK_END, 1241 (mode->htotal - mode->hdisplay) >> 4); 1242 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_GATE_END, 1243 (mode->htotal - mode->hdisplay) >> 4); 1244 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCREEN_STRIDE, 1245 (stride >> 4)); 1246 1247 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1248 PM3_VERT_TOTAL, mode->vtotal - 1); 1249 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1250 PM3_VERT_SYNC_END, t2 + t4 - 1); 1251 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1252 PM3_VERT_SYNC_START, t2 - 1); 1253 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1254 PM3_VERT_BLANK_END, mode->vtotal - mode->vdisplay); 1255 1256 /*8bpp*/ 1257 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1258 PM3_BYAPERTURE1MODE, PM3_BYAPERTUREMODE_PIXELSIZE_8BIT); 1259 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1260 PM3_BYAPERTURE2MODE, PM3_BYAPERTUREMODE_PIXELSIZE_8BIT); 1261 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_VIDEO_CONTROL, 1262 (PM3_VC_ENABLE | PM3_VC_HSC_ACTIVE_HIGH | PM3_VC_VSC_ACTIVE_HIGH | PM3_VC_PIXELSIZE_8BIT)); 1263 1264 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_V_CLOCK_CTL); 1265 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_V_CLOCK_CTL, (vclk & 0xFFFFFFFC)); 1266 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCREEN_BASE, 0x0); 1267 1268 tmp1 = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_CHIP_CONFIG); 1269 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CHIP_CONFIG, tmp1 & 0xFFFFFFFD); 1270 1271 pm3fb_set_pll(sc, mode->dot_clock); 1272 1273 if (mode->flags & VID_PHSYNC) 1274 sync |= PM3_SC_HSYNC_ACTIVE_HIGH; 1275 if (mode->flags & VID_PVSYNC) 1276 sync |= PM3_SC_VSYNC_ACTIVE_HIGH; 1277 1278 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1279 PM3_RD_PM3_INDEX_CONTROL, PM3_INCREMENT_DISABLE); 1280 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_SYNC_CONTROL, sync); 1281 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_DAC_CONTROL, 0x00); 1282 1283 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_PIXEL_SIZE, PM3_DACPS_8BIT); 1284 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_COLOR_FORMAT, 1285 (PM3_CF_ORDER_BGR | PM3_CF_VISUAL_256_COLOR)); 1286 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_MISC_CONTROL, PM3_MC_DAC_SIZE_8BIT); 1287 1288 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FIFOCONTROL, 0x00000905); 1289 1290 sc->sc_width = mode->hdisplay; 1291 sc->sc_height = mode->vdisplay; 1292 sc->sc_depth = 8; 1293 sc->sc_stride = stride; 1294 aprint_normal_dev(sc->sc_dev, "pm3 using %d x %d in 8 bit, stride %d\n", 1295 sc->sc_width, sc->sc_height, stride); 1296 } 1297