1 /* $NetBSD: pm2reg.h,v 1.8 2012/09/12 12:07:04 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * register definitions for Permedia 2 graphics controllers 30 */ 31 32 33 #ifndef PM2_REG_H 34 #define PM2_REG_H 35 36 #define PM2_RESET 0x00000000 /* any write initiates a chip reset */ 37 #define PM2_RESET_BUSY 0x80000000 /* reset in progress */ 38 39 #define PM2_INPUT_FIFO_SPACE 0x00000018 40 #define PM2_OUTPUT_FIFO_WORDS 0x00000020 41 42 #define PM2_VCLKCTL 0x00000040 43 #define VCC_CLOCK_A 0x00000000 44 #define VCC_CLOCK_B 0x00000001 45 #define VCC_CLOCK_C 0x00000002 46 /* PCI clocks to wait between RAMDAC accesses */ 47 #define VCC_RAMDAC_WAIT_MASK 0x000003fc 48 49 #define PM2_APERTURE1_CONTROL 0x00000050 50 #define PM2_APERTURE2_CONTROL 0x00000058 51 #define PM2_AP_BYTESWAP 0x00000001 52 #define PM2_AP_HALFWORDSWAP 0x00000002 53 #define PM2_AP_PACKED16_EN 0x00000008 54 #define PM2_AP_PACKED16_READ_B 0x00000010 /* Buffer A otherwise */ 55 #define PM2_AP_PACKED16_WRITE_B 0x00000020 /* A otherwise */ 56 #define PM2_AP_PACKED16_WRT_DBL 0x00000040 57 #define PM2_AP_PACKED16_R31 0x00000080 /* read buffer selected by 58 * visibility bit in memory 59 */ 60 #define PM2_AP_SVGA 0x00000100 61 #define PM2_AP_ROM 0x00000200 62 63 #define PM2_BYPASS_MASK 0x00001100 64 #define PM2_FB_WRITE_MASK 0x00001140 65 66 #define PM2_OUTPUT_FIFO 0x00002000 67 68 #define PM2_SCREEN_BASE 0x00003000 /* in 64bit units */ 69 #define PM2_SCREEN_STRIDE 0x00003008 /* in 64bit units */ 70 #define PM2_HTOTAL 0x00003010 71 #define PM2_HGATE_END 0x00003018 72 #define PM2_HBLANK_END 0x00003020 73 #define PM2_HSYNC_START 0x00003028 74 #define PM2_HSYNC_END 0x00003030 75 #define PM2_VTOTAL 0x00003038 76 #define PM2_VBLANK_END 0x00003040 77 #define PM2_VSYNC_START 0x00003048 78 #define PM2_VSYNC_END 0x00003050 79 #define PM2_VIDEO_CONTROL 0x00003058 80 #define PM2_VC_VIDEO_ENABLE 0x00000001 81 #define PM2_VC_BLANK_ACR_LOW 0x00000002 82 #define PM2_VC_LINE_DOUBLE 0x00000004 83 #define PM2_VC_HSYNC_FORCE_H 0x00000000 84 #define PM2_VC_HSYNC_ACT_HIGH 0x00000008 85 #define PM2_VC_HSYNC_FORCE_L 0x00000010 86 #define PM2_VC_HSYNC_ACT_LOW 0x00000018 87 #define PM2_VC_VSYNC_FORCE_H 0x00000000 88 #define PM2_VC_VSYNC_ACT_HIGH 0x00000020 89 #define PM2_VC_VSYNC_FORCE_L 0x00000040 90 #define PM2_VC_VSYNC_ACT_LOW 0x00000060 91 #define PM2_VC_BP_BASE_PENDING 0x00000080 92 #define PM2_VC_RE_BASE_PENDING 0x00000100 93 #define PM2_VC_SWAP_SYNC_BLANK 0x00000000 94 #define PM2_VC_SWAP_FREERUNNING 0x00000200 95 #define PM2_VC_SWAP_LIMIT_FR 0x00000400 96 #define PM2_VC_STEREO_ENABLE 0x00000800 97 #define PM2_VC_RIGHT_EYE_ACT_L 0x00001000 98 #define PM2_VC_DISP_RIGHT_FRAME 0x00002000 /* RO, left otherwise */ 99 #define PM2_VC_BP_RIGHT_PENDING 0x00004000 100 #define PM2_VC_RE_RIGHT_PENDING 0x00008000 101 #define PM2_VC_RAMDAC_64BIT 0x00010000 /* 32bit otherwise */ 102 103 #define PM2_DISPLAY_DATA 0x00003068 104 #define PM2_DD_SDA_IN 0x00000001 105 #define PM2_DD_SCL_IN 0x00000002 106 #define PM2_DD_SDA_OUT 0x00000004 107 #define PM2_DD_SCL_OUT 0x00000008 108 #define PM2_DD_LATCHED_DATA 0x00000010 109 #define PM2_DD_DATA_VALID 0x00000020 /* clear by 1 */ 110 #define PM2_DD_START 0x00000040 /* START detected */ 111 #define PM2_DD_STOP 0x00000080 /* STOP detected */ 112 #define PM2_DD_INSERT_WAITS 0x00000100 113 #define PM2_DD_USE_MONID 0x00000200 /* DDC2 otherwise */ 114 #define PM2_DD_MONID_IN_MASK 0x00001c00 115 #define PM2_DD_MONID_OUT_MASK 0x0000e000 116 117 /* RAMDAC */ 118 #define PM2_DAC_PAL_WRITE_IDX 0x00004000 119 #define PM2_DAC_DATA 0x00004008 120 #define PM2_DAC_MASK 0x00004010 121 #define PM2_DAC_PAL_READ_IDX 0x00004018 122 /* these are different on PM2V: */ 123 #define PM2_DAC_CURSOR_PAL 0x00004020 124 #define PM2_DAC_CURSOR_DATA 0x00004028 125 /* here we go: */ 126 #define PM2V_DAC_INDEX_LOW 0x00004020 127 #define PM2V_DAC_INDEX_HIGH 0x00004028 128 #define PM2V_DAC_INDEX_DATA 0x00004030 129 #define PM2V_DAC_INDEX_CONTROL 0x00004038 130 131 #define PM2_DAC_INDEX_DATA 0x00004050 132 #define PM2_DAC_CURSOR_RAM 0x00004058 133 #define PM2_DAC_CURSOR_X_LOW 0x00004060 134 #define PM2_DAC_CURSOR_X_HIGH 0x00004068 135 #define PM2_DAC_CURSOR_Y_LOW 0x00004070 136 #define PM2_DAC_CURSOR_Y_HIGH 0x00004078 137 138 /* RAMDAC registers ( through INDEX_DATA */ 139 #define PM2_DAC_COLOR_MODE 0x18 140 #define CM_PALETTE 0x00 141 #define CM_RGB332 0x01 142 #define CM_RGB232OFFSET 0x02 143 #define CM_RGBA2321 0x03 144 #define CM_RGBA5551 0x04 145 #define CM_RGBA4444 0x05 146 #define CM_RGB565 0x06 147 #define CM_RGBA8888 0x08 148 #define CM_RGB888 0x09 149 #define CM_GUI_DISABLE 0x10 150 #define CM_RGB 0x20 /* BGR otherwise */ 151 #define CM_TRUECOLOR 0x80 /* use palette for gamma correction */ 152 153 #define PM2_DAC_MISC_CONTROL 0x1e 154 #define MC_POWERDOWN 0x01 155 #define MC_PALETTE_8BIT 0x02 /* 6bit otherwise */ 156 #define MC_HSYNC_INV 0x04 157 #define MC_VSYNC_INV 0x08 158 #define MC_SYNCONGREEN 0x10 159 #define PM2_DAC_PIXELCLKA_M 0x20 160 #define PM2_DAC_PIXELCLKA_N 0x21 161 #define PM2_DAC_PIXELCLKA_P 0x22 162 #define PCLK_ENABLE 0x08 163 #define PM2_DAC_PIXELCLKB_M 0x23 164 #define PM2_DAC_PIXELCLKB_N 0x24 165 #define PM2_DAC_PIXELCLKB_P 0x25 166 #define PM2_DAC_PIXELCLKC_M 0x26 167 #define PM2_DAC_PIXELCLKC_N 0x27 168 #define PM2_DAC_PIXELCLKC_P 0x28 169 #define PM2_DAC_PIXELCLK_STATUS 0x29 170 #define PCLK_LOCKED 0x10 171 #define PM2_DAC_MEMCLK_M 0x30 172 #define PM2_DAC_MEMCLK_N 0x31 173 #define PM2_DAC_MEMCLK_P 0x32 174 #define PM2_DAC_MEMCLK_STATUS 0x33 175 176 /* PM2V RAMDAC */ 177 #define PM2V_DAC_MISC_CONTROL 0x000 178 #define PM2V_DAC_8BIT 0x01 /* 6bit otherwise */ 179 #define PM2V_DAC_BYPASS_CLUT 0x08 /* ??? guess from xorg */ 180 #define PM2V_DAC_8_24_OVERLAY 0x10 /* ??? guess from xorg */ 181 #define PM2V_DAC_SYNC_CONTROL 0x001 182 #define PM2V_DAC_HSYNC_INV 0x01 183 #define PM2V_DAC_VSYNC_INV 0x08 184 #define PM2V_DAC_CONTROL 0x002 185 #define PM2V_DAC_PIXEL_SIZE 0x003 186 #define PM2V_PS_8BIT 0x00 187 #define PM2V_PS_16BIT 0x01 188 #define PM2V_PS_32BIT 0x02 189 #define PM2V_PS_24BIT 0x04 190 #define PM2V_DAC_COLOR_FORMAT 0x004 191 #define PM2V_DAC_PALETTE 0x2e 192 #define PM2V_DAC_RGB555 0x61 193 #define PM2V_DAC_RGB565 0x70 194 #define PM2V_DAC_RGB888 0x60 195 #define PM2V_DAC_RGBA8888 0x20 196 197 #define PM2V_DAC_CHECK_CONTROL 0x018 198 #define PM2V_DAC_CLOCK_CONTROL 0x200 199 #define PM2V_DAC_CLOCK_A_M 0x201 200 #define PM2V_DAC_CLOCK_A_N 0x202 201 #define PM2V_DAC_CLOCK_A_P 0x203 202 #define PM2V_DAC_CLOCK_B_M 0x204 203 #define PM2V_DAC_CLOCK_B_N 0x205 204 #define PM2V_DAC_CLOCK_B_P 0x206 205 #define PM2V_DAC_MCLK_CONTROL 0x20D 206 #define PM2V_DAC_MCLK_M 0x20E 207 #define PM2V_DAC_MCLK_N 0x20F 208 #define PM2V_DAC_MCLK_P 0x210 209 210 /* drawing engine */ 211 #define PM2_RE_STARTXDOM 0x00008000 212 #define PM2_RE_DXDOM 0x00008008 213 #define PM2_RE_STARTXSUB 0x00008010 214 #define PM2_RE_STARTY 0x00008020 215 #define PM2_RE_DY 0x00008028 216 #define PM2_RE_COUNT 0x00008030 217 #define PM2_RE_BITMASK 0x00008068 /* for colour expansion */ 218 #define PM2_RE_COLOUR 0x000087f0 219 #define PM2_RE_CONFIG 0x00008d90 220 #define PM2RECFG_READ_SRC 0x00000001 221 #define PM2RECFG_READ_DST 0x00000002 222 #define PM2RECFG_PACKED 0x00000004 223 #define PM2RECFG_WRITE_EN 0x00000008 224 #define PM2RECFG_DDA_EN 0x00000010 225 #define PM2RECFG_ROP_EN 0x00000020 226 #define PM2RECFG_ROP_MASK 0x000003c0 227 #define PM2RECFG_ROP_SHIFT 6 228 229 #define PM2_RE_CONST_COLOUR 0x000087e8 230 #define PM2_RE_BUFFER_OFFSET 0x00008a90 /* distance between src and dst */ 231 #define PM2_RE_SOURCE_BASE 0x00008d80 /* write after windowbase */ 232 #define PM2_RE_SOURCE_DELTA 0x00008d88 /* offset in coordinates */ 233 #define PM2_RE_SOURCE_OFFSET 0x00008a88 /* same in pixels */ 234 #define PM2_RE_WINDOW_BASE 0x00008ab0 235 #define PM2_RE_WINDOW_ORIGIN 0x000081c8 236 #define PM2_RE_WRITE_MODE 0x00008ab8 237 #define PM2WM_WRITE_EN 0x00000001 238 #define PM2WM_TO_HOST 0x00000008 239 #define PM2_RE_PIXEL_SIZE 0x00008ad0 240 #define PM2PS_8BIT 0x00000000 241 #define PM2PS_16BIT 0x00000001 242 #define PM2PS_32BIT 0x00000002 243 #define PM2PS_24BIT 0x00000004 244 245 #define PM2_RE_MODE 0x000080a0 246 #define PM2RM_MASK_MIRROR 0x00000001 /* mask is right-to-left */ 247 #define PM2RM_MASK_INVERT 0x00000002 248 #define PM2RM_MASK_OPAQUE 0x00000040 /* BG in TEXEL0 */ 249 #define PM2RM_MASK_SWAP 0x00000180 250 #define PM2RM_MASK_PAD 0x00000200 /* new line new mask */ 251 #define PM2RM_MASK_OFFSET 0x00007c00 252 #define PM2RM_HOST_SWAP 0x00018000 253 #define PM2RM_LIMITS_EN 0x00040000 254 #define PM2RM_MASK_REL_X 0x00080000 255 256 #define PM2_RE_RECT_START 0x000080d0 257 #define PM2_RE_RECT_SIZE 0x000080d8 258 #define PM2_RE_RENDER 0x00008038 /* write starts command */ 259 #define PM2RE_STIPPLE 0x00000001 260 #define PM2RE_FASTFILL 0x00000008 261 #define PM2RE_LINE 0x00000000 262 #define PM2RE_TRAPEZOID 0x00000040 263 #define PM2RE_POINT 0x00000080 264 #define PM2RE_RECTANGLE 0x000000c0 265 #define PM2RE_SYNC_ON_MASK 0x00000800 /* wait for write to bitmask 266 register */ 267 #define PM2RE_SYNC_ON_HOST 0x00001000 /* wait for host data */ 268 #define PM2RE_TEXTURE_EN 0x00002000 269 #define PM2RE_INC_X 0x00200000 /* drawing direction */ 270 #define PM2RE_INC_Y 0x00400000 271 #define PM2_RE_TEXEL0 0x00008600 /* background colour */ 272 #define PM2_RE_STATUS 0x00000068 273 #define PM2ST_BUSY 0x80000000 274 #define PM2_RE_SYNC 0x00008c40 275 #define PM2_RE_FILTER_MODE 0x00008c00 276 #define PM2FLT_PASS_SYNC 0x00000400 277 #define PM2_RE_DDA_MODE 0x000087e0 278 #define PM2DDA_ENABLE 0x00000001 279 #define PM2DDA_GOURAUD 0x00000002 /* flat otherwise */ 280 #define PM2_RE_BLOCK_COLOUR 0x00008ac8 281 #define PM2_RE_STIPPLE_MODE 0x000081a0 282 #define PM2ST_ENABLE 0x00000001 283 #define PM2ST_XOFFSET_MASK 0x00000380 284 #define PM2ST_YOFFSET_MASK 0x00007000 285 #define PM2ST_INVERT 0x00020000 286 #define PM2ST_MIRROR_X 0x00040000 287 #define PM2ST_MIRROR_Y 0x00080000 288 #define PM2ST_OPAQUE 0x00100000 289 #define PM2_HW_WRITEMASK 0x00008ac0 290 #define PM2_SW_WRITEMASK 0x00008820 291 #define PM2_FB_READMODE 0x00008a80 292 #define PM2FB_PP0_MASK 0x00000007 293 #define PM2FB_PP1_MASK 0x00000038 294 #define PM2FB_PP2_MASK 0x000001c0 295 #define PM2FB_READ_SRC 0x00000200 296 #define PM2FB_READ_DST 0x00000400 297 #define PM2FB_FBCOLOR 0x00008000 /* for uploads */ 298 #define PM2FB_ORIGIN_BL 0x00010000 /* window origin, TL otherwise */ 299 #define PM2FB_PATCH_EN 0x00020000 300 #define PM2FB_PACKED 0x00040000 301 #define PM2FB_OFFSET_M 0x00380000 302 #define PM2FB_PM_PATCH 0x00000000 303 #define PM2FB_PM_SUB 0x02000000 304 #define PM2FB_PM_SUBP 0x04000000 305 306 #define PM2_RE_SCISSOR_MODE 0x00008180 307 #define PM2SC_USER_EN 0x00000001 /* from scissor reg */ 308 #define PM2SC_SCREEN_EN 0x00000002 /* screensize reg */ 309 #define PM2_RE_SCREENSIZE 0x00008198 310 #define PM2_RE_SCISSOR_MINYX 0x00008188 311 #define PM2_RE_SCISSOR_MAXYX 0x00008190 312 #define PM2_RE_TEXMAP_FORMAT 0x00008588 313 #define PM2_RE_DITHER_MODE 0x00008818 314 #define PM2_RE_ALPHA_MODE 0x00008810 315 #define PM2_RE_TEX_COLOUR_MODE 0x00008680 316 #define PM2_RE_TEX_READ_MODE 0x00008670 317 #define PM2_RE_TEX_LUT_MODE 0x00008678 318 #define PM2_RE_TEX_ADDRESS_MODE 0x00008380 319 #define PM2_RE_YUV_MODE 0x00008f00 320 #define PM2_RE_DEPTH_MODE 0x000089a0 321 #define PM2_RE_DEPTH 0x000089a8 322 #define PM2_RE_STENCIL_MODE 0x00008988 323 #define PM2_RE_ROP_MODE 0x00008828 324 #define PM2_RE_PACKEDDATA_LIMIT 0x00008150 325 #define PM2_RE_DATA 0x00008aa0 /* pixel data */ 326 #define PM2_RE_SOURCEDATA 0x00008aa8 /* raw data */ 327 328 329 #endif /* PM2_REG_H */ 330