1 /* $NetBSD: piixpmreg.h,v 1.7 2014/03/18 18:20:42 riastradh Exp $ */ 2 /* $OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DEV_PCI_PIIXREG_H_ 21 #define _DEV_PCI_PIIXREG_H_ 22 23 /* 24 * Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions. 25 */ 26 27 /* 28 * Power management registers. 29 */ 30 31 /* PCI configuration registers */ 32 #define PIIX_PM_BASE 0x40 /* Power management base address */ 33 #define PIIX_PM_BASE_CSB5_RESET 0x10 /* CSB5 PM reset */ 34 #define PIIX_DEVACTA 0x54 /* Device activity A (function 3) */ 35 #define PIIX_DEVACTB 0x58 /* Device activity B (function 3) */ 36 #define PIIX_PMREGMISC 0x80 /* Misc. Power management */ 37 #define PIIX_SMB_BASE 0x90 /* SMBus base address */ 38 #define PIIX_SMB_HOSTC 0xd0 /* SMBus host configuration */ 39 #define PIIX_SMB_HOSTC_HSTEN (1 << 16) /* enable host controller */ 40 #define PIIX_SMB_HOSTC_SMI (0 << 17) /* SMI */ 41 #define PIIX_SMB_HOSTC_IRQ (4 << 17) /* IRQ */ 42 #define PIIX_SMB_HOSTC_INTMASK (7 << 17) 43 44 /* SMBus I/O registers */ 45 #define PIIX_SMB_HS 0x00 /* host status */ 46 #define PIIX_SMB_HS_BUSY (1 << 0) /* running a command */ 47 #define PIIX_SMB_HS_INTR (1 << 1) /* command completed */ 48 #define PIIX_SMB_HS_DEVERR (1 << 2) /* command error */ 49 #define PIIX_SMB_HS_BUSERR (1 << 3) /* transaction collision */ 50 #define PIIX_SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 51 #define PIIX_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED" 52 #define PIIX_SMB_HC 0x02 /* host control */ 53 #define PIIX_SMB_HC_INTREN (1 << 0) /* enable interrupts */ 54 #define PIIX_SMB_HC_KILL (1 << 1) /* kill current transaction */ 55 #define PIIX_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 56 #define PIIX_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 57 #define PIIX_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 58 #define PIIX_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 59 #define PIIX_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 60 #define PIIX_SMB_HC_START (1 << 6) /* start transaction */ 61 #define PIIX_SMB_HCMD 0x03 /* host command */ 62 #define PIIX_SMB_TXSLVA 0x04 /* transmit slave address */ 63 #define PIIX_SMB_TXSLVA_READ (1 << 0) /* read direction */ 64 #define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 65 #define PIIX_SMB_HD0 0x05 /* host data 0 */ 66 #define PIIX_SMB_HD1 0x06 /* host data 1 */ 67 #define PIIX_SMB_HBDB 0x07 /* host block data byte */ 68 #define PIIX_SMB_SC 0x08 /* slave control */ 69 #define PIIX_SMB_SC_ALERTEN (1 << 3) /* enable SMBALERT# */ 70 71 /* Power management I/O registers */ 72 #define PIIX_PM_PMTMR 0x08 /* power management timer */ 73 74 /* Misc */ 75 #define PIIX_PM_SIZE 0x38 /* Power management I/O space size */ 76 #define PIIX_SMB_SIZE 0x10 /* SMBus I/O space size */ 77 78 #define PIIXPM_INDIRECTIO_BASE 0xcd6 79 #define PIIXPM_INDIRECTIO_SIZE 2 80 #define PIIXPM_INDIRECTIO_INDEX 0 81 #define PIIXPM_INDIRECTIO_DATA 1 82 83 #define SB800_PM_SMBUS0EN_LO 0x2c 84 #define SB800_PM_SMBUS0EN_HI 0x2d 85 #define SB800_PM_SMBUS0SEL 0x2e 86 #define SB800_PM_SMBUS0SELEN 0x2f 87 88 #define SB800_PM_SMBUS0EN_ENABLE 0x0001 89 #define SB800_PM_SMBUS0EN_BADDR 0xffe0 90 91 #endif /* !_DEV_PCI_PIIXREG_H_ */ 92