xref: /netbsd-src/sys/dev/pci/piixide.c (revision c2f76ff004a2cb67efe5b12d97bd3ef7fe89e18d)
1 /*	$NetBSD: piixide.c,v 1.56 2010/11/05 18:07:24 jakllsch Exp $	*/
2 
3 /*
4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.56 2010/11/05 18:07:24 jakllsch Exp $");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 
33 #include <dev/pci/pcivar.h>
34 #include <dev/pci/pcidevs.h>
35 #include <dev/pci/pciidereg.h>
36 #include <dev/pci/pciidevar.h>
37 #include <dev/pci/pciide_piix_reg.h>
38 
39 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *);
40 static void piix_setup_channel(struct ata_channel *);
41 static void piix3_4_setup_channel(struct ata_channel *);
42 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
43 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
44 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
45 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *);
46 static int piix_dma_init(void *, int, int, void *, size_t, int);
47 
48 static bool piixide_resume(device_t, const pmf_qual_t *);
49 static bool piixide_suspend(device_t, const pmf_qual_t *);
50 static int  piixide_match(device_t, cfdata_t, void *);
51 static void piixide_attach(device_t, device_t, void *);
52 
53 static const struct pciide_product_desc pciide_intel_products[] =  {
54 	{ PCI_PRODUCT_INTEL_82092AA,
55 	  0,
56 	  "Intel 82092AA IDE controller",
57 	  default_chip_map,
58 	},
59 	{ PCI_PRODUCT_INTEL_82371FB_IDE,
60 	  0,
61 	  "Intel 82371FB IDE controller (PIIX)",
62 	  piix_chip_map,
63 	},
64 	{ PCI_PRODUCT_INTEL_82371SB_IDE,
65 	  0,
66 	  "Intel 82371SB IDE Interface (PIIX3)",
67 	  piix_chip_map,
68 	},
69 	{ PCI_PRODUCT_INTEL_82371AB_IDE,
70 	  0,
71 	  "Intel 82371AB IDE controller (PIIX4)",
72 	  piix_chip_map,
73 	},
74 	{ PCI_PRODUCT_INTEL_82440MX_IDE,
75 	  0,
76 	  "Intel 82440MX IDE controller",
77 	  piix_chip_map
78 	},
79 	{ PCI_PRODUCT_INTEL_82801AA_IDE,
80 	  0,
81 	  "Intel 82801AA IDE Controller (ICH)",
82 	  piix_chip_map,
83 	},
84 	{ PCI_PRODUCT_INTEL_82801AB_IDE,
85 	  0,
86 	  "Intel 82801AB IDE Controller (ICH0)",
87 	  piix_chip_map,
88 	},
89 	{ PCI_PRODUCT_INTEL_82801BA_IDE,
90 	  0,
91 	  "Intel 82801BA IDE Controller (ICH2)",
92 	  piix_chip_map,
93 	},
94 	{ PCI_PRODUCT_INTEL_82801BAM_IDE,
95 	  0,
96 	  "Intel 82801BAM IDE Controller (ICH2-M)",
97 	  piix_chip_map,
98 	},
99 	{ PCI_PRODUCT_INTEL_82801CA_IDE_1,
100 	  0,
101 	  "Intel 82801CA IDE Controller (ICH3)",
102 	  piix_chip_map,
103 	},
104 	{ PCI_PRODUCT_INTEL_82801CA_IDE_2,
105 	  0,
106 	  "Intel 82801CA IDE Controller (ICH3)",
107 	  piix_chip_map,
108 	},
109 	{ PCI_PRODUCT_INTEL_82801DB_IDE,
110 	  0,
111 	  "Intel 82801DB IDE Controller (ICH4)",
112 	  piix_chip_map,
113 	},
114 	{ PCI_PRODUCT_INTEL_82801DBM_IDE,
115 	  0,
116 	  "Intel 82801DBM IDE Controller (ICH4-M)",
117 	  piix_chip_map,
118 	},
119 	{ PCI_PRODUCT_INTEL_82801EB_IDE,
120 	  0,
121 	  "Intel 82801EB IDE Controller (ICH5)",
122 	  piix_chip_map,
123 	},
124 	{ PCI_PRODUCT_INTEL_82801EB_SATA,
125 	  0,
126 	  "Intel 82801EB Serial ATA Controller",
127 	  piixsata_chip_map,
128 	},
129 	{ PCI_PRODUCT_INTEL_82801ER_SATA,
130 	  0,
131 	  "Intel 82801ER Serial ATA/Raid Controller",
132 	  piixsata_chip_map,
133 	},
134 	{ PCI_PRODUCT_INTEL_6300ESB_IDE,
135 	  0,
136 	  "Intel 6300ESB IDE Controller (ICH5)",
137 	  piix_chip_map,
138 	},
139 	{ PCI_PRODUCT_INTEL_6300ESB_SATA,
140 	  0,
141 	  "Intel 6300ESB Serial ATA Controller",
142 	  piixsata_chip_map,
143 	},
144 	{ PCI_PRODUCT_INTEL_6300ESB_RAID,
145 	  0,
146 	  "Intel 6300ESB Serial ATA/RAID Controller",
147 	  piixsata_chip_map,
148 	},
149 	{ PCI_PRODUCT_INTEL_82801FB_IDE,
150 	  0,
151 	  "Intel 82801FB IDE Controller (ICH6)",
152 	  piix_chip_map,
153 	},
154 	{ PCI_PRODUCT_INTEL_82801FB_SATA,
155 	  0,
156 	  "Intel 82801FB Serial ATA/Raid Controller",
157 	  piixsata_chip_map,
158 	},
159 	{ PCI_PRODUCT_INTEL_82801FR_SATA,
160 	  0,
161 	  "Intel 82801FR Serial ATA/Raid Controller",
162 	  piixsata_chip_map,
163 	},
164 	{ PCI_PRODUCT_INTEL_82801FBM_SATA,
165 	  0,
166 	  "Intel 82801FBM Serial ATA Controller (ICH6)",
167 	  piixsata_chip_map,
168 	},
169 	{ PCI_PRODUCT_INTEL_82801G_IDE,
170 	  0,
171 	  "Intel 82801GB/GR IDE Controller (ICH7)",
172 	  piix_chip_map,
173 	},
174 	{ PCI_PRODUCT_INTEL_82801G_SATA,
175 	  0,
176 	  "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)",
177 	  piixsata_chip_map,
178 	},
179 	{ PCI_PRODUCT_INTEL_82801GBM_SATA,
180 	  0,
181 	  "Intel 82801GBM/GHM Serial ATA Controller (ICH7)",
182 	  piixsata_chip_map,
183 	},
184 	{ PCI_PRODUCT_INTEL_82801H_SATA_1,
185 	  0,
186 	  "Intel 82801H Serial ATA Controller (ICH8)",
187 	  piixsata_chip_map,
188 	},
189 	{ PCI_PRODUCT_INTEL_82801H_SATA_RAID,
190 	  0,
191 	  "Intel 82801H Serial ATA RAID Controller (ICH8)",
192 	  piixsata_chip_map,
193 	},
194 	{ PCI_PRODUCT_INTEL_82801H_SATA_2,
195 	  0,
196 	  "Intel 82801H Serial ATA Controller (ICH8)",
197 	  piixsata_chip_map,
198 	},
199 	{ PCI_PRODUCT_INTEL_82801HBM_IDE,
200 	  0,
201 	  "Intel 82801HBM IDE Controller (ICH8M)",
202 	  piix_chip_map,
203 	},
204 	{ PCI_PRODUCT_INTEL_82801HBM_SATA_1,
205 	  0,
206 	  "Intel 82801HBM Serial ATA Controller (ICH8M)",
207 	  piixsata_chip_map,
208 	},
209 	{ PCI_PRODUCT_INTEL_82801HBM_SATA_2,
210 	  0,
211 	  "Intel 82801HBM Serial ATA Controller (ICH8M)",
212 	  piixsata_chip_map,
213 	},
214 	{ PCI_PRODUCT_INTEL_82801HEM_SATA,
215 	  0,
216 	  "Intel 82801HEM Serial ATA Controller (ICH8M)",
217 	  piixsata_chip_map,
218 	},
219 	{ PCI_PRODUCT_INTEL_63XXESB_IDE,
220 	  0,
221 	  "Intel 631xESB/632xESB IDE Controller",
222 	  piix_chip_map,
223 	},
224 	{ PCI_PRODUCT_INTEL_82801I_SATA_1,
225 	  0,
226 	  "Intel 82801I Serial ATA Controller (ICH9)",
227 	  piixsata_chip_map,
228 	},
229 	{ PCI_PRODUCT_INTEL_82801I_SATA_2,
230 	  0,
231 	  "Intel 82801I Serial ATA Controller (ICH9)",
232 	  piixsata_chip_map,
233 	},
234 	{ PCI_PRODUCT_INTEL_82801I_SATA_3,
235 	  0,
236 	  "Intel 82801I Serial ATA Controller (ICH9)",
237 	  piixsata_chip_map,
238 	},
239 	{ PCI_PRODUCT_INTEL_82801I_SATA_4,
240 	  0,
241 	  "Intel 82801I Mobile Serial ATA Controller (ICH9)",
242 	  piixsata_chip_map,
243 	},
244 	{ PCI_PRODUCT_INTEL_82801I_SATA_5,
245 	  0,
246 	  "Intel 82801I Mobile Serial ATA Controller (ICH9)",
247 	  piixsata_chip_map,
248 	},
249 	{ PCI_PRODUCT_INTEL_82801I_SATA_6,
250 	  0,
251 	  "Intel 82801I Mobile Serial ATA Controller (ICH9)",
252 	  piixsata_chip_map,
253 	},
254 	{ PCI_PRODUCT_INTEL_82801I_SATA_7,
255 	  0,
256 	  "Intel 82801I Mobile Serial ATA Controller (ICH9)",
257 	  piixsata_chip_map,
258 	},
259 	{ PCI_PRODUCT_INTEL_63XXESB_SATA,
260 	  0,
261 	  "Intel 631xESB/632xESB Serial ATA Controller",
262 	  piixsata_chip_map,
263 	},
264 	{ PCI_PRODUCT_INTEL_82801JD_SATA_IDE2,
265 	  0,
266 	  "Intel 82801JD Serial ATA Controller (ICH10)",
267 	  piixsata_chip_map,
268 	},
269 	{ PCI_PRODUCT_INTEL_82801JI_SATA_IDE2,
270 	  0,
271 	  "Intel 82801JI Serial ATA Controller (ICH10)",
272 	  piixsata_chip_map,
273 	},
274 	{ PCI_PRODUCT_INTEL_82801JD_SATA_IDE,
275 	  0,
276 	  "Intel 82801JD Serial ATA Controller (ICH10)",
277 	  piixsata_chip_map,
278 	},
279 	{ PCI_PRODUCT_INTEL_82801JI_SATA_IDE,
280 	  0,
281 	  "Intel 82801JI Serial ATA Controller (ICH10)",
282 	  piixsata_chip_map,
283 	},
284 	{
285 	  PCI_PRODUCT_INTEL_82965PM_IDE,
286 	  0,
287 	  "Intel 82965PM IDE controller",
288 	  piixsata_chip_map,
289 	},
290 	{
291 	  PCI_PRODUCT_INTEL_3400_SATA_1,
292 	  0,
293 	  "Intel 3400 Serial ATA Controller",
294 	  piixsata_chip_map,
295 	},
296 	{
297 	  PCI_PRODUCT_INTEL_3400_SATA_1,
298 	  0,
299 	  "Intel 3400 Serial ATA Controller",
300 	  piixsata_chip_map,
301 	},
302 	{
303 	  PCI_PRODUCT_INTEL_3400_SATA_2,
304 	  0,
305 	  "Intel 3400 Serial ATA Controller",
306 	  piixsata_chip_map,
307 	},
308 	{
309 	  PCI_PRODUCT_INTEL_3400_SATA_3,
310 	  0,
311 	  "Intel 3400 Serial ATA Controller",
312 	  piixsata_chip_map,
313 	},
314 	{
315 	  PCI_PRODUCT_INTEL_3400_SATA_4,
316 	  0,
317 	  "Intel 3400 Serial ATA Controller",
318 	  piixsata_chip_map,
319 	},
320 	{
321 	  PCI_PRODUCT_INTEL_3400_SATA_5,
322 	  0,
323 	  "Intel 3400 Serial ATA Controller",
324 	  piixsata_chip_map,
325 	},
326 	{
327 	  PCI_PRODUCT_INTEL_3400_SATA_6,
328 	  0,
329 	  "Intel 3400 Serial ATA Controller",
330 	  piixsata_chip_map,
331 	},
332 	{ 0,
333 	  0,
334 	  NULL,
335 	  NULL
336 	}
337 };
338 
339 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc),
340     piixide_match, piixide_attach, NULL, NULL);
341 
342 static int
343 piixide_match(device_t parent, cfdata_t match, void *aux)
344 {
345 	struct pci_attach_args *pa = aux;
346 
347 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
348 		if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
349 			return (2);
350 	}
351 	return (0);
352 }
353 
354 static void
355 piixide_attach(device_t parent, device_t self, void *aux)
356 {
357 	struct pci_attach_args *pa = aux;
358 	struct pciide_softc *sc = device_private(self);
359 
360 	sc->sc_wdcdev.sc_atac.atac_dev = self;
361 
362 	pciide_common_attach(sc, pa,
363 	    pciide_lookup_product(pa->pa_id, pciide_intel_products));
364 
365 	if (!pmf_device_register(self, piixide_suspend, piixide_resume))
366 		aprint_error_dev(self, "couldn't establish power handler\n");
367 }
368 
369 static bool
370 piixide_resume(device_t dv, const pmf_qual_t *qual)
371 {
372 	struct pciide_softc *sc = device_private(dv);
373 
374 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
375 	    sc->sc_pm_reg[0]);
376 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG,
377 	    sc->sc_pm_reg[1]);
378 
379 	return true;
380 }
381 
382 static bool
383 piixide_suspend(device_t dv, const pmf_qual_t *qual)
384 {
385 	struct pciide_softc *sc = device_private(dv);
386 
387 	sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag,
388 	    PIIX_IDETIM);
389 	sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag,
390 	    PIIX_UDMAREG);
391 
392 	return true;
393 }
394 
395 static void
396 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
397 {
398 	struct pciide_channel *cp;
399 	int channel;
400 	u_int32_t idetim;
401 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
402 
403 	if (pciide_chipen(sc, pa) == 0)
404 		return;
405 
406 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
407 	    "bus-master DMA support present");
408 	pciide_mapreg_dma(sc, pa);
409 	aprint_verbose("\n");
410 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
411 	if (sc->sc_dma_ok) {
412 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
413 		sc->sc_wdcdev.irqack = pciide_irqack;
414 		/* Do all revisions require DMA alignment workaround? */
415 		sc->sc_wdcdev.dma_init = piix_dma_init;
416 		switch(sc->sc_pp->ide_product) {
417 		case PCI_PRODUCT_INTEL_82371AB_IDE:
418 		case PCI_PRODUCT_INTEL_82440MX_IDE:
419 		case PCI_PRODUCT_INTEL_82801AA_IDE:
420 		case PCI_PRODUCT_INTEL_82801AB_IDE:
421 		case PCI_PRODUCT_INTEL_82801BA_IDE:
422 		case PCI_PRODUCT_INTEL_82801BAM_IDE:
423 		case PCI_PRODUCT_INTEL_82801CA_IDE_1:
424 		case PCI_PRODUCT_INTEL_82801CA_IDE_2:
425 		case PCI_PRODUCT_INTEL_82801DB_IDE:
426 		case PCI_PRODUCT_INTEL_82801DBM_IDE:
427 		case PCI_PRODUCT_INTEL_82801EB_IDE:
428 		case PCI_PRODUCT_INTEL_6300ESB_IDE:
429 		case PCI_PRODUCT_INTEL_82801FB_IDE:
430 		case PCI_PRODUCT_INTEL_82801G_IDE:
431 		case PCI_PRODUCT_INTEL_82801HBM_IDE:
432 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
433 		}
434 	}
435 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
436 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
437 	switch(sc->sc_pp->ide_product) {
438 	case PCI_PRODUCT_INTEL_82801AA_IDE:
439 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
440 		break;
441 	case PCI_PRODUCT_INTEL_82801BA_IDE:
442 	case PCI_PRODUCT_INTEL_82801BAM_IDE:
443 	case PCI_PRODUCT_INTEL_82801CA_IDE_1:
444 	case PCI_PRODUCT_INTEL_82801CA_IDE_2:
445 	case PCI_PRODUCT_INTEL_82801DB_IDE:
446 	case PCI_PRODUCT_INTEL_82801DBM_IDE:
447 	case PCI_PRODUCT_INTEL_82801EB_IDE:
448 	case PCI_PRODUCT_INTEL_6300ESB_IDE:
449 	case PCI_PRODUCT_INTEL_82801FB_IDE:
450 	case PCI_PRODUCT_INTEL_82801G_IDE:
451 	case PCI_PRODUCT_INTEL_82801HBM_IDE:
452 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
453 		break;
454 	default:
455 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
456 	}
457 	if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
458 		sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel;
459 	else
460 		sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel;
461 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
462 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
463 
464 	ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
465 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
466 	    DEBUG_PROBE);
467 	if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
468 		ATADEBUG_PRINT((", sidetim=0x%x",
469 		    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
470 		    DEBUG_PROBE);
471 		if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
472 			ATADEBUG_PRINT((", udamreg 0x%x",
473 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
474 			    DEBUG_PROBE);
475 		}
476 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
477 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
478 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
479 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
480 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
481 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
482 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
483 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
484 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
485 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
486 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
487 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
488 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
489 			ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
490 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
491 			    DEBUG_PROBE);
492 		}
493 
494 	}
495 	ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
496 
497 	wdc_allocate_regs(&sc->sc_wdcdev);
498 
499 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
500 	     channel++) {
501 		cp = &sc->pciide_channels[channel];
502 		if (pciide_chansetup(sc, channel, interface) == 0)
503 			continue;
504 		idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
505 		if ((PIIX_IDETIM_READ(idetim, channel) &
506 		    PIIX_IDETIM_IDE) == 0) {
507 #if 1
508 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
509 			    "%s channel ignored (disabled)\n", cp->name);
510 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
511 			continue;
512 #else
513 			pcireg_t interface;
514 
515 			idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
516 			    channel);
517 			pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
518 			    idetim);
519 			interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
520 			    sc->sc_tag, PCI_CLASS_REG));
521 			aprint_normal("channel %d idetim=%08x interface=%02x\n",
522 			    channel, idetim, interface);
523 #endif
524 		}
525 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
526 	}
527 
528 	ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
529 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
530 	    DEBUG_PROBE);
531 	if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
532 		ATADEBUG_PRINT((", sidetim=0x%x",
533 		    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
534 		    DEBUG_PROBE);
535 		if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
536 			ATADEBUG_PRINT((", udamreg 0x%x",
537 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
538 			    DEBUG_PROBE);
539 		}
540 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
541 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
542 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
543 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
544 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
545 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
546 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
547 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
548 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
549 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
550 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
551 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
552 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
553 			ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
554 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
555 			    DEBUG_PROBE);
556 		}
557 	}
558 	ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
559 }
560 
561 static void
562 piix_setup_channel(struct ata_channel *chp)
563 {
564 	u_int8_t mode[2], drive;
565 	u_int32_t oidetim, idetim, idedma_ctl;
566 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
567 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
568 	struct ata_drive_datas *drvp = cp->ata_channel.ch_drive;
569 
570 	oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
571 	idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
572 	idedma_ctl = 0;
573 
574 	/* set up new idetim: Enable IDE registers decode */
575 	idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
576 	    chp->ch_channel);
577 
578 	/* setup DMA */
579 	pciide_channel_dma_setup(cp);
580 
581 	/*
582 	 * Here we have to mess up with drives mode: PIIX can't have
583 	 * different timings for master and slave drives.
584 	 * We need to find the best combination.
585 	 */
586 
587 	/* If both drives supports DMA, take the lower mode */
588 	if ((drvp[0].drive_flags & DRIVE_DMA) &&
589 	    (drvp[1].drive_flags & DRIVE_DMA)) {
590 		mode[0] = mode[1] =
591 		    min(drvp[0].DMA_mode, drvp[1].DMA_mode);
592 		    drvp[0].DMA_mode = mode[0];
593 		    drvp[1].DMA_mode = mode[1];
594 		goto ok;
595 	}
596 	/*
597 	 * If only one drive supports DMA, use its mode, and
598 	 * put the other one in PIO mode 0 if mode not compatible
599 	 */
600 	if (drvp[0].drive_flags & DRIVE_DMA) {
601 		mode[0] = drvp[0].DMA_mode;
602 		mode[1] = drvp[1].PIO_mode;
603 		if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
604 		    piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
605 			mode[1] = drvp[1].PIO_mode = 0;
606 		goto ok;
607 	}
608 	if (drvp[1].drive_flags & DRIVE_DMA) {
609 		mode[1] = drvp[1].DMA_mode;
610 		mode[0] = drvp[0].PIO_mode;
611 		if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
612 		    piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
613 			mode[0] = drvp[0].PIO_mode = 0;
614 		goto ok;
615 	}
616 	/*
617 	 * If both drives are not DMA, takes the lower mode, unless
618 	 * one of them is PIO mode < 2
619 	 */
620 	if (drvp[0].PIO_mode < 2) {
621 		mode[0] = drvp[0].PIO_mode = 0;
622 		mode[1] = drvp[1].PIO_mode;
623 	} else if (drvp[1].PIO_mode < 2) {
624 		mode[1] = drvp[1].PIO_mode = 0;
625 		mode[0] = drvp[0].PIO_mode;
626 	} else {
627 		mode[0] = mode[1] =
628 		    min(drvp[1].PIO_mode, drvp[0].PIO_mode);
629 		drvp[0].PIO_mode = mode[0];
630 		drvp[1].PIO_mode = mode[1];
631 	}
632 ok:	/* The modes are setup */
633 	for (drive = 0; drive < 2; drive++) {
634 		if (drvp[drive].drive_flags & DRIVE_DMA) {
635 			idetim |= piix_setup_idetim_timings(
636 			    mode[drive], 1, chp->ch_channel);
637 			goto end;
638 		}
639 	}
640 	/* If we are there, none of the drives are DMA */
641 	if (mode[0] >= 2)
642 		idetim |= piix_setup_idetim_timings(
643 		    mode[0], 0, chp->ch_channel);
644 	else
645 		idetim |= piix_setup_idetim_timings(
646 		    mode[1], 0, chp->ch_channel);
647 end:	/*
648 	 * timing mode is now set up in the controller. Enable
649 	 * it per-drive
650 	 */
651 	for (drive = 0; drive < 2; drive++) {
652 		/* If no drive, skip */
653 		if ((drvp[drive].drive_flags & DRIVE) == 0)
654 			continue;
655 		idetim |= piix_setup_idetim_drvs(&drvp[drive]);
656 		if (drvp[drive].drive_flags & DRIVE_DMA)
657 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
658 	}
659 	if (idedma_ctl != 0) {
660 		/* Add software bits in status register */
661 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
662 		    idedma_ctl);
663 	}
664 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
665 }
666 
667 static void
668 piix3_4_setup_channel(struct ata_channel *chp)
669 {
670 	struct ata_drive_datas *drvp;
671 	u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
672 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
673 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
674 	struct wdc_softc *wdc = &sc->sc_wdcdev;
675 	int drive, s;
676 	int channel = chp->ch_channel;
677 
678 	oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
679 	sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
680 	udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
681 	ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
682 	idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
683 	sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
684 	    PIIX_SIDETIM_RTC_MASK(channel));
685 	idedma_ctl = 0;
686 
687 	/* set up new idetim: Enable IDE registers decode */
688 	idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
689 
690 	/* setup DMA if needed */
691 	pciide_channel_dma_setup(cp);
692 
693 	for (drive = 0; drive < 2; drive++) {
694 		udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
695 		    PIIX_UDMATIM_SET(0x3, channel, drive));
696 		drvp = &chp->ch_drive[drive];
697 		/* If no drive, skip */
698 		if ((drvp->drive_flags & DRIVE) == 0)
699 			continue;
700 		if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
701 		    (drvp->drive_flags & DRIVE_UDMA) == 0))
702 			goto pio;
703 
704 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
705 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
706 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
707 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
708 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
709 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
710 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
711 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
712 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
713 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
714 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
715 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
716 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
717 			ideconf |= PIIX_CONFIG_PINGPONG;
718 		}
719 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
720 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
721 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
722 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
723 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
724 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
725 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
726 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
727 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
728 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
729 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
730 			/* setup Ultra/100 */
731 			if (drvp->UDMA_mode > 2 &&
732 			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
733 				drvp->UDMA_mode = 2;
734 			if (drvp->UDMA_mode > 4) {
735 				ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
736 			} else {
737 				ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
738 				if (drvp->UDMA_mode > 2) {
739 					ideconf |= PIIX_CONFIG_UDMA66(channel,
740 					    drive);
741 				} else {
742 					ideconf &= ~PIIX_CONFIG_UDMA66(channel,
743 					    drive);
744 				}
745 			}
746 		}
747 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
748 			/* setup Ultra/66 */
749 			if (drvp->UDMA_mode > 2 &&
750 			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
751 				drvp->UDMA_mode = 2;
752 			if (drvp->UDMA_mode > 2)
753 				ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
754 			else
755 				ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
756 		}
757 		if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) &&
758 		    (drvp->drive_flags & DRIVE_UDMA)) {
759 			/* use Ultra/DMA */
760 			s = splbio();
761 			drvp->drive_flags &= ~DRIVE_DMA;
762 			splx(s);
763 			udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
764 			udmareg |= PIIX_UDMATIM_SET(
765 			    piix4_sct_udma[drvp->UDMA_mode], channel, drive);
766 		} else {
767 			/* use Multiword DMA */
768 			s = splbio();
769 			drvp->drive_flags &= ~DRIVE_UDMA;
770 			splx(s);
771 			if (drive == 0) {
772 				idetim |= piix_setup_idetim_timings(
773 				    drvp->DMA_mode, 1, channel);
774 			} else {
775 				sidetim |= piix_setup_sidetim_timings(
776 					drvp->DMA_mode, 1, channel);
777 				idetim =PIIX_IDETIM_SET(idetim,
778 				    PIIX_IDETIM_SITRE, channel);
779 			}
780 		}
781 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
782 
783 pio:		/* use PIO mode */
784 		idetim |= piix_setup_idetim_drvs(drvp);
785 		if (drive == 0) {
786 			idetim |= piix_setup_idetim_timings(
787 			    drvp->PIO_mode, 0, channel);
788 		} else {
789 			sidetim |= piix_setup_sidetim_timings(
790 				drvp->PIO_mode, 0, channel);
791 			idetim =PIIX_IDETIM_SET(idetim,
792 			    PIIX_IDETIM_SITRE, channel);
793 		}
794 	}
795 	if (idedma_ctl != 0) {
796 		/* Add software bits in status register */
797 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
798 		    idedma_ctl);
799 	}
800 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
801 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
802 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
803 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
804 }
805 
806 
807 /* setup ISP and RTC fields, based on mode */
808 static u_int32_t
809 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
810 {
811 
812 	if (dma)
813 		return PIIX_IDETIM_SET(0,
814 		    PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
815 		    PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
816 		    channel);
817 	else
818 		return PIIX_IDETIM_SET(0,
819 		    PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
820 		    PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
821 		    channel);
822 }
823 
824 /* setup DTE, PPE, IE and TIME field based on PIO mode */
825 static u_int32_t
826 piix_setup_idetim_drvs(struct ata_drive_datas *drvp)
827 {
828 	u_int32_t ret = 0;
829 	struct ata_channel *chp = drvp->chnl_softc;
830 	u_int8_t channel = chp->ch_channel;
831 	u_int8_t drive = drvp->drive;
832 
833 	/*
834 	 * If drive is using UDMA, timings setups are independent
835 	 * So just check DMA and PIO here.
836 	 */
837 	if (drvp->drive_flags & DRIVE_DMA) {
838 		/* if mode = DMA mode 0, use compatible timings */
839 		if ((drvp->drive_flags & DRIVE_DMA) &&
840 		    drvp->DMA_mode == 0) {
841 			drvp->PIO_mode = 0;
842 			return ret;
843 		}
844 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
845 		/*
846 		 * PIO and DMA timings are the same, use fast timings for PIO
847 		 * too, else use compat timings.
848 		 */
849 		if ((piix_isp_pio[drvp->PIO_mode] !=
850 		    piix_isp_dma[drvp->DMA_mode]) ||
851 		    (piix_rtc_pio[drvp->PIO_mode] !=
852 		    piix_rtc_dma[drvp->DMA_mode]))
853 			drvp->PIO_mode = 0;
854 		/* if PIO mode <= 2, use compat timings for PIO */
855 		if (drvp->PIO_mode <= 2) {
856 			ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
857 			    channel);
858 			return ret;
859 		}
860 	}
861 
862 	/*
863 	 * Now setup PIO modes. If mode < 2, use compat timings.
864 	 * Else enable fast timings. Enable IORDY and prefetch/post
865 	 * if PIO mode >= 3.
866 	 */
867 
868 	if (drvp->PIO_mode < 2)
869 		return ret;
870 
871 	ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
872 	if (drvp->PIO_mode >= 3) {
873 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
874 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
875 	}
876 	return ret;
877 }
878 
879 /* setup values in SIDETIM registers, based on mode */
880 static u_int32_t
881 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
882 {
883 	if (dma)
884 		return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
885 		    PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel);
886 	else
887 		return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
888 		    PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
889 }
890 
891 static void
892 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
893 {
894 	struct pciide_channel *cp;
895 	pcireg_t interface, cmdsts;
896 	int channel;
897 
898 	if (pciide_chipen(sc, pa) == 0)
899 		return;
900 
901 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
902 	    "bus-master DMA support present");
903 	pciide_mapreg_dma(sc, pa);
904 	aprint_verbose("\n");
905 
906 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
907 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
908 	if (sc->sc_dma_ok) {
909 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
910 		sc->sc_wdcdev.irqack = pciide_irqack;
911 		/* Do all revisions require DMA alignment workaround? */
912 		sc->sc_wdcdev.dma_init = piix_dma_init;
913 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
914 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
915 	}
916 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
917 
918 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
919 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
920 
921 	cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
922 	cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE;
923 	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
924 
925 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
926 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
927 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
928 
929 	interface = PCI_INTERFACE(pa->pa_class);
930 
931 	wdc_allocate_regs(&sc->sc_wdcdev);
932 
933 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
934 	     channel++) {
935 		cp = &sc->pciide_channels[channel];
936 		if (pciide_chansetup(sc, channel, interface) == 0)
937 			continue;
938 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
939 	}
940 }
941 
942 static int
943 piix_dma_init(void *v, int channel, int drive, void *databuf,
944     size_t datalen, int flags)
945 {
946 
947 	/* use PIO for unaligned transfer */
948 	if (((uintptr_t)databuf) & 0x1)
949 		return EINVAL;
950 
951 	return pciide_dma_init(v, channel, drive, databuf, datalen, flags);
952 }
953