1 /* $NetBSD: piixide.c,v 1.22 2005/06/20 02:10:18 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.22 2005/06/20 02:10:18 briggs Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { 0, 173 0, 174 NULL, 175 NULL 176 } 177 }; 178 179 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 180 piixide_match, piixide_attach, NULL, NULL); 181 182 static int 183 piixide_match(struct device *parent, struct cfdata *match, void *aux) 184 { 185 struct pci_attach_args *pa = aux; 186 187 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 188 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 189 return (2); 190 } 191 return (0); 192 } 193 194 static void 195 piixide_attach(struct device *parent, struct device *self, void *aux) 196 { 197 struct pci_attach_args *pa = aux; 198 struct pciide_softc *sc = (struct pciide_softc *)self; 199 200 pciide_common_attach(sc, pa, 201 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 202 203 /* Setup our powerhook */ 204 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 205 if (sc->sc_powerhook == NULL) 206 printf("%s: WARNING: unable to establish PCI power hook\n", 207 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 208 } 209 210 static void 211 piixide_powerhook(int why, void *hdl) 212 { 213 struct pciide_softc *sc = (struct pciide_softc *)hdl; 214 215 switch (why) { 216 case PWR_SUSPEND: 217 case PWR_STANDBY: 218 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 219 break; 220 case PWR_RESUME: 221 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 222 break; 223 case PWR_SOFTSUSPEND: 224 case PWR_SOFTSTANDBY: 225 case PWR_SOFTRESUME: 226 break; 227 } 228 229 return; 230 } 231 232 static void 233 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 234 { 235 struct pciide_channel *cp; 236 int channel; 237 u_int32_t idetim; 238 bus_size_t cmdsize, ctlsize; 239 240 if (pciide_chipen(sc, pa) == 0) 241 return; 242 243 aprint_normal("%s: bus-master DMA support present", 244 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 245 pciide_mapreg_dma(sc, pa); 246 aprint_normal("\n"); 247 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 248 if (sc->sc_dma_ok) { 249 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 250 sc->sc_wdcdev.irqack = pciide_irqack; 251 switch(sc->sc_pp->ide_product) { 252 case PCI_PRODUCT_INTEL_82371AB_IDE: 253 case PCI_PRODUCT_INTEL_82440MX_IDE: 254 case PCI_PRODUCT_INTEL_82801AA_IDE: 255 case PCI_PRODUCT_INTEL_82801AB_IDE: 256 case PCI_PRODUCT_INTEL_82801BA_IDE: 257 case PCI_PRODUCT_INTEL_82801BAM_IDE: 258 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 259 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 260 case PCI_PRODUCT_INTEL_82801DB_IDE: 261 case PCI_PRODUCT_INTEL_82801DBM_IDE: 262 case PCI_PRODUCT_INTEL_82801EB_IDE: 263 case PCI_PRODUCT_INTEL_6300ESB_IDE: 264 case PCI_PRODUCT_INTEL_82801FB_IDE: 265 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 266 } 267 } 268 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 269 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 270 switch(sc->sc_pp->ide_product) { 271 case PCI_PRODUCT_INTEL_82801AA_IDE: 272 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 273 break; 274 case PCI_PRODUCT_INTEL_82801BA_IDE: 275 case PCI_PRODUCT_INTEL_82801BAM_IDE: 276 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 277 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 278 case PCI_PRODUCT_INTEL_82801DB_IDE: 279 case PCI_PRODUCT_INTEL_82801DBM_IDE: 280 case PCI_PRODUCT_INTEL_82801EB_IDE: 281 case PCI_PRODUCT_INTEL_6300ESB_IDE: 282 case PCI_PRODUCT_INTEL_82801FB_IDE: 283 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 284 break; 285 default: 286 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 287 } 288 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 289 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 290 else 291 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 292 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 293 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 294 295 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 296 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 297 DEBUG_PROBE); 298 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 299 ATADEBUG_PRINT((", sidetim=0x%x", 300 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 301 DEBUG_PROBE); 302 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 303 ATADEBUG_PRINT((", udamreg 0x%x", 304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 305 DEBUG_PROBE); 306 } 307 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 308 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 309 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 310 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 311 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 312 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 313 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 314 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 315 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 316 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 317 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 318 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 319 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 320 DEBUG_PROBE); 321 } 322 323 } 324 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 325 326 wdc_allocate_regs(&sc->sc_wdcdev); 327 328 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 329 channel++) { 330 cp = &sc->pciide_channels[channel]; 331 /* PIIX is compat-only */ 332 if (pciide_chansetup(sc, channel, 0) == 0) 333 continue; 334 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 335 if ((PIIX_IDETIM_READ(idetim, channel) & 336 PIIX_IDETIM_IDE) == 0) { 337 #if 1 338 aprint_normal("%s: %s channel ignored (disabled)\n", 339 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 340 cp->ata_channel.ch_flags |= ATACH_DISABLED; 341 continue; 342 #else 343 pcireg_t interface; 344 345 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 346 channel); 347 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 348 idetim); 349 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 350 sc->sc_tag, PCI_CLASS_REG)); 351 aprint_normal("channel %d idetim=%08x interface=%02x\n", 352 channel, idetim, interface); 353 #endif 354 } 355 /* PIIX are compat-only pciide devices */ 356 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 357 } 358 359 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 360 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 361 DEBUG_PROBE); 362 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 363 ATADEBUG_PRINT((", sidetim=0x%x", 364 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 365 DEBUG_PROBE); 366 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 367 ATADEBUG_PRINT((", udamreg 0x%x", 368 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 369 DEBUG_PROBE); 370 } 371 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 372 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 373 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 374 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 375 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 376 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 377 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 378 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 379 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 380 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 381 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 382 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 383 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 384 DEBUG_PROBE); 385 } 386 } 387 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 388 } 389 390 static void 391 piix_setup_channel(struct ata_channel *chp) 392 { 393 u_int8_t mode[2], drive; 394 u_int32_t oidetim, idetim, idedma_ctl; 395 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 396 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 397 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 398 399 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 400 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 401 idedma_ctl = 0; 402 403 /* set up new idetim: Enable IDE registers decode */ 404 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 405 chp->ch_channel); 406 407 /* setup DMA */ 408 pciide_channel_dma_setup(cp); 409 410 /* 411 * Here we have to mess up with drives mode: PIIX can't have 412 * different timings for master and slave drives. 413 * We need to find the best combination. 414 */ 415 416 /* If both drives supports DMA, take the lower mode */ 417 if ((drvp[0].drive_flags & DRIVE_DMA) && 418 (drvp[1].drive_flags & DRIVE_DMA)) { 419 mode[0] = mode[1] = 420 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 421 drvp[0].DMA_mode = mode[0]; 422 drvp[1].DMA_mode = mode[1]; 423 goto ok; 424 } 425 /* 426 * If only one drive supports DMA, use its mode, and 427 * put the other one in PIO mode 0 if mode not compatible 428 */ 429 if (drvp[0].drive_flags & DRIVE_DMA) { 430 mode[0] = drvp[0].DMA_mode; 431 mode[1] = drvp[1].PIO_mode; 432 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 433 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 434 mode[1] = drvp[1].PIO_mode = 0; 435 goto ok; 436 } 437 if (drvp[1].drive_flags & DRIVE_DMA) { 438 mode[1] = drvp[1].DMA_mode; 439 mode[0] = drvp[0].PIO_mode; 440 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 441 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 442 mode[0] = drvp[0].PIO_mode = 0; 443 goto ok; 444 } 445 /* 446 * If both drives are not DMA, takes the lower mode, unless 447 * one of them is PIO mode < 2 448 */ 449 if (drvp[0].PIO_mode < 2) { 450 mode[0] = drvp[0].PIO_mode = 0; 451 mode[1] = drvp[1].PIO_mode; 452 } else if (drvp[1].PIO_mode < 2) { 453 mode[1] = drvp[1].PIO_mode = 0; 454 mode[0] = drvp[0].PIO_mode; 455 } else { 456 mode[0] = mode[1] = 457 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 458 drvp[0].PIO_mode = mode[0]; 459 drvp[1].PIO_mode = mode[1]; 460 } 461 ok: /* The modes are setup */ 462 for (drive = 0; drive < 2; drive++) { 463 if (drvp[drive].drive_flags & DRIVE_DMA) { 464 idetim |= piix_setup_idetim_timings( 465 mode[drive], 1, chp->ch_channel); 466 goto end; 467 } 468 } 469 /* If we are there, none of the drives are DMA */ 470 if (mode[0] >= 2) 471 idetim |= piix_setup_idetim_timings( 472 mode[0], 0, chp->ch_channel); 473 else 474 idetim |= piix_setup_idetim_timings( 475 mode[1], 0, chp->ch_channel); 476 end: /* 477 * timing mode is now set up in the controller. Enable 478 * it per-drive 479 */ 480 for (drive = 0; drive < 2; drive++) { 481 /* If no drive, skip */ 482 if ((drvp[drive].drive_flags & DRIVE) == 0) 483 continue; 484 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 485 if (drvp[drive].drive_flags & DRIVE_DMA) 486 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 487 } 488 if (idedma_ctl != 0) { 489 /* Add software bits in status register */ 490 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 491 idedma_ctl); 492 } 493 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 494 } 495 496 static void 497 piix3_4_setup_channel(struct ata_channel *chp) 498 { 499 struct ata_drive_datas *drvp; 500 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 501 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 502 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 503 struct wdc_softc *wdc = &sc->sc_wdcdev; 504 int drive, s; 505 int channel = chp->ch_channel; 506 507 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 508 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 509 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 510 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 511 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 512 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 513 PIIX_SIDETIM_RTC_MASK(channel)); 514 idedma_ctl = 0; 515 516 /* set up new idetim: Enable IDE registers decode */ 517 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 518 519 /* setup DMA if needed */ 520 pciide_channel_dma_setup(cp); 521 522 for (drive = 0; drive < 2; drive++) { 523 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 524 PIIX_UDMATIM_SET(0x3, channel, drive)); 525 drvp = &chp->ch_drive[drive]; 526 /* If no drive, skip */ 527 if ((drvp->drive_flags & DRIVE) == 0) 528 continue; 529 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 530 (drvp->drive_flags & DRIVE_UDMA) == 0)) 531 goto pio; 532 533 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 534 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 535 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 536 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 537 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 538 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 539 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 540 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 541 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 542 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 543 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 544 ideconf |= PIIX_CONFIG_PINGPONG; 545 } 546 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 555 /* setup Ultra/100 */ 556 if (drvp->UDMA_mode > 2 && 557 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 558 drvp->UDMA_mode = 2; 559 if (drvp->UDMA_mode > 4) { 560 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 561 } else { 562 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 563 if (drvp->UDMA_mode > 2) { 564 ideconf |= PIIX_CONFIG_UDMA66(channel, 565 drive); 566 } else { 567 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 568 drive); 569 } 570 } 571 } 572 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 573 /* setup Ultra/66 */ 574 if (drvp->UDMA_mode > 2 && 575 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 576 drvp->UDMA_mode = 2; 577 if (drvp->UDMA_mode > 2) 578 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 579 else 580 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 581 } 582 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 583 (drvp->drive_flags & DRIVE_UDMA)) { 584 /* use Ultra/DMA */ 585 s = splbio(); 586 drvp->drive_flags &= ~DRIVE_DMA; 587 splx(s); 588 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 589 udmareg |= PIIX_UDMATIM_SET( 590 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 591 } else { 592 /* use Multiword DMA */ 593 s = splbio(); 594 drvp->drive_flags &= ~DRIVE_UDMA; 595 splx(s); 596 if (drive == 0) { 597 idetim |= piix_setup_idetim_timings( 598 drvp->DMA_mode, 1, channel); 599 } else { 600 sidetim |= piix_setup_sidetim_timings( 601 drvp->DMA_mode, 1, channel); 602 idetim =PIIX_IDETIM_SET(idetim, 603 PIIX_IDETIM_SITRE, channel); 604 } 605 } 606 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 607 608 pio: /* use PIO mode */ 609 idetim |= piix_setup_idetim_drvs(drvp); 610 if (drive == 0) { 611 idetim |= piix_setup_idetim_timings( 612 drvp->PIO_mode, 0, channel); 613 } else { 614 sidetim |= piix_setup_sidetim_timings( 615 drvp->PIO_mode, 0, channel); 616 idetim =PIIX_IDETIM_SET(idetim, 617 PIIX_IDETIM_SITRE, channel); 618 } 619 } 620 if (idedma_ctl != 0) { 621 /* Add software bits in status register */ 622 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 623 idedma_ctl); 624 } 625 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 626 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 627 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 628 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 629 } 630 631 632 /* setup ISP and RTC fields, based on mode */ 633 static u_int32_t 634 piix_setup_idetim_timings(mode, dma, channel) 635 u_int8_t mode; 636 u_int8_t dma; 637 u_int8_t channel; 638 { 639 640 if (dma) 641 return PIIX_IDETIM_SET(0, 642 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 643 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 644 channel); 645 else 646 return PIIX_IDETIM_SET(0, 647 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 648 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 649 channel); 650 } 651 652 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 653 static u_int32_t 654 piix_setup_idetim_drvs(drvp) 655 struct ata_drive_datas *drvp; 656 { 657 u_int32_t ret = 0; 658 struct ata_channel *chp = drvp->chnl_softc; 659 u_int8_t channel = chp->ch_channel; 660 u_int8_t drive = drvp->drive; 661 662 /* 663 * If drive is using UDMA, timings setups are independant 664 * So just check DMA and PIO here. 665 */ 666 if (drvp->drive_flags & DRIVE_DMA) { 667 /* if mode = DMA mode 0, use compatible timings */ 668 if ((drvp->drive_flags & DRIVE_DMA) && 669 drvp->DMA_mode == 0) { 670 drvp->PIO_mode = 0; 671 return ret; 672 } 673 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 674 /* 675 * PIO and DMA timings are the same, use fast timings for PIO 676 * too, else use compat timings. 677 */ 678 if ((piix_isp_pio[drvp->PIO_mode] != 679 piix_isp_dma[drvp->DMA_mode]) || 680 (piix_rtc_pio[drvp->PIO_mode] != 681 piix_rtc_dma[drvp->DMA_mode])) 682 drvp->PIO_mode = 0; 683 /* if PIO mode <= 2, use compat timings for PIO */ 684 if (drvp->PIO_mode <= 2) { 685 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 686 channel); 687 return ret; 688 } 689 } 690 691 /* 692 * Now setup PIO modes. If mode < 2, use compat timings. 693 * Else enable fast timings. Enable IORDY and prefetch/post 694 * if PIO mode >= 3. 695 */ 696 697 if (drvp->PIO_mode < 2) 698 return ret; 699 700 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 701 if (drvp->PIO_mode >= 3) { 702 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 703 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 704 } 705 return ret; 706 } 707 708 /* setup values in SIDETIM registers, based on mode */ 709 static u_int32_t 710 piix_setup_sidetim_timings(mode, dma, channel) 711 u_int8_t mode; 712 u_int8_t dma; 713 u_int8_t channel; 714 { 715 if (dma) 716 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 717 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 718 else 719 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 720 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 721 } 722 723 static void 724 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 725 { 726 struct pciide_channel *cp; 727 bus_size_t cmdsize, ctlsize; 728 pcireg_t interface, cmdsts; 729 int channel; 730 731 if (pciide_chipen(sc, pa) == 0) 732 return; 733 734 aprint_normal("%s: bus-master DMA support present", 735 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 736 pciide_mapreg_dma(sc, pa); 737 aprint_normal("\n"); 738 739 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 740 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 741 if (sc->sc_dma_ok) { 742 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 743 sc->sc_wdcdev.irqack = pciide_irqack; 744 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 745 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 746 } 747 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 748 749 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 750 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 751 752 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 753 cmdsts &= ~0x0400; 754 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 755 756 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 757 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 758 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 759 760 interface = PCI_INTERFACE(pa->pa_class); 761 762 wdc_allocate_regs(&sc->sc_wdcdev); 763 764 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 765 channel++) { 766 cp = &sc->pciide_channels[channel]; 767 if (pciide_chansetup(sc, channel, interface) == 0) 768 continue; 769 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 770 pciide_pci_intr); 771 } 772 } 773