1 /* $NetBSD: piixide.c,v 1.58 2012/03/05 16:21:44 sborrill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.58 2012/03/05 16:21:44 sborrill Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_piix_reg.h> 38 39 static void piix_chip_map(struct pciide_softc*, 40 const struct pci_attach_args *); 41 static void piix_setup_channel(struct ata_channel *); 42 static void piix3_4_setup_channel(struct ata_channel *); 43 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 44 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 45 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 46 static void piixsata_chip_map(struct pciide_softc*, 47 const struct pci_attach_args *); 48 static int piix_dma_init(void *, int, int, void *, size_t, int); 49 50 static bool piixide_resume(device_t, const pmf_qual_t *); 51 static bool piixide_suspend(device_t, const pmf_qual_t *); 52 static int piixide_match(device_t, cfdata_t, void *); 53 static void piixide_attach(device_t, device_t, void *); 54 55 static const struct pciide_product_desc pciide_intel_products[] = { 56 { PCI_PRODUCT_INTEL_82092AA, 57 0, 58 "Intel 82092AA IDE controller", 59 default_chip_map, 60 }, 61 { PCI_PRODUCT_INTEL_82371FB_IDE, 62 0, 63 "Intel 82371FB IDE controller (PIIX)", 64 piix_chip_map, 65 }, 66 { PCI_PRODUCT_INTEL_82371SB_IDE, 67 0, 68 "Intel 82371SB IDE Interface (PIIX3)", 69 piix_chip_map, 70 }, 71 { PCI_PRODUCT_INTEL_82371AB_IDE, 72 0, 73 "Intel 82371AB IDE controller (PIIX4)", 74 piix_chip_map, 75 }, 76 { PCI_PRODUCT_INTEL_82440MX_IDE, 77 0, 78 "Intel 82440MX IDE controller", 79 piix_chip_map 80 }, 81 { PCI_PRODUCT_INTEL_82801AA_IDE, 82 0, 83 "Intel 82801AA IDE Controller (ICH)", 84 piix_chip_map, 85 }, 86 { PCI_PRODUCT_INTEL_82801AB_IDE, 87 0, 88 "Intel 82801AB IDE Controller (ICH0)", 89 piix_chip_map, 90 }, 91 { PCI_PRODUCT_INTEL_82801BA_IDE, 92 0, 93 "Intel 82801BA IDE Controller (ICH2)", 94 piix_chip_map, 95 }, 96 { PCI_PRODUCT_INTEL_82801BAM_IDE, 97 0, 98 "Intel 82801BAM IDE Controller (ICH2-M)", 99 piix_chip_map, 100 }, 101 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 102 0, 103 "Intel 82801CA IDE Controller (ICH3)", 104 piix_chip_map, 105 }, 106 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 107 0, 108 "Intel 82801CA IDE Controller (ICH3)", 109 piix_chip_map, 110 }, 111 { PCI_PRODUCT_INTEL_82801DB_IDE, 112 0, 113 "Intel 82801DB IDE Controller (ICH4)", 114 piix_chip_map, 115 }, 116 { PCI_PRODUCT_INTEL_82801DBM_IDE, 117 0, 118 "Intel 82801DBM IDE Controller (ICH4-M)", 119 piix_chip_map, 120 }, 121 { PCI_PRODUCT_INTEL_82801EB_IDE, 122 0, 123 "Intel 82801EB IDE Controller (ICH5)", 124 piix_chip_map, 125 }, 126 { PCI_PRODUCT_INTEL_82801EB_SATA, 127 0, 128 "Intel 82801EB Serial ATA Controller", 129 piixsata_chip_map, 130 }, 131 { PCI_PRODUCT_INTEL_82801ER_SATA, 132 0, 133 "Intel 82801ER Serial ATA/Raid Controller", 134 piixsata_chip_map, 135 }, 136 { PCI_PRODUCT_INTEL_6300ESB_IDE, 137 0, 138 "Intel 6300ESB IDE Controller (ICH5)", 139 piix_chip_map, 140 }, 141 { PCI_PRODUCT_INTEL_6300ESB_SATA, 142 0, 143 "Intel 6300ESB Serial ATA Controller", 144 piixsata_chip_map, 145 }, 146 { PCI_PRODUCT_INTEL_6300ESB_RAID, 147 0, 148 "Intel 6300ESB Serial ATA/RAID Controller", 149 piixsata_chip_map, 150 }, 151 { PCI_PRODUCT_INTEL_82801FB_IDE, 152 0, 153 "Intel 82801FB IDE Controller (ICH6)", 154 piix_chip_map, 155 }, 156 { PCI_PRODUCT_INTEL_82801FB_SATA, 157 0, 158 "Intel 82801FB Serial ATA/Raid Controller", 159 piixsata_chip_map, 160 }, 161 { PCI_PRODUCT_INTEL_82801FR_SATA, 162 0, 163 "Intel 82801FR Serial ATA/Raid Controller", 164 piixsata_chip_map, 165 }, 166 { PCI_PRODUCT_INTEL_82801FBM_SATA, 167 0, 168 "Intel 82801FBM Serial ATA Controller (ICH6)", 169 piixsata_chip_map, 170 }, 171 { PCI_PRODUCT_INTEL_82801G_IDE, 172 0, 173 "Intel 82801GB/GR IDE Controller (ICH7)", 174 piix_chip_map, 175 }, 176 { PCI_PRODUCT_INTEL_82801G_SATA, 177 0, 178 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 179 piixsata_chip_map, 180 }, 181 { PCI_PRODUCT_INTEL_82801GBM_SATA, 182 0, 183 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 184 piixsata_chip_map, 185 }, 186 { PCI_PRODUCT_INTEL_82801H_SATA_1, 187 0, 188 "Intel 82801H Serial ATA Controller (ICH8)", 189 piixsata_chip_map, 190 }, 191 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 192 0, 193 "Intel 82801H Serial ATA RAID Controller (ICH8)", 194 piixsata_chip_map, 195 }, 196 { PCI_PRODUCT_INTEL_82801H_SATA_2, 197 0, 198 "Intel 82801H Serial ATA Controller (ICH8)", 199 piixsata_chip_map, 200 }, 201 { PCI_PRODUCT_INTEL_82801HBM_IDE, 202 0, 203 "Intel 82801HBM IDE Controller (ICH8M)", 204 piix_chip_map, 205 }, 206 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 207 0, 208 "Intel 82801HBM Serial ATA Controller (ICH8M)", 209 piixsata_chip_map, 210 }, 211 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 212 0, 213 "Intel 82801HBM Serial ATA Controller (ICH8M)", 214 piixsata_chip_map, 215 }, 216 { PCI_PRODUCT_INTEL_82801HEM_SATA, 217 0, 218 "Intel 82801HEM Serial ATA Controller (ICH8M)", 219 piixsata_chip_map, 220 }, 221 { PCI_PRODUCT_INTEL_63XXESB_IDE, 222 0, 223 "Intel 631xESB/632xESB IDE Controller", 224 piix_chip_map, 225 }, 226 { PCI_PRODUCT_INTEL_82801I_SATA_1, 227 0, 228 "Intel 82801I Serial ATA Controller (ICH9)", 229 piixsata_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82801I_SATA_2, 232 0, 233 "Intel 82801I Serial ATA Controller (ICH9)", 234 piixsata_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82801I_SATA_3, 237 0, 238 "Intel 82801I Serial ATA Controller (ICH9)", 239 piixsata_chip_map, 240 }, 241 { PCI_PRODUCT_INTEL_82801I_SATA_4, 242 0, 243 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 244 piixsata_chip_map, 245 }, 246 { PCI_PRODUCT_INTEL_82801I_SATA_5, 247 0, 248 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 249 piixsata_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82801I_SATA_6, 252 0, 253 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 254 piixsata_chip_map, 255 }, 256 { PCI_PRODUCT_INTEL_82801I_SATA_7, 257 0, 258 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 259 piixsata_chip_map, 260 }, 261 { PCI_PRODUCT_INTEL_63XXESB_SATA, 262 0, 263 "Intel 631xESB/632xESB Serial ATA Controller", 264 piixsata_chip_map, 265 }, 266 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE2, 267 0, 268 "Intel 82801JD Serial ATA Controller (ICH10)", 269 piixsata_chip_map, 270 }, 271 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE2, 272 0, 273 "Intel 82801JI Serial ATA Controller (ICH10)", 274 piixsata_chip_map, 275 }, 276 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE, 277 0, 278 "Intel 82801JD Serial ATA Controller (ICH10)", 279 piixsata_chip_map, 280 }, 281 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE, 282 0, 283 "Intel 82801JI Serial ATA Controller (ICH10)", 284 piixsata_chip_map, 285 }, 286 { 287 PCI_PRODUCT_INTEL_82965PM_IDE, 288 0, 289 "Intel 82965PM IDE controller", 290 piixsata_chip_map, 291 }, 292 { 293 PCI_PRODUCT_INTEL_3400_SATA_1, 294 0, 295 "Intel 3400 Serial ATA Controller", 296 piixsata_chip_map, 297 }, 298 { 299 PCI_PRODUCT_INTEL_3400_SATA_1, 300 0, 301 "Intel 3400 Serial ATA Controller", 302 piixsata_chip_map, 303 }, 304 { 305 PCI_PRODUCT_INTEL_3400_SATA_2, 306 0, 307 "Intel 3400 Serial ATA Controller", 308 piixsata_chip_map, 309 }, 310 { 311 PCI_PRODUCT_INTEL_3400_SATA_3, 312 0, 313 "Intel 3400 Serial ATA Controller", 314 piixsata_chip_map, 315 }, 316 { 317 PCI_PRODUCT_INTEL_3400_SATA_4, 318 0, 319 "Intel 3400 Serial ATA Controller", 320 piixsata_chip_map, 321 }, 322 { 323 PCI_PRODUCT_INTEL_3400_SATA_5, 324 0, 325 "Intel 3400 Serial ATA Controller", 326 piixsata_chip_map, 327 }, 328 { 329 PCI_PRODUCT_INTEL_3400_SATA_6, 330 0, 331 "Intel 3400 Serial ATA Controller", 332 piixsata_chip_map, 333 }, 334 { 335 PCI_PRODUCT_INTEL_6SERIES_SATA_1, 336 0, 337 "Intel 6 Series Serial ATA Controller", 338 piixsata_chip_map, 339 }, 340 { 341 PCI_PRODUCT_INTEL_6SERIES_SATA_2, 342 0, 343 "Intel 6 Series Serial ATA Controller", 344 piixsata_chip_map, 345 }, 346 { 347 PCI_PRODUCT_INTEL_6SERIES_SATA_3, 348 0, 349 "Intel 6 Series Serial ATA Controller", 350 piixsata_chip_map, 351 }, 352 { 353 PCI_PRODUCT_INTEL_6SERIES_SATA_4, 354 0, 355 "Intel 6 Series Serial ATA Controller", 356 piixsata_chip_map, 357 }, 358 { 0, 359 0, 360 NULL, 361 NULL 362 } 363 }; 364 365 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 366 piixide_match, piixide_attach, NULL, NULL); 367 368 static int 369 piixide_match(device_t parent, cfdata_t match, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 373 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 374 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 375 return (2); 376 } 377 return (0); 378 } 379 380 static void 381 piixide_attach(device_t parent, device_t self, void *aux) 382 { 383 struct pci_attach_args *pa = aux; 384 struct pciide_softc *sc = device_private(self); 385 386 sc->sc_wdcdev.sc_atac.atac_dev = self; 387 388 pciide_common_attach(sc, pa, 389 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 390 391 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 392 aprint_error_dev(self, "couldn't establish power handler\n"); 393 } 394 395 static bool 396 piixide_resume(device_t dv, const pmf_qual_t *qual) 397 { 398 struct pciide_softc *sc = device_private(dv); 399 400 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 401 sc->sc_pm_reg[0]); 402 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 403 sc->sc_pm_reg[1]); 404 405 return true; 406 } 407 408 static bool 409 piixide_suspend(device_t dv, const pmf_qual_t *qual) 410 { 411 struct pciide_softc *sc = device_private(dv); 412 413 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 414 PIIX_IDETIM); 415 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 416 PIIX_UDMAREG); 417 418 return true; 419 } 420 421 static void 422 piix_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 423 { 424 struct pciide_channel *cp; 425 int channel; 426 u_int32_t idetim; 427 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 428 429 if (pciide_chipen(sc, pa) == 0) 430 return; 431 432 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 433 "bus-master DMA support present"); 434 pciide_mapreg_dma(sc, pa); 435 aprint_verbose("\n"); 436 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 437 if (sc->sc_dma_ok) { 438 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 439 sc->sc_wdcdev.irqack = pciide_irqack; 440 /* Do all revisions require DMA alignment workaround? */ 441 sc->sc_wdcdev.dma_init = piix_dma_init; 442 switch(sc->sc_pp->ide_product) { 443 case PCI_PRODUCT_INTEL_82371AB_IDE: 444 case PCI_PRODUCT_INTEL_82440MX_IDE: 445 case PCI_PRODUCT_INTEL_82801AA_IDE: 446 case PCI_PRODUCT_INTEL_82801AB_IDE: 447 case PCI_PRODUCT_INTEL_82801BA_IDE: 448 case PCI_PRODUCT_INTEL_82801BAM_IDE: 449 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 450 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 451 case PCI_PRODUCT_INTEL_82801DB_IDE: 452 case PCI_PRODUCT_INTEL_82801DBM_IDE: 453 case PCI_PRODUCT_INTEL_82801EB_IDE: 454 case PCI_PRODUCT_INTEL_6300ESB_IDE: 455 case PCI_PRODUCT_INTEL_82801FB_IDE: 456 case PCI_PRODUCT_INTEL_82801G_IDE: 457 case PCI_PRODUCT_INTEL_82801HBM_IDE: 458 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 459 } 460 } 461 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 462 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 463 switch(sc->sc_pp->ide_product) { 464 case PCI_PRODUCT_INTEL_82801AA_IDE: 465 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 466 break; 467 case PCI_PRODUCT_INTEL_82801BA_IDE: 468 case PCI_PRODUCT_INTEL_82801BAM_IDE: 469 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 470 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 471 case PCI_PRODUCT_INTEL_82801DB_IDE: 472 case PCI_PRODUCT_INTEL_82801DBM_IDE: 473 case PCI_PRODUCT_INTEL_82801EB_IDE: 474 case PCI_PRODUCT_INTEL_6300ESB_IDE: 475 case PCI_PRODUCT_INTEL_82801FB_IDE: 476 case PCI_PRODUCT_INTEL_82801G_IDE: 477 case PCI_PRODUCT_INTEL_82801HBM_IDE: 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 479 break; 480 default: 481 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 482 } 483 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 484 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 485 else 486 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 487 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 488 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 489 490 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 491 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 492 DEBUG_PROBE); 493 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 494 ATADEBUG_PRINT((", sidetim=0x%x", 495 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 496 DEBUG_PROBE); 497 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 498 ATADEBUG_PRINT((", udamreg 0x%x", 499 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 500 DEBUG_PROBE); 501 } 502 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 503 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 504 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 505 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 512 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 513 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 514 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 515 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 516 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 517 DEBUG_PROBE); 518 } 519 520 } 521 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 522 523 wdc_allocate_regs(&sc->sc_wdcdev); 524 525 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 526 channel++) { 527 cp = &sc->pciide_channels[channel]; 528 if (pciide_chansetup(sc, channel, interface) == 0) 529 continue; 530 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 531 if ((PIIX_IDETIM_READ(idetim, channel) & 532 PIIX_IDETIM_IDE) == 0) { 533 #if 1 534 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 535 "%s channel ignored (disabled)\n", cp->name); 536 cp->ata_channel.ch_flags |= ATACH_DISABLED; 537 continue; 538 #else 539 pcireg_t interface; 540 541 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 542 channel); 543 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 544 idetim); 545 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 546 sc->sc_tag, PCI_CLASS_REG)); 547 aprint_normal("channel %d idetim=%08x interface=%02x\n", 548 channel, idetim, interface); 549 #endif 550 } 551 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 552 } 553 554 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 555 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 556 DEBUG_PROBE); 557 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 558 ATADEBUG_PRINT((", sidetim=0x%x", 559 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 560 DEBUG_PROBE); 561 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 562 ATADEBUG_PRINT((", udamreg 0x%x", 563 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 564 DEBUG_PROBE); 565 } 566 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 567 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 568 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 569 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 570 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 571 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 572 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 573 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 574 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 579 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 580 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 581 DEBUG_PROBE); 582 } 583 } 584 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 585 } 586 587 static void 588 piix_setup_channel(struct ata_channel *chp) 589 { 590 u_int8_t mode[2], drive; 591 u_int32_t oidetim, idetim, idedma_ctl; 592 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 593 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 594 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 595 596 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 597 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 598 idedma_ctl = 0; 599 600 /* set up new idetim: Enable IDE registers decode */ 601 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 602 chp->ch_channel); 603 604 /* setup DMA */ 605 pciide_channel_dma_setup(cp); 606 607 /* 608 * Here we have to mess up with drives mode: PIIX can't have 609 * different timings for master and slave drives. 610 * We need to find the best combination. 611 */ 612 613 /* If both drives supports DMA, take the lower mode */ 614 if ((drvp[0].drive_flags & DRIVE_DMA) && 615 (drvp[1].drive_flags & DRIVE_DMA)) { 616 mode[0] = mode[1] = 617 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 618 drvp[0].DMA_mode = mode[0]; 619 drvp[1].DMA_mode = mode[1]; 620 goto ok; 621 } 622 /* 623 * If only one drive supports DMA, use its mode, and 624 * put the other one in PIO mode 0 if mode not compatible 625 */ 626 if (drvp[0].drive_flags & DRIVE_DMA) { 627 mode[0] = drvp[0].DMA_mode; 628 mode[1] = drvp[1].PIO_mode; 629 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 630 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 631 mode[1] = drvp[1].PIO_mode = 0; 632 goto ok; 633 } 634 if (drvp[1].drive_flags & DRIVE_DMA) { 635 mode[1] = drvp[1].DMA_mode; 636 mode[0] = drvp[0].PIO_mode; 637 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 638 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 639 mode[0] = drvp[0].PIO_mode = 0; 640 goto ok; 641 } 642 /* 643 * If both drives are not DMA, takes the lower mode, unless 644 * one of them is PIO mode < 2 645 */ 646 if (drvp[0].PIO_mode < 2) { 647 mode[0] = drvp[0].PIO_mode = 0; 648 mode[1] = drvp[1].PIO_mode; 649 } else if (drvp[1].PIO_mode < 2) { 650 mode[1] = drvp[1].PIO_mode = 0; 651 mode[0] = drvp[0].PIO_mode; 652 } else { 653 mode[0] = mode[1] = 654 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 655 drvp[0].PIO_mode = mode[0]; 656 drvp[1].PIO_mode = mode[1]; 657 } 658 ok: /* The modes are setup */ 659 for (drive = 0; drive < 2; drive++) { 660 if (drvp[drive].drive_flags & DRIVE_DMA) { 661 idetim |= piix_setup_idetim_timings( 662 mode[drive], 1, chp->ch_channel); 663 goto end; 664 } 665 } 666 /* If we are there, none of the drives are DMA */ 667 if (mode[0] >= 2) 668 idetim |= piix_setup_idetim_timings( 669 mode[0], 0, chp->ch_channel); 670 else 671 idetim |= piix_setup_idetim_timings( 672 mode[1], 0, chp->ch_channel); 673 end: /* 674 * timing mode is now set up in the controller. Enable 675 * it per-drive 676 */ 677 for (drive = 0; drive < 2; drive++) { 678 /* If no drive, skip */ 679 if ((drvp[drive].drive_flags & DRIVE) == 0) 680 continue; 681 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 682 if (drvp[drive].drive_flags & DRIVE_DMA) 683 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 684 } 685 if (idedma_ctl != 0) { 686 /* Add software bits in status register */ 687 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 688 idedma_ctl); 689 } 690 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 691 } 692 693 static void 694 piix3_4_setup_channel(struct ata_channel *chp) 695 { 696 struct ata_drive_datas *drvp; 697 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 698 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 699 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 700 struct wdc_softc *wdc = &sc->sc_wdcdev; 701 int drive, s; 702 int channel = chp->ch_channel; 703 704 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 705 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 706 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 707 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 708 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 709 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 710 PIIX_SIDETIM_RTC_MASK(channel)); 711 idedma_ctl = 0; 712 713 /* set up new idetim: Enable IDE registers decode */ 714 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 715 716 /* setup DMA if needed */ 717 pciide_channel_dma_setup(cp); 718 719 for (drive = 0; drive < 2; drive++) { 720 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 721 PIIX_UDMATIM_SET(0x3, channel, drive)); 722 drvp = &chp->ch_drive[drive]; 723 /* If no drive, skip */ 724 if ((drvp->drive_flags & DRIVE) == 0) 725 continue; 726 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 727 (drvp->drive_flags & DRIVE_UDMA) == 0)) 728 goto pio; 729 730 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 731 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 732 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 733 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 734 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 735 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 736 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 737 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 738 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 739 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 740 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 743 ideconf |= PIIX_CONFIG_PINGPONG; 744 } 745 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 746 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 747 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 748 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 749 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 750 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 751 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 752 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 753 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 754 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 755 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 756 /* setup Ultra/100 */ 757 if (drvp->UDMA_mode > 2 && 758 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 759 drvp->UDMA_mode = 2; 760 if (drvp->UDMA_mode > 4) { 761 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 762 } else { 763 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 764 if (drvp->UDMA_mode > 2) { 765 ideconf |= PIIX_CONFIG_UDMA66(channel, 766 drive); 767 } else { 768 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 769 drive); 770 } 771 } 772 } 773 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 774 /* setup Ultra/66 */ 775 if (drvp->UDMA_mode > 2 && 776 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 777 drvp->UDMA_mode = 2; 778 if (drvp->UDMA_mode > 2) 779 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 780 else 781 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 782 } 783 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 784 (drvp->drive_flags & DRIVE_UDMA)) { 785 /* use Ultra/DMA */ 786 s = splbio(); 787 drvp->drive_flags &= ~DRIVE_DMA; 788 splx(s); 789 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 790 udmareg |= PIIX_UDMATIM_SET( 791 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 792 } else { 793 /* use Multiword DMA */ 794 s = splbio(); 795 drvp->drive_flags &= ~DRIVE_UDMA; 796 splx(s); 797 if (drive == 0) { 798 idetim |= piix_setup_idetim_timings( 799 drvp->DMA_mode, 1, channel); 800 } else { 801 sidetim |= piix_setup_sidetim_timings( 802 drvp->DMA_mode, 1, channel); 803 idetim =PIIX_IDETIM_SET(idetim, 804 PIIX_IDETIM_SITRE, channel); 805 } 806 } 807 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 808 809 pio: /* use PIO mode */ 810 idetim |= piix_setup_idetim_drvs(drvp); 811 if (drive == 0) { 812 idetim |= piix_setup_idetim_timings( 813 drvp->PIO_mode, 0, channel); 814 } else { 815 sidetim |= piix_setup_sidetim_timings( 816 drvp->PIO_mode, 0, channel); 817 idetim =PIIX_IDETIM_SET(idetim, 818 PIIX_IDETIM_SITRE, channel); 819 } 820 } 821 if (idedma_ctl != 0) { 822 /* Add software bits in status register */ 823 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 824 idedma_ctl); 825 } 826 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 827 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 828 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 829 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 830 } 831 832 833 /* setup ISP and RTC fields, based on mode */ 834 static u_int32_t 835 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 836 { 837 838 if (dma) 839 return PIIX_IDETIM_SET(0, 840 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 841 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 842 channel); 843 else 844 return PIIX_IDETIM_SET(0, 845 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 846 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 847 channel); 848 } 849 850 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 851 static u_int32_t 852 piix_setup_idetim_drvs(struct ata_drive_datas *drvp) 853 { 854 u_int32_t ret = 0; 855 struct ata_channel *chp = drvp->chnl_softc; 856 u_int8_t channel = chp->ch_channel; 857 u_int8_t drive = drvp->drive; 858 859 /* 860 * If drive is using UDMA, timings setups are independent 861 * So just check DMA and PIO here. 862 */ 863 if (drvp->drive_flags & DRIVE_DMA) { 864 /* if mode = DMA mode 0, use compatible timings */ 865 if ((drvp->drive_flags & DRIVE_DMA) && 866 drvp->DMA_mode == 0) { 867 drvp->PIO_mode = 0; 868 return ret; 869 } 870 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 871 /* 872 * PIO and DMA timings are the same, use fast timings for PIO 873 * too, else use compat timings. 874 */ 875 if ((piix_isp_pio[drvp->PIO_mode] != 876 piix_isp_dma[drvp->DMA_mode]) || 877 (piix_rtc_pio[drvp->PIO_mode] != 878 piix_rtc_dma[drvp->DMA_mode])) 879 drvp->PIO_mode = 0; 880 /* if PIO mode <= 2, use compat timings for PIO */ 881 if (drvp->PIO_mode <= 2) { 882 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 883 channel); 884 return ret; 885 } 886 } 887 888 /* 889 * Now setup PIO modes. If mode < 2, use compat timings. 890 * Else enable fast timings. Enable IORDY and prefetch/post 891 * if PIO mode >= 3. 892 */ 893 894 if (drvp->PIO_mode < 2) 895 return ret; 896 897 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 898 if (drvp->PIO_mode >= 3) { 899 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 900 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 901 } 902 return ret; 903 } 904 905 /* setup values in SIDETIM registers, based on mode */ 906 static u_int32_t 907 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 908 { 909 if (dma) 910 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 911 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 912 else 913 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 914 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 915 } 916 917 static void 918 piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 919 { 920 struct pciide_channel *cp; 921 pcireg_t interface, cmdsts; 922 int channel; 923 924 if (pciide_chipen(sc, pa) == 0) 925 return; 926 927 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 928 "bus-master DMA support present"); 929 pciide_mapreg_dma(sc, pa); 930 aprint_verbose("\n"); 931 932 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 933 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 934 if (sc->sc_dma_ok) { 935 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 936 sc->sc_wdcdev.irqack = pciide_irqack; 937 /* Do all revisions require DMA alignment workaround? */ 938 sc->sc_wdcdev.dma_init = piix_dma_init; 939 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 940 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 941 } 942 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 943 944 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 945 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 946 947 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 948 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 949 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 950 951 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 952 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 953 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 954 955 interface = PCI_INTERFACE(pa->pa_class); 956 957 wdc_allocate_regs(&sc->sc_wdcdev); 958 959 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 960 channel++) { 961 cp = &sc->pciide_channels[channel]; 962 if (pciide_chansetup(sc, channel, interface) == 0) 963 continue; 964 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 965 } 966 } 967 968 static int 969 piix_dma_init(void *v, int channel, int drive, void *databuf, 970 size_t datalen, int flags) 971 { 972 973 /* use PIO for unaligned transfer */ 974 if (((uintptr_t)databuf) & 0x1) 975 return EINVAL; 976 977 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 978 } 979