1*ce099b40Smartin /* $NetBSD: pcscpreg.h,v 1.2 2008/04/28 20:23:55 martin Exp $ */ 2671d0ae8Sthorpej 3671d0ae8Sthorpej /*- 4671d0ae8Sthorpej * Copyright (c) 1998 The NetBSD Foundation, Inc. 5671d0ae8Sthorpej * All rights reserved. 6671d0ae8Sthorpej * 7671d0ae8Sthorpej * This code is derived from software contributed to The NetBSD Foundation 8671d0ae8Sthorpej * by Izumi Tsutsui. 9671d0ae8Sthorpej * 10671d0ae8Sthorpej * Redistribution and use in source and binary forms, with or without 11671d0ae8Sthorpej * modification, are permitted provided that the following conditions 12671d0ae8Sthorpej * are met: 13671d0ae8Sthorpej * 1. Redistributions of source code must retain the above copyright 14671d0ae8Sthorpej * notice, this list of conditions and the following disclaimer. 15671d0ae8Sthorpej * 2. Redistributions in binary form must reproduce the above copyright 16671d0ae8Sthorpej * notice, this list of conditions and the following disclaimer in the 17671d0ae8Sthorpej * documentation and/or other materials provided with the distribution. 18671d0ae8Sthorpej * 19671d0ae8Sthorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20671d0ae8Sthorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21671d0ae8Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22671d0ae8Sthorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23671d0ae8Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24671d0ae8Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25671d0ae8Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26671d0ae8Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27671d0ae8Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28671d0ae8Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29671d0ae8Sthorpej * POSSIBILITY OF SUCH DAMAGE. 30671d0ae8Sthorpej */ 31671d0ae8Sthorpej 32671d0ae8Sthorpej /* 33671d0ae8Sthorpej * Am53c974 DMA engine registers 34671d0ae8Sthorpej */ 35671d0ae8Sthorpej 36671d0ae8Sthorpej #define DMA_CMD 0x40 /* Command */ 37671d0ae8Sthorpej #define DMACMD_RSVD 0xFFFFFF28 /* reserved */ 38671d0ae8Sthorpej #define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */ 39671d0ae8Sthorpej #define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */ 40671d0ae8Sthorpej #define DMACMD_MDL 0x00000010 /* Map to Memory Description List */ 41671d0ae8Sthorpej #define DMACMD_DIAG 0x00000004 /* Diagnostic */ 42671d0ae8Sthorpej #define DMACMD_CMD 0x00000003 /* Command Code Bit */ 43671d0ae8Sthorpej #define DMACMD_IDLE 0x00000000 /* Idle */ 44671d0ae8Sthorpej #define DMACMD_BLAST 0x00000001 /* Blast */ 45671d0ae8Sthorpej #define DMACMD_ABORT 0x00000002 /* Abort */ 46671d0ae8Sthorpej #define DMACMD_START 0x00000003 /* Start */ 47671d0ae8Sthorpej 48671d0ae8Sthorpej #define DMA_STC 0x44 /* Start Transfer Count */ 49671d0ae8Sthorpej #define DMA_SPA 0x48 /* Start Physical Address */ 50671d0ae8Sthorpej #define DMA_WBC 0x4C /* Working Byte Counter */ 51671d0ae8Sthorpej #define DMA_WAC 0x50 /* Working Address Counter */ 52671d0ae8Sthorpej 53671d0ae8Sthorpej #define DMA_STAT 0x54 /* Status Register */ 54671d0ae8Sthorpej #define DMASTAT_RSVD 0xFFFFFF80 /* reserved */ 55671d0ae8Sthorpej #define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */ 56671d0ae8Sthorpej #define DMASTAT_BCMP 0x00000020 /* BLAST Complete */ 57671d0ae8Sthorpej #define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */ 58671d0ae8Sthorpej #define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */ 59671d0ae8Sthorpej #define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */ 60671d0ae8Sthorpej #define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */ 61671d0ae8Sthorpej #define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */ 62671d0ae8Sthorpej 63671d0ae8Sthorpej #define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */ 64671d0ae8Sthorpej #define DMA_WMAC 0x5C /* Working MDL Counter */ 65671d0ae8Sthorpej #define DMA_SBAC 0x70 /* SCSI Bus and Control */ 66